arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  *
   7  * Mingkai Hu <mingkai.hu@nxp.com>
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "fsl,ls1046a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 crypto = &crypto;
  21                 fman0 = &fman0;
  22                 ethernet0 = &enet0;
  23                 ethernet1 = &enet1;
  24                 ethernet2 = &enet2;
  25                 ethernet3 = &enet3;
  26                 ethernet4 = &enet4;
  27                 ethernet5 = &enet5;
  28                 ethernet6 = &enet6;
  29                 ethernet7 = &enet7;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a72";
  39                         reg = <0x0>;
  40                         clocks = <&clockgen 1 0>;
  41                         next-level-cache = <&l2>;
  42                         cpu-idle-states = <&CPU_PH20>;
  43                         #cooling-cells = <2>;
  44                 };
  45
  46                 cpu1: cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a72";
  49                         reg = <0x1>;
  50                         clocks = <&clockgen 1 0>;
  51                         next-level-cache = <&l2>;
  52                         cpu-idle-states = <&CPU_PH20>;
  53                         #cooling-cells = <2>;
  54                 };
  55
  56                 cpu2: cpu@2 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a72";
  59                         reg = <0x2>;
  60                         clocks = <&clockgen 1 0>;
  61                         next-level-cache = <&l2>;
  62                         cpu-idle-states = <&CPU_PH20>;
  63                         #cooling-cells = <2>;
  64                 };
  65
  66                 cpu3: cpu@3 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a72";
  69                         reg = <0x3>;
  70                         clocks = <&clockgen 1 0>;
  71                         next-level-cache = <&l2>;
  72                         cpu-idle-states = <&CPU_PH20>;
  73                         #cooling-cells = <2>;
  74                 };
  75
  76                 l2: l2-cache {
  77                         compatible = "cache";
  78                 };
  79         };
  80
  81         idle-states {
  82                 /*
  83                  * PSCI node is not added default, U-boot will add missing
  84                  * parts if it determines to use PSCI.
  85                  */
  86                 entry-method = "psci";
  87
  88                 CPU_PH20: cpu-ph20 {
  89                         compatible = "arm,idle-state";
  90                         idle-state-name = "PH20";
  91                         arm,psci-suspend-param = <0x0>;
  92                         entry-latency-us = <1000>;
  93                         exit-latency-us = <1000>;
  94                         min-residency-us = <3000>;
  95                 };
  96         };
  97
  98         memory@80000000 {
  99                 device_type = "memory";
 100                 /* Real size will be filled by bootloader */
 101                 reg = <0x0 0x80000000 0x0 0x0>;
 102         };
 103
 104         sysclk: sysclk {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 clock-frequency = <100000000>;
 108                 clock-output-names = "sysclk";
 109         };
 110
 111         reboot {
 112                 compatible ="syscon-reboot";
 113                 regmap = <&dcfg>;
 114                 offset = <0xb0>;
 115                 mask = <0x02>;
 116         };
 117
 118         thermal-zones {
 119                 cpu_thermal: cpu-thermal {
 120                         polling-delay-passive = <1000>;
 121                         polling-delay = <5000>;
 122                         thermal-sensors = <&tmu 3>;
 123
 124                         trips {
 125                                 cpu_alert: cpu-alert {
 126                                         temperature = <85000>;
 127                                         hysteresis = <2000>;
 128                                         type = "passive";
 129                                 };
 130
 131                                 cpu_crit: cpu-crit {
 132                                         temperature = <95000>;
 133                                         hysteresis = <2000>;
 134                                         type = "critical";
 135                                 };
 136                         };
 137
 138                         cooling-maps {
 139                                 map0 {
 140                                         trip = <&cpu_alert>;
 141                                         cooling-device =
 142                                                 <&cpu0 THERMAL_NO_LIMIT
 143                                                 THERMAL_NO_LIMIT>;
 144                                 };
 145                         };
 146                 };
 147         };
 148
 149         timer {
 150                 compatible = "arm,armv8-timer";
 151                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
 152                                           IRQ_TYPE_LEVEL_LOW)>,
 153                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
 154                                           IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
 156                                           IRQ_TYPE_LEVEL_LOW)>,
 157                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
 158                                           IRQ_TYPE_LEVEL_LOW)>;
 159         };
 160
 161         pmu {
 162                 compatible = "arm,cortex-a72-pmu";
 163                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 167                 interrupt-affinity = <&cpu0>,
 168                                      <&cpu1>,
 169                                      <&cpu2>,
 170                                      <&cpu3>;
 171         };
 172
 173         gic: interrupt-controller@1400000 {
 174                 compatible = "arm,gic-400";
 175                 #interrupt-cells = <3>;
 176                 interrupt-controller;
 177                 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
 178                       <0x0 0x1420000 0 0x20000>, /* GICC */
 179                       <0x0 0x1440000 0 0x20000>, /* GICH */
 180                       <0x0 0x1460000 0 0x20000>; /* GICV */
 181                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 182                                          IRQ_TYPE_LEVEL_LOW)>;
 183         };
 184
 185         soc: soc {
 186                 compatible = "simple-bus";
 187                 #address-cells = <2>;
 188                 #size-cells = <2>;
 189                 ranges;
 190
 191                 ddr: memory-controller@1080000 {
 192                         compatible = "fsl,qoriq-memory-controller";
 193                         reg = <0x0 0x1080000 0x0 0x1000>;
 194                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 195                         big-endian;
 196                 };
 197
 198                 ifc: ifc@1530000 {
 199                         compatible = "fsl,ifc", "simple-bus";
 200                         reg = <0x0 0x1530000 0x0 0x10000>;
 201                         big-endian;
 202                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 203                 };
 204
 205                 qspi: spi@1550000 {
 206                         compatible = "fsl,ls1021a-qspi";
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         reg = <0x0 0x1550000 0x0 0x10000>,
 210                                 <0x0 0x40000000 0x0 0x10000000>;
 211                         reg-names = "QuadSPI", "QuadSPI-memory";
 212                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 213                         clock-names = "qspi_en", "qspi";
 214                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 215                         big-endian;
 216                         fsl,qspi-has-second-chip;
 217                         status = "disabled";
 218                 };
 219
 220                 esdhc: esdhc@1560000 {
 221                         compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
 222                         reg = <0x0 0x1560000 0x0 0x10000>;
 223                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 224                         clocks = <&clockgen 2 1>;
 225                         voltage-ranges = <1800 1800 3300 3300>;
 226                         sdhci,auto-cmd12;
 227                         big-endian;
 228                         bus-width = <4>;
 229                 };
 230
 231                 scfg: scfg@1570000 {
 232                         compatible = "fsl,ls1046a-scfg", "syscon";
 233                         reg = <0x0 0x1570000 0x0 0x10000>;
 234                         big-endian;
 235                 };
 236
 237                 crypto: crypto@1700000 {
 238                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 239                                      "fsl,sec-v4.0";
 240                         fsl,sec-era = <8>;
 241                         #address-cells = <1>;
 242                         #size-cells = <1>;
 243                         ranges = <0x0 0x00 0x1700000 0x100000>;
 244                         reg = <0x00 0x1700000 0x0 0x100000>;
 245                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 246                         dma-coherent;
 247
 248                         sec_jr0: jr@10000 {
 249                                 compatible = "fsl,sec-v5.4-job-ring",
 250                                              "fsl,sec-v5.0-job-ring",
 251                                              "fsl,sec-v4.0-job-ring";
 252                                 reg        = <0x10000 0x10000>;
 253                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 254                         };
 255
 256                         sec_jr1: jr@20000 {
 257                                 compatible = "fsl,sec-v5.4-job-ring",
 258                                              "fsl,sec-v5.0-job-ring",
 259                                              "fsl,sec-v4.0-job-ring";
 260                                 reg        = <0x20000 0x10000>;
 261                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 262                         };
 263
 264                         sec_jr2: jr@30000 {
 265                                 compatible = "fsl,sec-v5.4-job-ring",
 266                                              "fsl,sec-v5.0-job-ring",
 267                                              "fsl,sec-v4.0-job-ring";
 268                                 reg        = <0x30000 0x10000>;
 269                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 270                         };
 271
 272                         sec_jr3: jr@40000 {
 273                                 compatible = "fsl,sec-v5.4-job-ring",
 274                                              "fsl,sec-v5.0-job-ring",
 275                                              "fsl,sec-v4.0-job-ring";
 276                                 reg        = <0x40000 0x10000>;
 277                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 278                         };
 279                 };
 280
 281                 qman: qman@1880000 {
 282                         compatible = "fsl,qman";
 283                         reg = <0x0 0x1880000 0x0 0x10000>;
 284                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 285                         memory-region = <&qman_fqd &qman_pfdr>;
 286
 287                 };
 288
 289                 bman: bman@1890000 {
 290                         compatible = "fsl,bman";
 291                         reg = <0x0 0x1890000 0x0 0x10000>;
 292                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 293                         memory-region = <&bman_fbpr>;
 294
 295                 };
 296
 297                 qportals: qman-portals@500000000 {
 298                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 299                 };
 300
 301                 bportals: bman-portals@508000000 {
 302                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 303                 };
 304
 305                 dcfg: dcfg@1ee0000 {
 306                         compatible = "fsl,ls1046a-dcfg", "syscon";
 307                         reg = <0x0 0x1ee0000 0x0 0x1000>;
 308                         big-endian;
 309                 };
 310
 311                 clockgen: clocking@1ee1000 {
 312                         compatible = "fsl,ls1046a-clockgen";
 313                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 314                         #clock-cells = <2>;
 315                         clocks = <&sysclk>;
 316                 };
 317
 318                 tmu: tmu@1f00000 {
 319                         compatible = "fsl,qoriq-tmu";
 320                         reg = <0x0 0x1f00000 0x0 0x10000>;
 321                         interrupts = <0 33 0x4>;
 322                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 323                         fsl,tmu-calibration =
 324                                 /* Calibration data group 1 */
 325                                 <0x00000000 0x00000026
 326                                 0x00000001 0x0000002d
 327                                 0x00000002 0x00000032
 328                                 0x00000003 0x00000039
 329                                 0x00000004 0x0000003f
 330                                 0x00000005 0x00000046
 331                                 0x00000006 0x0000004d
 332                                 0x00000007 0x00000054
 333                                 0x00000008 0x0000005a
 334                                 0x00000009 0x00000061
 335                                 0x0000000a 0x0000006a
 336                                 0x0000000b 0x00000071
 337                                 /* Calibration data group 2 */
 338                                 0x00010000 0x00000025
 339                                 0x00010001 0x0000002c
 340                                 0x00010002 0x00000035
 341                                 0x00010003 0x0000003d
 342                                 0x00010004 0x00000045
 343                                 0x00010005 0x0000004e
 344                                 0x00010006 0x00000057
 345                                 0x00010007 0x00000061
 346                                 0x00010008 0x0000006b
 347                                 0x00010009 0x00000076
 348                                 /* Calibration data group 3 */
 349                                 0x00020000 0x00000029
 350                                 0x00020001 0x00000033
 351                                 0x00020002 0x0000003d
 352                                 0x00020003 0x00000049
 353                                 0x00020004 0x00000056
 354                                 0x00020005 0x00000061
 355                                 0x00020006 0x0000006d
 356                                 /* Calibration data group 4 */
 357                                 0x00030000 0x00000021
 358                                 0x00030001 0x0000002a
 359                                 0x00030002 0x0000003c
 360                                 0x00030003 0x0000004e>;
 361                         big-endian;
 362                         #thermal-sensor-cells = <1>;
 363                 };
 364
 365                 dspi: spi@2100000 {
 366                         compatible = "fsl,ls1021a-v1.0-dspi";
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         reg = <0x0 0x2100000 0x0 0x10000>;
 370                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 371                         clock-names = "dspi";
 372                         clocks = <&clockgen 4 1>;
 373                         spi-num-chipselects = <5>;
 374                         big-endian;
 375                         status = "disabled";
 376                 };
 377
 378                 i2c0: i2c@2180000 {
 379                         compatible = "fsl,vf610-i2c";
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         reg = <0x0 0x2180000 0x0 0x10000>;
 383                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 384                         clocks = <&clockgen 4 1>;
 385                         dmas = <&edma0 1 39>,
 386                                <&edma0 1 38>;
 387                         dma-names = "tx", "rx";
 388                         status = "disabled";
 389                 };
 390
 391                 i2c1: i2c@2190000 {
 392                         compatible = "fsl,vf610-i2c";
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         reg = <0x0 0x2190000 0x0 0x10000>;
 396                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 397                         clocks = <&clockgen 4 1>;
 398                         status = "disabled";
 399                 };
 400
 401                 i2c2: i2c@21a0000 {
 402                         compatible = "fsl,vf610-i2c";
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         reg = <0x0 0x21a0000 0x0 0x10000>;
 406                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&clockgen 4 1>;
 408                         status = "disabled";
 409                 };
 410
 411                 i2c3: i2c@21b0000 {
 412                         compatible = "fsl,vf610-i2c";
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         reg = <0x0 0x21b0000 0x0 0x10000>;
 416                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 417                         clocks = <&clockgen 4 1>;
 418                         status = "disabled";
 419                 };
 420
 421                 duart0: serial@21c0500 {
 422                         compatible = "fsl,ns16550", "ns16550a";
 423                         reg = <0x00 0x21c0500 0x0 0x100>;
 424                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 425                         clocks = <&clockgen 4 1>;
 426                 };
 427
 428                 duart1: serial@21c0600 {
 429                         compatible = "fsl,ns16550", "ns16550a";
 430                         reg = <0x00 0x21c0600 0x0 0x100>;
 431                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 432                         clocks = <&clockgen 4 1>;
 433                 };
 434
 435                 duart2: serial@21d0500 {
 436                         compatible = "fsl,ns16550", "ns16550a";
 437                         reg = <0x0 0x21d0500 0x0 0x100>;
 438                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 439                         clocks = <&clockgen 4 1>;
 440                 };
 441
 442                 duart3: serial@21d0600 {
 443                         compatible = "fsl,ns16550", "ns16550a";
 444                         reg = <0x0 0x21d0600 0x0 0x100>;
 445                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&clockgen 4 1>;
 447                 };
 448
 449                 gpio0: gpio@2300000 {
 450                         compatible = "fsl,qoriq-gpio";
 451                         reg = <0x0 0x2300000 0x0 0x10000>;
 452                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 453                         gpio-controller;
 454                         #gpio-cells = <2>;
 455                         interrupt-controller;
 456                         #interrupt-cells = <2>;
 457                 };
 458
 459                 gpio1: gpio@2310000 {
 460                         compatible = "fsl,qoriq-gpio";
 461                         reg = <0x0 0x2310000 0x0 0x10000>;
 462                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 463                         gpio-controller;
 464                         #gpio-cells = <2>;
 465                         interrupt-controller;
 466                         #interrupt-cells = <2>;
 467                 };
 468
 469                 gpio2: gpio@2320000 {
 470                         compatible = "fsl,qoriq-gpio";
 471                         reg = <0x0 0x2320000 0x0 0x10000>;
 472                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 473                         gpio-controller;
 474                         #gpio-cells = <2>;
 475                         interrupt-controller;
 476                         #interrupt-cells = <2>;
 477                 };
 478
 479                 gpio3: gpio@2330000 {
 480                         compatible = "fsl,qoriq-gpio";
 481                         reg = <0x0 0x2330000 0x0 0x10000>;
 482                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 483                         gpio-controller;
 484                         #gpio-cells = <2>;
 485                         interrupt-controller;
 486                         #interrupt-cells = <2>;
 487                 };
 488
 489                 lpuart0: serial@2950000 {
 490                         compatible = "fsl,ls1021a-lpuart";
 491                         reg = <0x0 0x2950000 0x0 0x1000>;
 492                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 493                         clocks = <&clockgen 4 0>;
 494                         clock-names = "ipg";
 495                         status = "disabled";
 496                 };
 497
 498                 lpuart1: serial@2960000 {
 499                         compatible = "fsl,ls1021a-lpuart";
 500                         reg = <0x0 0x2960000 0x0 0x1000>;
 501                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&clockgen 4 1>;
 503                         clock-names = "ipg";
 504                         status = "disabled";
 505                 };
 506
 507                 lpuart2: serial@2970000 {
 508                         compatible = "fsl,ls1021a-lpuart";
 509                         reg = <0x0 0x2970000 0x0 0x1000>;
 510                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&clockgen 4 1>;
 512                         clock-names = "ipg";
 513                         status = "disabled";
 514                 };
 515
 516                 lpuart3: serial@2980000 {
 517                         compatible = "fsl,ls1021a-lpuart";
 518                         reg = <0x0 0x2980000 0x0 0x1000>;
 519                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&clockgen 4 1>;
 521                         clock-names = "ipg";
 522                         status = "disabled";
 523                 };
 524
 525                 lpuart4: serial@2990000 {
 526                         compatible = "fsl,ls1021a-lpuart";
 527                         reg = <0x0 0x2990000 0x0 0x1000>;
 528                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&clockgen 4 1>;
 530                         clock-names = "ipg";
 531                         status = "disabled";
 532                 };
 533
 534                 lpuart5: serial@29a0000 {
 535                         compatible = "fsl,ls1021a-lpuart";
 536                         reg = <0x0 0x29a0000 0x0 0x1000>;
 537                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&clockgen 4 1>;
 539                         clock-names = "ipg";
 540                         status = "disabled";
 541                 };
 542
 543                 wdog0: watchdog@2ad0000 {
 544                         compatible = "fsl,imx21-wdt";
 545                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 546                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 547                         clocks = <&clockgen 4 1>;
 548                         big-endian;
 549                 };
 550
 551                 edma0: edma@2c00000 {
 552                         #dma-cells = <2>;
 553                         compatible = "fsl,vf610-edma";
 554                         reg = <0x0 0x2c00000 0x0 0x10000>,
 555                               <0x0 0x2c10000 0x0 0x10000>,
 556                               <0x0 0x2c20000 0x0 0x10000>;
 557                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 558                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 559                         interrupt-names = "edma-tx", "edma-err";
 560                         dma-channels = <32>;
 561                         big-endian;
 562                         clock-names = "dmamux0", "dmamux1";
 563                         clocks = <&clockgen 4 1>,
 564                                  <&clockgen 4 1>;
 565                 };
 566
 567                 usb0: usb@2f00000 {
 568                         compatible = "snps,dwc3";
 569                         reg = <0x0 0x2f00000 0x0 0x10000>;
 570                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 571                         dr_mode = "host";
 572                         snps,quirk-frame-length-adjustment = <0x20>;
 573                         snps,dis_rxdet_inp3_quirk;
 574                 };
 575
 576                 usb1: usb@3000000 {
 577                         compatible = "snps,dwc3";
 578                         reg = <0x0 0x3000000 0x0 0x10000>;
 579                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 580                         dr_mode = "host";
 581                         snps,quirk-frame-length-adjustment = <0x20>;
 582                         snps,dis_rxdet_inp3_quirk;
 583                 };
 584
 585                 usb2: usb@3100000 {
 586                         compatible = "snps,dwc3";
 587                         reg = <0x0 0x3100000 0x0 0x10000>;
 588                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 589                         dr_mode = "host";
 590                         snps,quirk-frame-length-adjustment = <0x20>;
 591                         snps,dis_rxdet_inp3_quirk;
 592                 };
 593
 594                 sata: sata@3200000 {
 595                         compatible = "fsl,ls1046a-ahci";
 596                         reg = <0x0 0x3200000 0x0 0x10000>,
 597                                 <0x0 0x20140520 0x0 0x4>;
 598                         reg-names = "ahci", "sata-ecc";
 599                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 600                         clocks = <&clockgen 4 1>;
 601                 };
 602
 603                 msi1: msi-controller@1580000 {
 604                         compatible = "fsl,ls1046a-msi";
 605                         msi-controller;
 606                         reg = <0x0 0x1580000 0x0 0x10000>;
 607                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 608                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 610                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 611                 };
 612
 613                 msi2: msi-controller@1590000 {
 614                         compatible = "fsl,ls1046a-msi";
 615                         msi-controller;
 616                         reg = <0x0 0x1590000 0x0 0x10000>;
 617                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 618                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 619                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 620                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 621                 };
 622
 623                 msi3: msi-controller@15a0000 {
 624                         compatible = "fsl,ls1046a-msi";
 625                         msi-controller;
 626                         reg = <0x0 0x15a0000 0x0 0x10000>;
 627                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 628                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 631                 };
 632
 633                 pcie@3400000 {
 634                         compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
 635                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 636                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 637                         reg-names = "regs", "config";
 638                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 639                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 640                         interrupt-names = "aer", "pme";
 641                         #address-cells = <3>;
 642                         #size-cells = <2>;
 643                         device_type = "pci";
 644                         dma-coherent;
 645                         num-lanes = <4>;
 646                         bus-range = <0x0 0xff>;
 647                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 648                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 649                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 650                         #interrupt-cells = <1>;
 651                         interrupt-map-mask = <0 0 0 7>;
 652                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 653                                         <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 654                                         <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 655                                         <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 656                 };
 657
 658                 pcie@3500000 {
 659                         compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
 660                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 661                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 662                         reg-names = "regs", "config";
 663                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 664                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 665                         interrupt-names = "aer", "pme";
 666                         #address-cells = <3>;
 667                         #size-cells = <2>;
 668                         device_type = "pci";
 669                         dma-coherent;
 670                         num-lanes = <2>;
 671                         bus-range = <0x0 0xff>;
 672                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 673                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 674                         msi-parent = <&msi2>, <&msi3>, <&msi1>;
 675                         #interrupt-cells = <1>;
 676                         interrupt-map-mask = <0 0 0 7>;
 677                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 678                                         <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 679                                         <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 680                                         <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 681                 };
 682
 683                 pcie@3600000 {
 684                         compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
 685                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 686                                0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 687                         reg-names = "regs", "config";
 688                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 689                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 690                         interrupt-names = "aer", "pme";
 691                         #address-cells = <3>;
 692                         #size-cells = <2>;
 693                         device_type = "pci";
 694                         dma-coherent;
 695                         num-lanes = <2>;
 696                         bus-range = <0x0 0xff>;
 697                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 698                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 699                         msi-parent = <&msi3>, <&msi1>, <&msi2>;
 700                         #interrupt-cells = <1>;
 701                         interrupt-map-mask = <0 0 0 7>;
 702                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 703                                         <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 704                                         <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 705                                         <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 706                 };
 707
 708         };
 709
 710         reserved-memory {
 711                 #address-cells = <2>;
 712                 #size-cells = <2>;
 713                 ranges;
 714
 715                 bman_fbpr: bman-fbpr {
 716                         compatible = "shared-dma-pool";
 717                         size = <0 0x1000000>;
 718                         alignment = <0 0x1000000>;
 719                         no-map;
 720                 };
 721
 722                 qman_fqd: qman-fqd {
 723                         compatible = "shared-dma-pool";
 724                         size = <0 0x800000>;
 725                         alignment = <0 0x800000>;
 726                         no-map;
 727                 };
 728
 729                 qman_pfdr: qman-pfdr {
 730                         compatible = "shared-dma-pool";
 731                         size = <0 0x2000000>;
 732                         alignment = <0 0x2000000>;
 733                         no-map;
 734                 };
 735         };
 736
 737         firmware {
 738                 optee {
 739                         compatible = "linaro,optee-tz";
 740                         method = "smc";
 741                 };
 742         };
 743 };
 744
 745 #include "qoriq-qman-portals.dtsi"
 746 #include "qoriq-bman-portals.dtsi"