2 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 * Copyright 2016 Freescale Semiconductor, Inc.
7 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPLv2 or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
14 * a) This library is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
19 * This library is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 compatible = "fsl,ls2080a";
53 interrupt-parent = <&gic>;
69 device_type = "memory";
70 reg = <0x00000000 0x80000000 0 0x80000000>;
71 /* DRAM space - 1, size : 2 GB DRAM */
75 compatible = "fixed-clock";
77 clock-frequency = <100000000>;
78 clock-output-names = "sysclk";
81 gic: interrupt-controller@6000000 {
82 compatible = "arm,gic-v3";
83 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
84 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
85 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
86 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
87 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
88 #interrupt-cells = <3>;
93 interrupts = <1 9 0x4>;
95 its: gic-its@6020000 {
96 compatible = "arm,gic-v3-its";
98 reg = <0x0 0x6020000 0 0x20000>;
102 rstcr: syscon@1e60000 {
103 compatible = "fsl,ls2080a-rstcr", "syscon";
104 reg = <0x0 0x1e60000 0x0 0x4>;
108 compatible ="syscon-reboot";
115 compatible = "arm,armv8-timer";
116 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
117 <1 14 4>, /* Physical Non-Secure PPI, active-low */
118 <1 11 4>, /* Virtual PPI, active-low */
119 <1 10 4>; /* Hypervisor PPI, active-low */
124 compatible = "arm,armv8-pmuv3";
125 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
129 compatible = "arm,psci-0.2";
134 compatible = "simple-bus";
135 #address-cells = <2>;
139 clockgen: clocking@1300000 {
140 compatible = "fsl,ls2080a-clockgen";
141 reg = <0 0x1300000 0 0xa0000>;
147 compatible = "fsl,ls2080a-dcfg", "syscon";
148 reg = <0x0 0x1e00000 0x0 0x10000>;
153 compatible = "fsl,qoriq-tmu";
154 reg = <0x0 0x1f80000 0x0 0x10000>;
155 interrupts = <0 23 0x4>;
156 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
157 fsl,tmu-calibration = <0x00000000 0x00000026
158 0x00000001 0x0000002d
159 0x00000002 0x00000032
160 0x00000003 0x00000039
161 0x00000004 0x0000003f
162 0x00000005 0x00000046
163 0x00000006 0x0000004d
164 0x00000007 0x00000054
165 0x00000008 0x0000005a
166 0x00000009 0x00000061
167 0x0000000a 0x0000006a
168 0x0000000b 0x00000071
170 0x00010000 0x00000025
171 0x00010001 0x0000002c
172 0x00010002 0x00000035
173 0x00010003 0x0000003d
174 0x00010004 0x00000045
175 0x00010005 0x0000004e
176 0x00010006 0x00000057
177 0x00010007 0x00000061
178 0x00010008 0x0000006b
179 0x00010009 0x00000076
181 0x00020000 0x00000029
182 0x00020001 0x00000033
183 0x00020002 0x0000003d
184 0x00020003 0x00000049
185 0x00020004 0x00000056
186 0x00020005 0x00000061
187 0x00020006 0x0000006d
189 0x00030000 0x00000021
190 0x00030001 0x0000002a
191 0x00030002 0x0000003c
192 0x00030003 0x0000004e>;
194 #thermal-sensor-cells = <1>;
198 cpu_thermal: cpu-thermal {
199 polling-delay-passive = <1000>;
200 polling-delay = <5000>;
202 thermal-sensors = <&tmu 4>;
205 cpu_alert: cpu-alert {
206 temperature = <75000>;
211 temperature = <85000>;
221 <&cpu0 THERMAL_NO_LIMIT
227 <&cpu2 THERMAL_NO_LIMIT
233 <&cpu4 THERMAL_NO_LIMIT
239 <&cpu6 THERMAL_NO_LIMIT
246 serial0: serial@21c0500 {
247 compatible = "fsl,ns16550", "ns16550a";
248 reg = <0x0 0x21c0500 0x0 0x100>;
249 clocks = <&clockgen 4 3>;
250 interrupts = <0 32 0x4>; /* Level high type */
253 serial1: serial@21c0600 {
254 compatible = "fsl,ns16550", "ns16550a";
255 reg = <0x0 0x21c0600 0x0 0x100>;
256 clocks = <&clockgen 4 3>;
257 interrupts = <0 32 0x4>; /* Level high type */
260 cluster1_core0_watchdog: wdt@c000000 {
261 compatible = "arm,sp805-wdt", "arm,primecell";
262 reg = <0x0 0xc000000 0x0 0x1000>;
263 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
264 clock-names = "apb_pclk", "wdog_clk";
267 cluster1_core1_watchdog: wdt@c010000 {
268 compatible = "arm,sp805-wdt", "arm,primecell";
269 reg = <0x0 0xc010000 0x0 0x1000>;
270 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
271 clock-names = "apb_pclk", "wdog_clk";
274 cluster2_core0_watchdog: wdt@c100000 {
275 compatible = "arm,sp805-wdt", "arm,primecell";
276 reg = <0x0 0xc100000 0x0 0x1000>;
277 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
278 clock-names = "apb_pclk", "wdog_clk";
281 cluster2_core1_watchdog: wdt@c110000 {
282 compatible = "arm,sp805-wdt", "arm,primecell";
283 reg = <0x0 0xc110000 0x0 0x1000>;
284 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
285 clock-names = "apb_pclk", "wdog_clk";
288 cluster3_core0_watchdog: wdt@c200000 {
289 compatible = "arm,sp805-wdt", "arm,primecell";
290 reg = <0x0 0xc200000 0x0 0x1000>;
291 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
292 clock-names = "apb_pclk", "wdog_clk";
295 cluster3_core1_watchdog: wdt@c210000 {
296 compatible = "arm,sp805-wdt", "arm,primecell";
297 reg = <0x0 0xc210000 0x0 0x1000>;
298 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
299 clock-names = "apb_pclk", "wdog_clk";
302 cluster4_core0_watchdog: wdt@c300000 {
303 compatible = "arm,sp805-wdt", "arm,primecell";
304 reg = <0x0 0xc300000 0x0 0x1000>;
305 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
306 clock-names = "apb_pclk", "wdog_clk";
309 cluster4_core1_watchdog: wdt@c310000 {
310 compatible = "arm,sp805-wdt", "arm,primecell";
311 reg = <0x0 0xc310000 0x0 0x1000>;
312 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
313 clock-names = "apb_pclk", "wdog_clk";
316 crypto: crypto@8000000 {
317 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
319 #address-cells = <1>;
321 ranges = <0x0 0x00 0x8000000 0x100000>;
322 reg = <0x00 0x8000000 0x0 0x100000>;
323 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
327 compatible = "fsl,sec-v5.0-job-ring",
328 "fsl,sec-v4.0-job-ring";
329 reg = <0x10000 0x10000>;
330 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
334 compatible = "fsl,sec-v5.0-job-ring",
335 "fsl,sec-v4.0-job-ring";
336 reg = <0x20000 0x10000>;
337 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
341 compatible = "fsl,sec-v5.0-job-ring",
342 "fsl,sec-v4.0-job-ring";
343 reg = <0x30000 0x10000>;
344 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
348 compatible = "fsl,sec-v5.0-job-ring",
349 "fsl,sec-v4.0-job-ring";
350 reg = <0x40000 0x10000>;
351 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
355 fsl_mc: fsl-mc@80c000000 {
356 compatible = "fsl,qoriq-mc";
357 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
358 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
360 #address-cells = <3>;
364 * Region type 0x0 - MC portals
365 * Region type 0x1 - QBMAN portals
367 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
368 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
371 * Define the maximum number of MACs present on the SoC.
374 #address-cells = <1>;
378 compatible = "fsl,qoriq-mc-dpmac";
383 compatible = "fsl,qoriq-mc-dpmac";
388 compatible = "fsl,qoriq-mc-dpmac";
393 compatible = "fsl,qoriq-mc-dpmac";
398 compatible = "fsl,qoriq-mc-dpmac";
403 compatible = "fsl,qoriq-mc-dpmac";
408 compatible = "fsl,qoriq-mc-dpmac";
413 compatible = "fsl,qoriq-mc-dpmac";
418 compatible = "fsl,qoriq-mc-dpmac";
423 compatible = "fsl,qoriq-mc-dpmac";
428 compatible = "fsl,qoriq-mc-dpmac";
433 compatible = "fsl,qoriq-mc-dpmac";
438 compatible = "fsl,qoriq-mc-dpmac";
443 compatible = "fsl,qoriq-mc-dpmac";
448 compatible = "fsl,qoriq-mc-dpmac";
453 compatible = "fsl,qoriq-mc-dpmac";
459 smmu: iommu@5000000 {
460 compatible = "arm,mmu-500";
461 reg = <0 0x5000000 0 0x800000>;
462 #global-interrupts = <12>;
463 interrupts = <0 13 4>, /* global secure fault */
464 <0 14 4>, /* combined secure interrupt */
465 <0 15 4>, /* global non-secure fault */
466 <0 16 4>, /* combined non-secure interrupt */
467 /* performance counter interrupts 0-7 */
468 <0 211 4>, <0 212 4>,
469 <0 213 4>, <0 214 4>,
470 <0 215 4>, <0 216 4>,
471 <0 217 4>, <0 218 4>,
472 /* per context interrupt, 64 interrupts */
473 <0 146 4>, <0 147 4>,
474 <0 148 4>, <0 149 4>,
475 <0 150 4>, <0 151 4>,
476 <0 152 4>, <0 153 4>,
477 <0 154 4>, <0 155 4>,
478 <0 156 4>, <0 157 4>,
479 <0 158 4>, <0 159 4>,
480 <0 160 4>, <0 161 4>,
481 <0 162 4>, <0 163 4>,
482 <0 164 4>, <0 165 4>,
483 <0 166 4>, <0 167 4>,
484 <0 168 4>, <0 169 4>,
485 <0 170 4>, <0 171 4>,
486 <0 172 4>, <0 173 4>,
487 <0 174 4>, <0 175 4>,
488 <0 176 4>, <0 177 4>,
489 <0 178 4>, <0 179 4>,
490 <0 180 4>, <0 181 4>,
491 <0 182 4>, <0 183 4>,
492 <0 184 4>, <0 185 4>,
493 <0 186 4>, <0 187 4>,
494 <0 188 4>, <0 189 4>,
495 <0 190 4>, <0 191 4>,
496 <0 192 4>, <0 193 4>,
497 <0 194 4>, <0 195 4>,
498 <0 196 4>, <0 197 4>,
499 <0 198 4>, <0 199 4>,
500 <0 200 4>, <0 201 4>,
501 <0 202 4>, <0 203 4>,
502 <0 204 4>, <0 205 4>,
503 <0 206 4>, <0 207 4>,
504 <0 208 4>, <0 209 4>;
505 mmu-masters = <&fsl_mc 0x300 0>;
510 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
511 #address-cells = <1>;
513 reg = <0x0 0x2100000 0x0 0x10000>;
514 interrupts = <0 26 0x4>; /* Level high type */
515 clocks = <&clockgen 4 3>;
516 clock-names = "dspi";
517 spi-num-chipselects = <5>;
520 esdhc: esdhc@2140000 {
522 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
523 reg = <0x0 0x2140000 0x0 0x10000>;
524 interrupts = <0 28 0x4>; /* Level high type */
525 clocks = <&clockgen 4 1>;
526 voltage-ranges = <1800 1800 3300 3300>;
532 gpio0: gpio@2300000 {
533 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
534 reg = <0x0 0x2300000 0x0 0x10000>;
535 interrupts = <0 36 0x4>; /* Level high type */
539 interrupt-controller;
540 #interrupt-cells = <2>;
543 gpio1: gpio@2310000 {
544 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
545 reg = <0x0 0x2310000 0x0 0x10000>;
546 interrupts = <0 36 0x4>; /* Level high type */
550 interrupt-controller;
551 #interrupt-cells = <2>;
554 gpio2: gpio@2320000 {
555 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
556 reg = <0x0 0x2320000 0x0 0x10000>;
557 interrupts = <0 37 0x4>; /* Level high type */
561 interrupt-controller;
562 #interrupt-cells = <2>;
565 gpio3: gpio@2330000 {
566 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
567 reg = <0x0 0x2330000 0x0 0x10000>;
568 interrupts = <0 37 0x4>; /* Level high type */
572 interrupt-controller;
573 #interrupt-cells = <2>;
578 compatible = "fsl,vf610-i2c";
579 #address-cells = <1>;
581 reg = <0x0 0x2000000 0x0 0x10000>;
582 interrupts = <0 34 0x4>; /* Level high type */
584 clocks = <&clockgen 4 3>;
589 compatible = "fsl,vf610-i2c";
590 #address-cells = <1>;
592 reg = <0x0 0x2010000 0x0 0x10000>;
593 interrupts = <0 34 0x4>; /* Level high type */
595 clocks = <&clockgen 4 3>;
600 compatible = "fsl,vf610-i2c";
601 #address-cells = <1>;
603 reg = <0x0 0x2020000 0x0 0x10000>;
604 interrupts = <0 35 0x4>; /* Level high type */
606 clocks = <&clockgen 4 3>;
611 compatible = "fsl,vf610-i2c";
612 #address-cells = <1>;
614 reg = <0x0 0x2030000 0x0 0x10000>;
615 interrupts = <0 35 0x4>; /* Level high type */
617 clocks = <&clockgen 4 3>;
621 compatible = "fsl,ifc", "simple-bus";
622 reg = <0x0 0x2240000 0x0 0x20000>;
623 interrupts = <0 21 0x4>; /* Level high type */
625 #address-cells = <2>;
628 ranges = <0 0 0x5 0x80000000 0x08000000
629 2 0 0x5 0x30000000 0x00010000
630 3 0 0x5 0x20000000 0x00010000>;
633 qspi: quadspi@20c0000 {
635 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
636 #address-cells = <1>;
638 reg = <0x0 0x20c0000 0x0 0x10000>,
639 <0x0 0x20000000 0x0 0x10000000>;
640 reg-names = "QuadSPI", "QuadSPI-memory";
641 interrupts = <0 25 0x4>; /* Level high type */
642 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
643 clock-names = "qspi_en", "qspi";
646 pcie1: pcie@3400000 {
647 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
649 reg-names = "regs", "config";
650 interrupts = <0 108 0x4>; /* Level high type */
651 interrupt-names = "intr";
652 #address-cells = <3>;
657 bus-range = <0x0 0xff>;
659 #interrupt-cells = <1>;
660 interrupt-map-mask = <0 0 0 7>;
661 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
662 <0000 0 0 2 &gic 0 0 0 110 4>,
663 <0000 0 0 3 &gic 0 0 0 111 4>,
664 <0000 0 0 4 &gic 0 0 0 112 4>;
667 pcie2: pcie@3500000 {
668 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
670 reg-names = "regs", "config";
671 interrupts = <0 113 0x4>; /* Level high type */
672 interrupt-names = "intr";
673 #address-cells = <3>;
678 bus-range = <0x0 0xff>;
680 #interrupt-cells = <1>;
681 interrupt-map-mask = <0 0 0 7>;
682 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
683 <0000 0 0 2 &gic 0 0 0 115 4>,
684 <0000 0 0 3 &gic 0 0 0 116 4>,
685 <0000 0 0 4 &gic 0 0 0 117 4>;
688 pcie3: pcie@3600000 {
689 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
691 reg-names = "regs", "config";
692 interrupts = <0 118 0x4>; /* Level high type */
693 interrupt-names = "intr";
694 #address-cells = <3>;
699 bus-range = <0x0 0xff>;
701 #interrupt-cells = <1>;
702 interrupt-map-mask = <0 0 0 7>;
703 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
704 <0000 0 0 2 &gic 0 0 0 120 4>,
705 <0000 0 0 3 &gic 0 0 0 121 4>,
706 <0000 0 0 4 &gic 0 0 0 122 4>;
709 pcie4: pcie@3700000 {
710 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
712 reg-names = "regs", "config";
713 interrupts = <0 123 0x4>; /* Level high type */
714 interrupt-names = "intr";
715 #address-cells = <3>;
720 bus-range = <0x0 0xff>;
722 #interrupt-cells = <1>;
723 interrupt-map-mask = <0 0 0 7>;
724 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
725 <0000 0 0 2 &gic 0 0 0 125 4>,
726 <0000 0 0 3 &gic 0 0 0 126 4>,
727 <0000 0 0 4 &gic 0 0 0 127 4>;
730 sata0: sata@3200000 {
732 compatible = "fsl,ls2080a-ahci";
733 reg = <0x0 0x3200000 0x0 0x10000>;
734 interrupts = <0 133 0x4>; /* Level high type */
735 clocks = <&clockgen 4 3>;
739 sata1: sata@3210000 {
741 compatible = "fsl,ls2080a-ahci";
742 reg = <0x0 0x3210000 0x0 0x10000>;
743 interrupts = <0 136 0x4>; /* Level high type */
744 clocks = <&clockgen 4 3>;
750 compatible = "snps,dwc3";
751 reg = <0x0 0x3100000 0x0 0x10000>;
752 interrupts = <0 80 0x4>; /* Level high type */
754 snps,quirk-frame-length-adjustment = <0x20>;
755 snps,dis_rxdet_inp3_quirk;
760 compatible = "snps,dwc3";
761 reg = <0x0 0x3110000 0x0 0x10000>;
762 interrupts = <0 81 0x4>; /* Level high type */
764 snps,quirk-frame-length-adjustment = <0x20>;
765 snps,dis_rxdet_inp3_quirk;
769 compatible = "arm,ccn-504";
770 reg = <0x0 0x04000000 0x0 0x01000000>;
771 interrupts = <0 12 4>;
775 ddr1: memory-controller@1080000 {
776 compatible = "fsl,qoriq-memory-controller";
777 reg = <0x0 0x1080000 0x0 0x1000>;
778 interrupts = <0 17 0x4>;
782 ddr2: memory-controller@1090000 {
783 compatible = "fsl,qoriq-memory-controller";
784 reg = <0x0 0x1090000 0x0 0x1000>;
785 interrupts = <0 18 0x4>;