arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi

   1 /*
   2  * Copyright (C) 2016 Marvell Technology Group Ltd.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPLv2 or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /*
  44  * Device Tree file for Marvell Armada CP110 Master.
  45  */
  46
  47 #define ICU_GRP_NSR 0x0
  48
  49 / {
  50         cp110-master {
  51                 #address-cells = <2>;
  52                 #size-cells = <2>;
  53                 compatible = "simple-bus";
  54                 interrupt-parent = <&cpm_icu>;
  55                 ranges;
  56
  57                 config-space@f2000000 {
  58                         #address-cells = <1>;
  59                         #size-cells = <1>;
  60                         compatible = "simple-bus";
  61                         ranges = <0x0 0x0 0xf2000000 0x2000000>;
  62
  63                         cpm_ethernet: ethernet@0 {
  64                                 compatible = "marvell,armada-7k-pp22";
  65                                 reg = <0x0 0x100000>, <0x129000 0xb000>;
  66                                 clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>,
  67                                          <&cpm_clk 1 5>, <&cpm_clk 1 18>;
  68                                 clock-names = "pp_clk", "gop_clk",
  69                                               "mg_clk","axi_clk";
  70                                 marvell,system-controller = <&cpm_syscon0>;
  71                                 status = "disabled";
  72                                 dma-coherent;
  73
  74                                 cpm_eth0: eth0 {
  75                                         interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
  76                                                      <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
  77                                                      <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
  78                                                      <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
  79                                                      <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
  80                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  81                                                           "tx-cpu3", "rx-shared";
  82                                         port-id = <0>;
  83                                         gop-port-id = <0>;
  84                                         status = "disabled";
  85                                 };
  86
  87                                 cpm_eth1: eth1 {
  88                                         interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
  89                                                      <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
  90                                                      <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
  91                                                      <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
  92                                                      <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
  93                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  94                                                           "tx-cpu3", "rx-shared";
  95                                         port-id = <1>;
  96                                         gop-port-id = <2>;
  97                                         status = "disabled";
  98                                 };
  99
 100                                 cpm_eth2: eth2 {
 101                                         interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
 102                                                      <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 103                                                      <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 104                                                      <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
 105                                                      <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
 106                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
 107                                                           "tx-cpu3", "rx-shared";
 108                                         port-id = <2>;
 109                                         gop-port-id = <3>;
 110                                         status = "disabled";
 111                                 };
 112                         };
 113
 114                         cpm_comphy: phy@120000 {
 115                                 compatible = "marvell,comphy-cp110";
 116                                 reg = <0x120000 0x6000>;
 117                                 marvell,system-controller = <&cpm_syscon0>;
 118                                 #address-cells = <1>;
 119                                 #size-cells = <0>;
 120
 121                                 cpm_comphy0: phy@0 {
 122                                         reg = <0>;
 123                                         #phy-cells = <1>;
 124                                 };
 125
 126                                 cpm_comphy1: phy@1 {
 127                                         reg = <1>;
 128                                         #phy-cells = <1>;
 129                                 };
 130
 131                                 cpm_comphy2: phy@2 {
 132                                         reg = <2>;
 133                                         #phy-cells = <1>;
 134                                 };
 135
 136                                 cpm_comphy3: phy@3 {
 137                                         reg = <3>;
 138                                         #phy-cells = <1>;
 139                                 };
 140
 141                                 cpm_comphy4: phy@4 {
 142                                         reg = <4>;
 143                                         #phy-cells = <1>;
 144                                 };
 145
 146                                 cpm_comphy5: phy@5 {
 147                                         reg = <5>;
 148                                         #phy-cells = <1>;
 149                                 };
 150                         };
 151
 152                         cpm_mdio: mdio@12a200 {
 153                                 #address-cells = <1>;
 154                                 #size-cells = <0>;
 155                                 compatible = "marvell,orion-mdio";
 156                                 reg = <0x12a200 0x10>;
 157                                 clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>,
 158                                          <&cpm_clk 1 6>, <&cpm_clk 1 18>;
 159                                 status = "disabled";
 160                         };
 161
 162                         cpm_xmdio: mdio@12a600 {
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165                                 compatible = "marvell,xmdio";
 166                                 reg = <0x12a600 0x10>;
 167                                 status = "disabled";
 168                         };
 169
 170                         cpm_icu: interrupt-controller@1e0000 {
 171                                 compatible = "marvell,cp110-icu";
 172                                 reg = <0x1e0000 0x10>;
 173                                 #interrupt-cells = <3>;
 174                                 interrupt-controller;
 175                                 msi-parent = <&gicp>;
 176                         };
 177
 178                         cpm_rtc: rtc@284000 {
 179                                 compatible = "marvell,armada-8k-rtc";
 180                                 reg = <0x284000 0x20>, <0x284080 0x24>;
 181                                 reg-names = "rtc", "rtc-soc";
 182                                 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
 183                         };
 184
 185                         cpm_syscon0: system-controller@440000 {
 186                                 compatible = "syscon", "simple-mfd";
 187                                 reg = <0x440000 0x1000>;
 188
 189                                 cpm_clk: clock {
 190                                         compatible = "marvell,cp110-clock";
 191                                         #clock-cells = <2>;
 192                                 };
 193
 194                                 cpm_gpio1: gpio@100 {
 195                                         compatible = "marvell,armada-8k-gpio";
 196                                         offset = <0x100>;
 197                                         ngpios = <32>;
 198                                         gpio-controller;
 199                                         #gpio-cells = <2>;
 200                                         gpio-ranges = <&cpm_pinctrl 0 0 32>;
 201                                         interrupt-controller;
 202                                         interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
 203                                                      <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
 204                                                      <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
 205                                                      <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
 206                                         status = "disabled";
 207                                 };
 208
 209                                 cpm_gpio2: gpio@140 {
 210                                         compatible = "marvell,armada-8k-gpio";
 211                                         offset = <0x140>;
 212                                         ngpios = <31>;
 213                                         gpio-controller;
 214                                         #gpio-cells = <2>;
 215                                         gpio-ranges = <&cpm_pinctrl 0 32 31>;
 216                                         interrupt-controller;
 217                                         interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
 218                                                      <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
 219                                                      <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
 220                                                      <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
 221                                         status = "disabled";
 222                                 };
 223                         };
 224
 225                         cpm_usb3_0: usb3@500000 {
 226                                 compatible = "marvell,armada-8k-xhci",
 227                                              "generic-xhci";
 228                                 reg = <0x500000 0x4000>;
 229                                 dma-coherent;
 230                                 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
 231                                 clocks = <&cpm_clk 1 22>;
 232                                 status = "disabled";
 233                         };
 234
 235                         cpm_usb3_1: usb3@510000 {
 236                                 compatible = "marvell,armada-8k-xhci",
 237                                              "generic-xhci";
 238                                 reg = <0x510000 0x4000>;
 239                                 dma-coherent;
 240                                 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
 241                                 clocks = <&cpm_clk 1 23>;
 242                                 status = "disabled";
 243                         };
 244
 245                         cpm_sata0: sata@540000 {
 246                                 compatible = "marvell,armada-8k-ahci",
 247                                              "generic-ahci";
 248                                 reg = <0x540000 0x30000>;
 249                                 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
 250                                 clocks = <&cpm_clk 1 15>;
 251                                 status = "disabled";
 252                         };
 253
 254                         cpm_xor0: xor@6a0000 {
 255                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 256                                 reg = <0x6a0000 0x1000>,
 257                                       <0x6b0000 0x1000>;
 258                                 dma-coherent;
 259                                 msi-parent = <&gic_v2m0>;
 260                                 clocks = <&cpm_clk 1 8>;
 261                         };
 262
 263                         cpm_xor1: xor@6c0000 {
 264                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 265                                 reg = <0x6c0000 0x1000>,
 266                                       <0x6d0000 0x1000>;
 267                                 dma-coherent;
 268                                 msi-parent = <&gic_v2m0>;
 269                                 clocks = <&cpm_clk 1 7>;
 270                         };
 271
 272                         cpm_spi0: spi@700600 {
 273                                 compatible = "marvell,armada-380-spi";
 274                                 reg = <0x700600 0x50>;
 275                                 #address-cells = <0x1>;
 276                                 #size-cells = <0x0>;
 277                                 cell-index = <1>;
 278                                 clocks = <&cpm_clk 1 21>;
 279                                 status = "disabled";
 280                         };
 281
 282                         cpm_spi1: spi@700680 {
 283                                 compatible = "marvell,armada-380-spi";
 284                                 reg = <0x700680 0x50>;
 285                                 #address-cells = <1>;
 286                                 #size-cells = <0>;
 287                                 cell-index = <2>;
 288                                 clocks = <&cpm_clk 1 21>;
 289                                 status = "disabled";
 290                         };
 291
 292                         cpm_i2c0: i2c@701000 {
 293                                 compatible = "marvell,mv78230-i2c";
 294                                 reg = <0x701000 0x20>;
 295                                 #address-cells = <1>;
 296                                 #size-cells = <0>;
 297                                 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
 298                                 clocks = <&cpm_clk 1 21>;
 299                                 status = "disabled";
 300                         };
 301
 302                         cpm_i2c1: i2c@701100 {
 303                                 compatible = "marvell,mv78230-i2c";
 304                                 reg = <0x701100 0x20>;
 305                                 #address-cells = <1>;
 306                                 #size-cells = <0>;
 307                                 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
 308                                 clocks = <&cpm_clk 1 21>;
 309                                 status = "disabled";
 310                         };
 311
 312                         cpm_nand: nand@720000 {
 313                                 /*
 314                                  * Due to the limiation of the pin available
 315                                  * this controller is only usable on the CPM
 316                                  * for A7K and on the CPS for A8K.
 317                                  */
 318                                 compatible = "marvell,armada370-nand";
 319                                 reg = <0x720000 0x54>;
 320                                 #address-cells = <1>;
 321                                 #size-cells = <1>;
 322                                 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
 323                                 clocks = <&cpm_clk 1 2>;
 324                                 status = "disabled";
 325                         };
 326
 327                         cpm_trng: trng@760000 {
 328                                 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
 329                                 reg = <0x760000 0x7d>;
 330                                 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
 331                                 clocks = <&cpm_clk 1 25>;
 332                                 status = "okay";
 333                         };
 334
 335                         cpm_sdhci0: sdhci@780000 {
 336                                 compatible = "marvell,armada-cp110-sdhci";
 337                                 reg = <0x780000 0x300>;
 338                                 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
 339                                 clock-names = "core","axi";
 340                                 clocks = <&cpm_clk 1 4>, <&cpm_clk 1 18>;
 341                                 dma-coherent;
 342                                 status = "disabled";
 343                         };
 344
 345                         cpm_crypto: crypto@800000 {
 346                                 compatible = "inside-secure,safexcel-eip197";
 347                                 reg = <0x800000 0x200000>;
 348                                 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 349                                              <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 350                                              <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 351                                              <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 352                                              <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 353                                              <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 354                                 interrupt-names = "mem", "ring0", "ring1",
 355                                 "ring2", "ring3", "eip";
 356                                 clocks = <&cpm_clk 1 26>;
 357                                 dma-coherent;
 358                         };
 359                 };
 360
 361                 cpm_pcie0: pcie@f2600000 {
 362                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 363                         reg = <0 0xf2600000 0 0x10000>,
 364                               <0 0xf6f00000 0 0x80000>;
 365                         reg-names = "ctrl", "config";
 366                         #address-cells = <3>;
 367                         #size-cells = <2>;
 368                         #interrupt-cells = <1>;
 369                         device_type = "pci";
 370                         dma-coherent;
 371                         msi-parent = <&gic_v2m0>;
 372
 373                         bus-range = <0 0xff>;
 374                         ranges =
 375                                 /* downstream I/O */
 376                                 <0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000
 377                                 /* non-prefetchable memory */
 378                                 0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;
 379                         interrupt-map-mask = <0 0 0 0>;
 380                         interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 381                         interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 382                         num-lanes = <1>;
 383                         clocks = <&cpm_clk 1 13>;
 384                         status = "disabled";
 385                 };
 386
 387                 cpm_pcie1: pcie@f2620000 {
 388                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 389                         reg = <0 0xf2620000 0 0x10000>,
 390                               <0 0xf7f00000 0 0x80000>;
 391                         reg-names = "ctrl", "config";
 392                         #address-cells = <3>;
 393                         #size-cells = <2>;
 394                         #interrupt-cells = <1>;
 395                         device_type = "pci";
 396                         dma-coherent;
 397                         msi-parent = <&gic_v2m0>;
 398
 399                         bus-range = <0 0xff>;
 400                         ranges =
 401                                 /* downstream I/O */
 402                                 <0x81000000 0 0xf9010000 0  0xf9010000 0 0x10000
 403                                 /* non-prefetchable memory */
 404                                 0x82000000 0 0xf7000000 0  0xf7000000 0 0xf00000>;
 405                         interrupt-map-mask = <0 0 0 0>;
 406                         interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 407                         interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 408
 409                         num-lanes = <1>;
 410                         clocks = <&cpm_clk 1 11>;
 411                         status = "disabled";
 412                 };
 413
 414                 cpm_pcie2: pcie@f2640000 {
 415                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 416                         reg = <0 0xf2640000 0 0x10000>,
 417                               <0 0xf8f00000 0 0x80000>;
 418                         reg-names = "ctrl", "config";
 419                         #address-cells = <3>;
 420                         #size-cells = <2>;
 421                         #interrupt-cells = <1>;
 422                         device_type = "pci";
 423                         dma-coherent;
 424                         msi-parent = <&gic_v2m0>;
 425
 426                         bus-range = <0 0xff>;
 427                         ranges =
 428                                 /* downstream I/O */
 429                                 <0x81000000 0 0xf9020000 0  0xf9020000 0 0x10000
 430                                 /* non-prefetchable memory */
 431                                 0x82000000 0 0xf8000000 0  0xf8000000 0 0xf00000>;
 432                         interrupt-map-mask = <0 0 0 0>;
 433                         interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 434                         interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 435
 436                         num-lanes = <1>;
 437                         clocks = <&cpm_clk 1 12>;
 438                         status = "disabled";
 439                 };
 440         };
 441 };