2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
17 model = "MediaTek MT7622 RFB1 board";
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
26 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
42 compatible = "gpio-keys";
43 poll-interval = <100>;
53 linux,code = <KEY_WPS_BUTTON>;
59 reg = <0 0x40000000 0 0x3F000000>;
62 reg_1p8v: regulator-1p8v {
63 compatible = "regulator-fixed";
64 regulator-name = "fixed-1.8V";
65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>;
70 reg_3p3v: regulator-3p3v {
71 compatible = "regulator-fixed";
72 regulator-name = "fixed-3.3V";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
79 reg_5v: regulator-5v {
80 compatible = "regulator-fixed";
81 regulator-name = "fixed-5V";
82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pcie0_pins>;
100 /* eMMC is shared pin with parallel NAND */
101 emmc_pins_default: emmc-pins-default {
103 function = "emmc", "emmc_rst";
107 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
108 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
109 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
112 pins = "NDL0", "NDL1", "NDL2",
113 "NDL3", "NDL4", "NDL5",
114 "NDL6", "NDL7", "NRB";
125 emmc_pins_uhs: emmc-pins-uhs {
132 pins = "NDL0", "NDL1", "NDL2",
133 "NDL3", "NDL4", "NDL5",
134 "NDL6", "NDL7", "NRB";
136 drive-strength = <4>;
142 drive-strength = <4>;
150 groups = "mdc_mdio", "rgmii_via_gmac2";
154 i2c1_pins: i2c1-pins {
161 i2c2_pins: i2c2-pins {
168 i2s1_pins: i2s1-pins {
171 groups = "i2s_out_mclk_bclk_ws",
177 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
178 "I2S_WS", "I2S_MCLK";
179 drive-strength = <12>;
184 irrx_pins: irrx-pins {
191 irtx_pins: irtx-pins {
198 /* Parallel nand is shared pin with eMMC */
199 parallel_nand_pins: parallel-nand-pins {
206 pcie0_pins: pcie0-pins {
209 groups = "pcie0_pad_perst",
215 pcie1_pins: pcie1-pins {
218 groups = "pcie1_pad_perst",
224 pmic_bus_pins: pmic-bus-pins {
231 pwm7_pins: pwm1-2-pins {
234 groups = "pwm_ch7_2";
238 wled_pins: wled-pins {
245 sd0_pins_default: sd0-pins-default {
251 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
252 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
253 * DAT2, DAT3, CMD, CLK for SD respectively.
256 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
257 "I2S2_IN","I2S4_OUT";
259 drive-strength = <8>;
264 drive-strength = <12>;
273 sd0_pins_uhs: sd0-pins-uhs {
280 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
281 "I2S2_IN","I2S4_OUT";
292 /* Serial NAND is shared pin with SPI-NOR */
293 serial_nand_pins: serial-nand-pins {
300 spic0_pins: spic0-pins {
307 spic1_pins: spic1-pins {
314 /* SPI-NOR is shared pin with serial NAND */
315 spi_nor_pins: spi-nor-pins {
322 /* serial NAND is shared pin with SPI-NOR */
323 serial_nand_pins: serial-nand-pins {
330 uart0_pins: uart0-pins {
333 groups = "uart0_0_tx_rx" ;
337 uart2_pins: uart2-pins {
340 groups = "uart2_1_tx_rx" ;
344 watchdog_pins: watchdog-pins {
346 function = "watchdog";
361 pinctrl-names = "default";
362 pinctrl-0 = <&irrx_pins>;
367 pinctrl-names = "default";
368 pinctrl-0 = <ð_pins>;
372 compatible = "mediatek,eth-mac";
374 phy-handle = <&phy5>;
378 #address-cells = <1>;
381 phy5: ethernet-phy@5 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&i2c1_pins>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c2_pins>;
401 pinctrl-names = "default", "state_uhs";
402 pinctrl-0 = <&emmc_pins_default>;
403 pinctrl-1 = <&emmc_pins_uhs>;
406 max-frequency = <50000000>;
409 vmmc-supply = <®_3p3v>;
410 vqmmc-supply = <®_1p8v>;
411 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
412 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
417 pinctrl-names = "default", "state_uhs";
418 pinctrl-0 = <&sd0_pins_default>;
419 pinctrl-1 = <&sd0_pins_uhs>;
422 max-frequency = <50000000>;
425 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
426 vmmc-supply = <®_3p3v>;
427 vqmmc-supply = <®_3p3v>;
428 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
429 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
433 pinctrl-names = "default";
434 pinctrl-0 = <¶llel_nand_pins>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&spi_nor_pins>;
444 compatible = "jedec,spi-nor";
450 pinctrl-names = "default";
451 pinctrl-0 = <&pwm7_pins>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&pmic_bus_pins>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&spic0_pins>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&spic1_pins>;
483 vusb33-supply = <®_3p3v>;
484 vbus-supply = <®_5v>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&uart0_pins>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&uart2_pins>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&watchdog_pins>;