arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16
  17 / {
  18         model = "Qualcomm Technologies, Inc. MSM8996";
  19
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         chosen { };
  26
  27         memory {
  28                 device_type = "memory";
  29                 /* We expect the bootloader to fill in the reg */
  30                 reg = <0 0 0 0>;
  31         };
  32
  33         reserved-memory {
  34                 #address-cells = <2>;
  35                 #size-cells = <2>;
  36                 ranges;
  37
  38                 mba_region: mba@91500000 {
  39                         reg = <0x0 0x91500000 0x0 0x200000>;
  40                         no-map;
  41                 };
  42
  43                 slpi_region: slpi@90b00000 {
  44                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  45                         no-map;
  46                 };
  47
  48                 venus_region: venus@90400000 {
  49                         reg = <0x0 0x90400000 0x0 0x700000>;
  50                         no-map;
  51                 };
  52
  53                 adsp_region: adsp@8ea00000 {
  54                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  55                         no-map;
  56                 };
  57
  58                 mpss_region: mpss@88800000 {
  59                         reg = <0x0 0x88800000 0x0 0x6200000>;
  60                         no-map;
  61                 };
  62
  63                 smem_mem: smem-mem@86000000 {
  64                         reg = <0x0 0x86000000 0x0 0x200000>;
  65                         no-map;
  66                 };
  67
  68                 memory@85800000 {
  69                         reg = <0x0 0x85800000 0x0 0x800000>;
  70                         no-map;
  71                 };
  72
  73                 memory@86200000 {
  74                         reg = <0x0 0x86200000 0x0 0x2600000>;
  75                         no-map;
  76                 };
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 CPU0: cpu@0 {
  84                         device_type = "cpu";
  85                         compatible = "qcom,kryo";
  86                         reg = <0x0 0x0>;
  87                         enable-method = "psci";
  88                         next-level-cache = <&L2_0>;
  89                         L2_0: l2-cache {
  90                               compatible = "cache";
  91                               cache-level = <2>;
  92                         };
  93                 };
  94
  95                 CPU1: cpu@1 {
  96                         device_type = "cpu";
  97                         compatible = "qcom,kryo";
  98                         reg = <0x0 0x1>;
  99                         enable-method = "psci";
 100                         next-level-cache = <&L2_0>;
 101                 };
 102
 103                 CPU2: cpu@100 {
 104                         device_type = "cpu";
 105                         compatible = "qcom,kryo";
 106                         reg = <0x0 0x100>;
 107                         enable-method = "psci";
 108                         next-level-cache = <&L2_1>;
 109                         L2_1: l2-cache {
 110                               compatible = "cache";
 111                               cache-level = <2>;
 112                         };
 113                 };
 114
 115                 CPU3: cpu@101 {
 116                         device_type = "cpu";
 117                         compatible = "qcom,kryo";
 118                         reg = <0x0 0x101>;
 119                         enable-method = "psci";
 120                         next-level-cache = <&L2_1>;
 121                 };
 122
 123                 cpu-map {
 124                         cluster0 {
 125                                 core0 {
 126                                         cpu = <&CPU0>;
 127                                 };
 128
 129                                 core1 {
 130                                         cpu = <&CPU1>;
 131                                 };
 132                         };
 133
 134                         cluster1 {
 135                                 core0 {
 136                                         cpu = <&CPU2>;
 137                                 };
 138
 139                                 core1 {
 140                                         cpu = <&CPU3>;
 141                                 };
 142                         };
 143                 };
 144         };
 145
 146         thermal-zones {
 147                 cpu-thermal0 {
 148                         polling-delay-passive = <250>;
 149                         polling-delay = <1000>;
 150
 151                         thermal-sensors = <&tsens0 3>;
 152
 153                         trips {
 154                                 cpu_alert0: trip0 {
 155                                         temperature = <75000>;
 156                                         hysteresis = <2000>;
 157                                         type = "passive";
 158                                 };
 159
 160                                 cpu_crit0: trip1 {
 161                                         temperature = <110000>;
 162                                         hysteresis = <2000>;
 163                                         type = "critical";
 164                                 };
 165                         };
 166                 };
 167
 168                 cpu-thermal1 {
 169                         polling-delay-passive = <250>;
 170                         polling-delay = <1000>;
 171
 172                         thermal-sensors = <&tsens0 5>;
 173
 174                         trips {
 175                                 cpu_alert1: trip0 {
 176                                         temperature = <75000>;
 177                                         hysteresis = <2000>;
 178                                         type = "passive";
 179                                 };
 180
 181                                 cpu_crit1: trip1 {
 182                                         temperature = <110000>;
 183                                         hysteresis = <2000>;
 184                                         type = "critical";
 185                                 };
 186                         };
 187                 };
 188
 189                 cpu-thermal2 {
 190                         polling-delay-passive = <250>;
 191                         polling-delay = <1000>;
 192
 193                         thermal-sensors = <&tsens0 8>;
 194
 195                         trips {
 196                                 cpu_alert2: trip0 {
 197                                         temperature = <75000>;
 198                                         hysteresis = <2000>;
 199                                         type = "passive";
 200                                 };
 201
 202                                 cpu_crit2: trip1 {
 203                                         temperature = <110000>;
 204                                         hysteresis = <2000>;
 205                                         type = "critical";
 206                                 };
 207                         };
 208                 };
 209
 210                 cpu-thermal3 {
 211                         polling-delay-passive = <250>;
 212                         polling-delay = <1000>;
 213
 214                         thermal-sensors = <&tsens0 10>;
 215
 216                         trips {
 217                                 cpu_alert3: trip0 {
 218                                         temperature = <75000>;
 219                                         hysteresis = <2000>;
 220                                         type = "passive";
 221                                 };
 222
 223                                 cpu_crit3: trip1 {
 224                                         temperature = <110000>;
 225                                         hysteresis = <2000>;
 226                                         type = "critical";
 227                                 };
 228                         };
 229                 };
 230         };
 231
 232         timer {
 233                 compatible = "arm,armv8-timer";
 234                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 235                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 236                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 237                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 238         };
 239
 240         clocks {
 241                 xo_board: xo_board {
 242                         compatible = "fixed-clock";
 243                         #clock-cells = <0>;
 244                         clock-frequency = <19200000>;
 245                         clock-output-names = "xo_board";
 246                 };
 247
 248                 sleep_clk: sleep_clk {
 249                         compatible = "fixed-clock";
 250                         #clock-cells = <0>;
 251                         clock-frequency = <32764>;
 252                         clock-output-names = "sleep_clk";
 253                 };
 254         };
 255
 256         psci {
 257                 compatible = "arm,psci-1.0";
 258                 method = "smc";
 259         };
 260
 261         firmware {
 262                 scm {
 263                         compatible = "qcom,scm-msm8996";
 264                 };
 265         };
 266
 267         tcsr_mutex: hwlock {
 268                 compatible = "qcom,tcsr-mutex";
 269                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 270                 #hwlock-cells = <1>;
 271         };
 272
 273         smem {
 274                 compatible = "qcom,smem";
 275                 memory-region = <&smem_mem>;
 276                 hwlocks = <&tcsr_mutex 3>;
 277         };
 278
 279         rpm-glink {
 280                 compatible = "qcom,glink-rpm";
 281
 282                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 283
 284                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 285
 286                 mboxes = <&apcs_glb 0>;
 287
 288                 rpm_requests {
 289                         compatible = "qcom,rpm-msm8996";
 290                         qcom,glink-channels = "rpm_requests";
 291
 292                         pm8994-regulators {
 293                                 compatible = "qcom,rpm-pm8994-regulators";
 294
 295                                 pm8994_s1: s1 {};
 296                                 pm8994_s2: s2 {};
 297                                 pm8994_s3: s3 {};
 298                                 pm8994_s4: s4 {};
 299                                 pm8994_s5: s5 {};
 300                                 pm8994_s6: s6 {};
 301                                 pm8994_s7: s7 {};
 302                                 pm8994_s8: s8 {};
 303                                 pm8994_s9: s9 {};
 304                                 pm8994_s10: s10 {};
 305                                 pm8994_s11: s11 {};
 306                                 pm8994_s12: s12 {};
 307
 308                                 pm8994_l1: l1 {};
 309                                 pm8994_l2: l2 {};
 310                                 pm8994_l3: l3 {};
 311                                 pm8994_l4: l4 {};
 312                                 pm8994_l5: l5 {};
 313                                 pm8994_l6: l6 {};
 314                                 pm8994_l7: l7 {};
 315                                 pm8994_l8: l8 {};
 316                                 pm8994_l9: l9 {};
 317                                 pm8994_l10: l10 {};
 318                                 pm8994_l11: l11 {};
 319                                 pm8994_l12: l12 {};
 320                                 pm8994_l13: l13 {};
 321                                 pm8994_l14: l14 {};
 322                                 pm8994_l15: l15 {};
 323                                 pm8994_l16: l16 {};
 324                                 pm8994_l17: l17 {};
 325                                 pm8994_l18: l18 {};
 326                                 pm8994_l19: l19 {};
 327                                 pm8994_l20: l20 {};
 328                                 pm8994_l21: l21 {};
 329                                 pm8994_l22: l22 {};
 330                                 pm8994_l23: l23 {};
 331                                 pm8994_l24: l24 {};
 332                                 pm8994_l25: l25 {};
 333                                 pm8994_l26: l26 {};
 334                                 pm8994_l27: l27 {};
 335                                 pm8994_l28: l28 {};
 336                                 pm8994_l29: l29 {};
 337                                 pm8994_l30: l30 {};
 338                                 pm8994_l31: l31 {};
 339                                 pm8994_l32: l32 {};
 340                         };
 341
 342                 };
 343         };
 344
 345         soc: soc {
 346                 #address-cells = <1>;
 347                 #size-cells = <1>;
 348                 ranges = <0 0 0 0xffffffff>;
 349                 compatible = "simple-bus";
 350
 351                 rpm_msg_ram: memory@68000 {
 352                         compatible = "qcom,rpm-msg-ram";
 353                         reg = <0x68000 0x6000>;
 354                 };
 355
 356                 tcsr_mutex_regs: syscon@740000 {
 357                         compatible = "syscon";
 358                         reg = <0x740000 0x20000>;
 359                 };
 360
 361                 intc: interrupt-controller@9bc0000 {
 362                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
 363                         #interrupt-cells = <3>;
 364                         interrupt-controller;
 365                         #redistributor-regions = <1>;
 366                         redistributor-stride = <0x0 0x40000>;
 367                         reg = <0x09bc0000 0x10000>,
 368                               <0x09c00000 0x100000>;
 369                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 370                 };
 371
 372                 apcs: syscon@9820000 {
 373                         compatible = "syscon";
 374                         reg = <0x9820000 0x1000>;
 375                 };
 376
 377                 apcs_glb: mailbox@9820000 {
 378                         compatible = "qcom,msm8996-apcs-hmss-global";
 379                         reg = <0x9820000 0x1000>;
 380
 381                         #mbox-cells = <1>;
 382                 };
 383
 384                 gcc: clock-controller@300000 {
 385                         compatible = "qcom,gcc-msm8996";
 386                         #clock-cells = <1>;
 387                         #reset-cells = <1>;
 388                         #power-domain-cells = <1>;
 389                         reg = <0x300000 0x90000>;
 390                 };
 391
 392                 kryocc: clock-controller@6400000 {
 393                         compatible = "qcom,apcc-msm8996";
 394                         reg = <0x6400000 0x90000>;
 395                         #clock-cells = <1>;
 396                 };
 397
 398                 blsp1_spi0: spi@07575000 {
 399                         compatible = "qcom,spi-qup-v2.2.1";
 400                         reg = <0x07575000 0x600>;
 401                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 403                                  <&gcc GCC_BLSP1_AHB_CLK>;
 404                         clock-names = "core", "iface";
 405                         pinctrl-names = "default", "sleep";
 406                         pinctrl-0 = <&blsp1_spi0_default>;
 407                         pinctrl-1 = <&blsp1_spi0_sleep>;
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         status = "disabled";
 411                 };
 412
 413                 blsp2_i2c0: i2c@075b5000 {
 414                         compatible = "qcom,i2c-qup-v2.2.1";
 415                         reg = <0x075b5000 0x1000>;
 416                         interrupts = <GIC_SPI 101 0>;
 417                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 418                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 419                         clock-names = "iface", "core";
 420                         pinctrl-names = "default", "sleep";
 421                         pinctrl-0 = <&blsp2_i2c0_default>;
 422                         pinctrl-1 = <&blsp2_i2c0_sleep>;
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425                         status = "disabled";
 426                 };
 427
 428                 tsens0: thermal-sensor@4a8000 {
 429                         compatible = "qcom,msm8996-tsens";
 430                         reg = <0x4a8000 0x2000>;
 431                         #thermal-sensor-cells = <1>;
 432                 };
 433
 434                 blsp2_uart1: serial@75b0000 {
 435                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 436                         reg = <0x75b0000 0x1000>;
 437                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 439                                  <&gcc GCC_BLSP2_AHB_CLK>;
 440                         clock-names = "core", "iface";
 441                         status = "disabled";
 442                 };
 443
 444                 blsp2_i2c1: i2c@075b6000 {
 445                         compatible = "qcom,i2c-qup-v2.2.1";
 446                         reg = <0x075b6000 0x1000>;
 447                         interrupts = <GIC_SPI 102 0>;
 448                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 449                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
 450                         clock-names = "iface", "core";
 451                         pinctrl-names = "default", "sleep";
 452                         pinctrl-0 = <&blsp2_i2c1_default>;
 453                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                         status = "disabled";
 457                 };
 458
 459                 blsp2_uart2: serial@75b1000 {
 460                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 461                         reg = <0x075b1000 0x1000>;
 462                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 464                                  <&gcc GCC_BLSP2_AHB_CLK>;
 465                         clock-names = "core", "iface";
 466                         status = "disabled";
 467                 };
 468
 469                 blsp1_i2c2: i2c@07577000 {
 470                         compatible = "qcom,i2c-qup-v2.2.1";
 471                         reg = <0x07577000 0x1000>;
 472                         interrupts = <GIC_SPI 97 0>;
 473                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 474                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 475                         clock-names = "iface", "core";
 476                         pinctrl-names = "default", "sleep";
 477                         pinctrl-0 = <&blsp1_i2c2_default>;
 478                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 479                         #address-cells = <1>;
 480                         #size-cells = <0>;
 481                         status = "disabled";
 482                 };
 483
 484                 blsp2_spi5: spi@075ba000{
 485                         compatible = "qcom,spi-qup-v2.2.1";
 486                         reg = <0x075ba000 0x600>;
 487                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 488                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
 489                                  <&gcc GCC_BLSP2_AHB_CLK>;
 490                         clock-names = "core", "iface";
 491                         pinctrl-names = "default", "sleep";
 492                         pinctrl-0 = <&blsp2_spi5_default>;
 493                         pinctrl-1 = <&blsp2_spi5_sleep>;
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         status = "disabled";
 497                 };
 498
 499                 sdhc2: sdhci@74a4900 {
 500                          status = "disabled";
 501                          compatible = "qcom,sdhci-msm-v4";
 502                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 503                          reg-names = "hc_mem", "core_mem";
 504
 505                          interrupts = <0 125 0>, <0 221 0>;
 506                          interrupt-names = "hc_irq", "pwr_irq";
 507
 508                          clock-names = "iface", "core", "xo";
 509                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 510                          <&gcc GCC_SDCC2_APPS_CLK>,
 511                          <&xo_board>;
 512                          bus-width = <4>;
 513                  };
 514
 515                 msmgpio: pinctrl@1010000 {
 516                         compatible = "qcom,msm8996-pinctrl";
 517                         reg = <0x01010000 0x300000>;
 518                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 519                         gpio-controller;
 520                         #gpio-cells = <2>;
 521                         interrupt-controller;
 522                         #interrupt-cells = <2>;
 523                 };
 524
 525                 timer@09840000 {
 526                         #address-cells = <1>;
 527                         #size-cells = <1>;
 528                         ranges;
 529                         compatible = "arm,armv7-timer-mem";
 530                         reg = <0x09840000 0x1000>;
 531                         clock-frequency = <19200000>;
 532
 533                         frame@9850000 {
 534                                 frame-number = <0>;
 535                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 536                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 537                                 reg = <0x09850000 0x1000>,
 538                                       <0x09860000 0x1000>;
 539                         };
 540
 541                         frame@9870000 {
 542                                 frame-number = <1>;
 543                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 544                                 reg = <0x09870000 0x1000>;
 545                                 status = "disabled";
 546                         };
 547
 548                         frame@9880000 {
 549                                 frame-number = <2>;
 550                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 551                                 reg = <0x09880000 0x1000>;
 552                                 status = "disabled";
 553                         };
 554
 555                         frame@9890000 {
 556                                 frame-number = <3>;
 557                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 558                                 reg = <0x09890000 0x1000>;
 559                                 status = "disabled";
 560                         };
 561
 562                         frame@98a0000 {
 563                                 frame-number = <4>;
 564                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 565                                 reg = <0x098a0000 0x1000>;
 566                                 status = "disabled";
 567                         };
 568
 569                         frame@98b0000 {
 570                                 frame-number = <5>;
 571                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 572                                 reg = <0x098b0000 0x1000>;
 573                                 status = "disabled";
 574                         };
 575
 576                         frame@98c0000 {
 577                                 frame-number = <6>;
 578                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 579                                 reg = <0x098c0000 0x1000>;
 580                                 status = "disabled";
 581                         };
 582                 };
 583
 584                 spmi_bus: qcom,spmi@400f000 {
 585                         compatible = "qcom,spmi-pmic-arb";
 586                         reg = <0x400f000 0x1000>,
 587                               <0x4400000 0x800000>,
 588                               <0x4c00000 0x800000>,
 589                               <0x5800000 0x200000>,
 590                               <0x400a000 0x002100>;
 591                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 592                         interrupt-names = "periph_irq";
 593                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 594                         qcom,ee = <0>;
 595                         qcom,channel = <0>;
 596                         #address-cells = <2>;
 597                         #size-cells = <0>;
 598                         interrupt-controller;
 599                         #interrupt-cells = <4>;
 600                 };
 601
 602                 mmcc: clock-controller@8c0000 {
 603                         compatible = "qcom,mmcc-msm8996";
 604                         #clock-cells = <1>;
 605                         #reset-cells = <1>;
 606                         #power-domain-cells = <1>;
 607                         reg = <0x8c0000 0x40000>;
 608                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 609                                           <&mmcc MMPLL1_PLL>,
 610                                           <&mmcc MMPLL3_PLL>,
 611                                           <&mmcc MMPLL4_PLL>,
 612                                           <&mmcc MMPLL5_PLL>;
 613                         assigned-clock-rates = <624000000>,
 614                                                <810000000>,
 615                                                <980000000>,
 616                                                <960000000>,
 617                                                <825000000>;
 618                 };
 619
 620                 qfprom@74000 {
 621                         compatible = "qcom,qfprom";
 622                         reg = <0x74000 0x8ff>;
 623                         #address-cells = <1>;
 624                         #size-cells = <1>;
 625
 626                         qusb2p_hstx_trim: hstx_trim@24e {
 627                                 reg = <0x24e 0x2>;
 628                                 bits = <5 4>;
 629                         };
 630
 631                         qusb2s_hstx_trim: hstx_trim@24f {
 632                                 reg = <0x24f 0x1>;
 633                                 bits = <1 4>;
 634                         };
 635                 };
 636
 637                 phy@34000 {
 638                         compatible = "qcom,msm8996-qmp-pcie-phy";
 639                         reg = <0x34000 0x488>;
 640                         #clock-cells = <1>;
 641                         #address-cells = <1>;
 642                         #size-cells = <1>;
 643                         ranges;
 644
 645                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 646                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 647                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 648                         clock-names = "aux", "cfg_ahb", "ref";
 649
 650                         vdda-phy-supply = <&pm8994_l28>;
 651                         vdda-pll-supply = <&pm8994_l12>;
 652
 653                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 654                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 655                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 656                         reset-names = "phy", "common", "cfg";
 657                         status = "disabled";
 658
 659                         pciephy_0: lane@35000 {
 660                                 reg = <0x035000 0x130>,
 661                                         <0x035200 0x200>,
 662                                         <0x035400 0x1dc>;
 663                                 #phy-cells = <0>;
 664
 665                                 clock-output-names = "pcie_0_pipe_clk_src";
 666                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 667                                 clock-names = "pipe0";
 668                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 669                                 reset-names = "lane0";
 670                         };
 671
 672                         pciephy_1: lane@36000 {
 673                                 reg = <0x036000 0x130>,
 674                                         <0x036200 0x200>,
 675                                         <0x036400 0x1dc>;
 676                                 #phy-cells = <0>;
 677
 678                                 clock-output-names = "pcie_1_pipe_clk_src";
 679                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 680                                 clock-names = "pipe1";
 681                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 682                                 reset-names = "lane1";
 683                         };
 684
 685                         pciephy_2: lane@37000 {
 686                                 reg = <0x037000 0x130>,
 687                                         <0x037200 0x200>,
 688                                         <0x037400 0x1dc>;
 689                                 #phy-cells = <0>;
 690
 691                                 clock-output-names = "pcie_2_pipe_clk_src";
 692                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 693                                 clock-names = "pipe2";
 694                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 695                                 reset-names = "lane2";
 696                         };
 697                 };
 698
 699                 phy@7410000 {
 700                         compatible = "qcom,msm8996-qmp-usb3-phy";
 701                         reg = <0x7410000 0x1c4>;
 702                         #clock-cells = <1>;
 703                         #address-cells = <1>;
 704                         #size-cells = <1>;
 705                         ranges;
 706
 707                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 708                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 709                                 <&gcc GCC_USB3_CLKREF_CLK>;
 710                         clock-names = "aux", "cfg_ahb", "ref";
 711
 712                         vdda-phy-supply = <&pm8994_l28>;
 713                         vdda-pll-supply = <&pm8994_l12>;
 714
 715                         resets = <&gcc GCC_USB3_PHY_BCR>,
 716                                 <&gcc GCC_USB3PHY_PHY_BCR>;
 717                         reset-names = "phy", "common";
 718                         status = "disabled";
 719
 720                         ssusb_phy_0: lane@7410200 {
 721                                 reg = <0x7410200 0x200>,
 722                                         <0x7410400 0x130>,
 723                                         <0x7410600 0x1a8>;
 724                                 #phy-cells = <0>;
 725
 726                                 clock-output-names = "usb3_phy_pipe_clk_src";
 727                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
 728                                 clock-names = "pipe0";
 729                         };
 730                 };
 731
 732                 hsusb_phy1: phy@7411000 {
 733                         compatible = "qcom,msm8996-qusb2-phy";
 734                         reg = <0x7411000 0x180>;
 735                         #phy-cells = <0>;
 736
 737                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 738                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
 739                         clock-names = "cfg_ahb", "ref";
 740
 741                         vdda-pll-supply = <&pm8994_l12>;
 742                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 743
 744                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 745                         nvmem-cells = <&qusb2p_hstx_trim>;
 746                         status = "disabled";
 747                 };
 748
 749                 hsusb_phy2: phy@7412000 {
 750                         compatible = "qcom,msm8996-qusb2-phy";
 751                         reg = <0x7412000 0x180>;
 752                         #phy-cells = <0>;
 753
 754                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 755                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
 756                         clock-names = "cfg_ahb", "ref";
 757
 758                         vdda-pll-supply = <&pm8994_l12>;
 759                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 760
 761                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
 762                         nvmem-cells = <&qusb2s_hstx_trim>;
 763                         status = "disabled";
 764                 };
 765
 766                 usb2: usb@7600000 {
 767                         compatible = "qcom,dwc3";
 768                         #address-cells = <1>;
 769                         #size-cells = <1>;
 770                         ranges;
 771
 772                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
 773                                 <&gcc GCC_USB20_MASTER_CLK>,
 774                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 775                                 <&gcc GCC_USB20_SLEEP_CLK>,
 776                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 777
 778                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 779                                           <&gcc GCC_USB20_MASTER_CLK>;
 780                         assigned-clock-rates = <19200000>, <60000000>;
 781
 782                         power-domains = <&gcc USB30_GDSC>;
 783                         status = "disabled";
 784
 785                         dwc3@7600000 {
 786                                 compatible = "snps,dwc3";
 787                                 reg = <0x7600000 0xcc00>;
 788                                 interrupts = <0 138 0>;
 789                                 phys = <&hsusb_phy2>;
 790                                 phy-names = "usb2-phy";
 791                                 snps,dis_u2_susphy_quirk;
 792                                 snps,dis_enblslpm_quirk;
 793                         };
 794                 };
 795
 796                 usb3: usb@6a00000 {
 797                         compatible = "qcom,dwc3";
 798                         #address-cells = <1>;
 799                         #size-cells = <1>;
 800                         ranges;
 801
 802                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 803                                 <&gcc GCC_USB30_MASTER_CLK>,
 804                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
 805                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 806                                 <&gcc GCC_USB30_SLEEP_CLK>,
 807                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 808
 809                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 810                                           <&gcc GCC_USB30_MASTER_CLK>;
 811                         assigned-clock-rates = <19200000>, <120000000>;
 812
 813                         power-domains = <&gcc USB30_GDSC>;
 814                         status = "disabled";
 815
 816                         dwc3@6a00000 {
 817                                 compatible = "snps,dwc3";
 818                                 reg = <0x6a00000 0xcc00>;
 819                                 interrupts = <0 131 0>;
 820                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 821                                 phy-names = "usb2-phy", "usb3-phy";
 822                                 snps,dis_u2_susphy_quirk;
 823                                 snps,dis_enblslpm_quirk;
 824                         };
 825                 };
 826         };
 827
 828         adsp-pil {
 829                 compatible = "qcom,msm8996-adsp-pil";
 830
 831                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
 832                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 833                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 834                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 835                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 836                 interrupt-names = "wdog", "fatal", "ready",
 837                                   "handover", "stop-ack";
 838
 839                 clocks = <&xo_board>;
 840                 clock-names = "xo";
 841
 842                 memory-region = <&adsp_region>;
 843
 844                 qcom,smem-states = <&adsp_smp2p_out 0>;
 845                 qcom,smem-state-names = "stop";
 846
 847                 smd-edge {
 848                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 849
 850                         label = "lpass";
 851                         qcom,ipc = <&apcs 16 8>;
 852                         qcom,smd-edge = <1>;
 853                         qcom,remote-pid = <2>;
 854                 };
 855         };
 856
 857         adsp-smp2p {
 858                 compatible = "qcom,smp2p";
 859                 qcom,smem = <443>, <429>;
 860
 861                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 862
 863                 qcom,ipc = <&apcs 16 10>;
 864
 865                 qcom,local-pid = <0>;
 866                 qcom,remote-pid = <2>;
 867
 868                 adsp_smp2p_out: master-kernel {
 869                         qcom,entry-name = "master-kernel";
 870                         #qcom,smem-state-cells = <1>;
 871                 };
 872
 873                 adsp_smp2p_in: slave-kernel {
 874                         qcom,entry-name = "slave-kernel";
 875
 876                         interrupt-controller;
 877                         #interrupt-cells = <2>;
 878                 };
 879         };
 880
 881         modem-smp2p {
 882                 compatible = "qcom,smp2p";
 883                 qcom,smem = <435>, <428>;
 884
 885                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 886
 887                 qcom,ipc = <&apcs 16 14>;
 888
 889                 qcom,local-pid = <0>;
 890                 qcom,remote-pid = <1>;
 891
 892                 modem_smp2p_out: master-kernel {
 893                         qcom,entry-name = "master-kernel";
 894                         #qcom,smem-state-cells = <1>;
 895                 };
 896
 897                 modem_smp2p_in: slave-kernel {
 898                         qcom,entry-name = "slave-kernel";
 899
 900                         interrupt-controller;
 901                         #interrupt-cells = <2>;
 902                 };
 903         };
 904
 905         smp2p-slpi {
 906                 compatible = "qcom,smp2p";
 907                 qcom,smem = <481>, <430>;
 908
 909                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 910
 911                 qcom,ipc = <&apcs 16 26>;
 912
 913                 qcom,local-pid = <0>;
 914                 qcom,remote-pid = <3>;
 915
 916                 slpi_smp2p_in: slave-kernel {
 917                         qcom,entry-name = "slave-kernel";
 918                         interrupt-controller;
 919                         #interrupt-cells = <2>;
 920                 };
 921
 922                 slpi_smp2p_out: master-kernel {
 923                         qcom,entry-name = "master-kernel";
 924                         #qcom,smem-state-cells = <1>;
 925                 };
 926         };
 927
 928 };
 929 #include "msm8996-pins.dtsi"