arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi

   1 /*
   2  * Device Tree Source for the r8a7795 ES1.x SoC
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include "r8a7795.dtsi"
  12
  13 &soc {
  14         xhci1: usb@ee0400000 {
  15                 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
  16                 reg = <0 0xee040000 0 0xc00>;
  17                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  18                 clocks = <&cpg CPG_MOD 327>;
  19                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  20                 resets = <&cpg 327>;
  21                 status = "disabled";
  22         };
  23
  24         /delete-node/ usb-phy@ee0e0200;
  25         /delete-node/ usb@ee0e0100;
  26         /delete-node/ usb@ee0e0000;
  27         /delete-node/ usb@e659c000;
  28
  29         /delete-node/ dma-controller@e6460000;
  30         /delete-node/ dma-controller@e6470000;
  31
  32         fcpf2: fcp@fe952000 {
  33                 compatible = "renesas,fcpf";
  34                 reg = <0 0xfe952000 0 0x200>;
  35                 clocks = <&cpg CPG_MOD 613>;
  36                 power-domains = <&sysc R8A7795_PD_A3VP>;
  37                 resets = <&cpg 613>;
  38         };
  39
  40         vspi2: vsp@fe9c0000 {
  41                 compatible = "renesas,vsp2";
  42                 reg = <0 0xfe9c0000 0 0x8000>;
  43                 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
  44                 clocks = <&cpg CPG_MOD 629>;
  45                 power-domains = <&sysc R8A7795_PD_A3VP>;
  46                 resets = <&cpg 629>;
  47
  48                 renesas,fcp = <&fcpvi2>;
  49         };
  50
  51         fcpvi2: fcp@fe9cf000 {
  52                 compatible = "renesas,fcpv";
  53                 reg = <0 0xfe9cf000 0 0x200>;
  54                 clocks = <&cpg CPG_MOD 609>;
  55                 power-domains = <&sysc R8A7795_PD_A3VP>;
  56                 resets = <&cpg 609>;
  57         };
  58
  59         vspd3: vsp@fea38000 {
  60                 compatible = "renesas,vsp2";
  61                 reg = <0 0xfea38000 0 0x4000>;
  62                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
  63                 clocks = <&cpg CPG_MOD 620>;
  64                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  65                 resets = <&cpg 620>;
  66
  67                 renesas,fcp = <&fcpvd3>;
  68         };
  69
  70         fcpvd3: fcp@fea3f000 {
  71                 compatible = "renesas,fcpv";
  72                 reg = <0 0xfea3f000 0 0x200>;
  73                 clocks = <&cpg CPG_MOD 600>;
  74                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  75                 resets = <&cpg 600>;
  76         };
  77
  78         fdp1@fe948000 {
  79                 compatible = "renesas,fdp1";
  80                 reg = <0 0xfe948000 0 0x2400>;
  81                 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
  82                 clocks = <&cpg CPG_MOD 117>;
  83                 power-domains = <&sysc R8A7795_PD_A3VP>;
  84                 resets = <&cpg 117>;
  85                 renesas,fcp = <&fcpf2>;
  86         };
  87 };
  88
  89 &du {
  90         vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
  91 };