arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 ethernet0 = &gmac2io;
  31                 ethernet1 = &gmac2phy;
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53", "arm,armv8";
  41                         reg = <0x0 0x0>;
  42                         clocks = <&cru ARMCLK>;
  43                         #cooling-cells = <2>;
  44                         dynamic-power-coefficient = <120>;
  45                         enable-method = "psci";
  46                         next-level-cache = <&l2>;
  47                         operating-points-v2 = <&cpu0_opp_table>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0x0 0x1>;
  54                         clocks = <&cru ARMCLK>;
  55                         #cooling-cells = <2>;
  56                         dynamic-power-coefficient = <120>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&l2>;
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                 };
  61
  62                 cpu2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x0 0x2>;
  66                         clocks = <&cru ARMCLK>;
  67                         #cooling-cells = <2>;
  68                         dynamic-power-coefficient = <120>;
  69                         enable-method = "psci";
  70                         next-level-cache = <&l2>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53", "arm,armv8";
  77                         reg = <0x0 0x3>;
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>;
  80                         dynamic-power-coefficient = <120>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&l2>;
  83                         operating-points-v2 = <&cpu0_opp_table>;
  84                 };
  85
  86                 l2: l2-cache0 {
  87                         compatible = "cache";
  88                 };
  89         };
  90
  91         cpu0_opp_table: opp_table0 {
  92                 compatible = "operating-points-v2";
  93                 opp-shared;
  94
  95                 opp-408000000 {
  96                         opp-hz = /bits/ 64 <408000000>;
  97                         opp-microvolt = <950000>;
  98                         clock-latency-ns = <40000>;
  99                         opp-suspend;
 100                 };
 101                 opp-600000000 {
 102                         opp-hz = /bits/ 64 <600000000>;
 103                         opp-microvolt = <950000>;
 104                         clock-latency-ns = <40000>;
 105                 };
 106                 opp-816000000 {
 107                         opp-hz = /bits/ 64 <816000000>;
 108                         opp-microvolt = <1000000>;
 109                         clock-latency-ns = <40000>;
 110                 };
 111                 opp-1008000000 {
 112                         opp-hz = /bits/ 64 <1008000000>;
 113                         opp-microvolt = <1100000>;
 114                         clock-latency-ns = <40000>;
 115                 };
 116                 opp-1200000000 {
 117                         opp-hz = /bits/ 64 <1200000000>;
 118                         opp-microvolt = <1225000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp-1296000000 {
 122                         opp-hz = /bits/ 64 <1296000000>;
 123                         opp-microvolt = <1300000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126         };
 127
 128         amba {
 129                 compatible = "simple-bus";
 130                 #address-cells = <2>;
 131                 #size-cells = <2>;
 132                 ranges;
 133
 134                 dmac: dmac@ff1f0000 {
 135                         compatible = "arm,pl330", "arm,primecell";
 136                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 137                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 139                         clocks = <&cru ACLK_DMAC>;
 140                         clock-names = "apb_pclk";
 141                         #dma-cells = <1>;
 142                 };
 143         };
 144
 145         arm-pmu {
 146                 compatible = "arm,cortex-a53-pmu";
 147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 152         };
 153
 154         psci {
 155                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 156                 method = "smc";
 157         };
 158
 159         timer {
 160                 compatible = "arm,armv8-timer";
 161                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 163                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 164                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 165         };
 166
 167         xin24m: xin24m {
 168                 compatible = "fixed-clock";
 169                 #clock-cells = <0>;
 170                 clock-frequency = <24000000>;
 171                 clock-output-names = "xin24m";
 172         };
 173
 174         i2s0: i2s@ff000000 {
 175                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 176                 reg = <0x0 0xff000000 0x0 0x1000>;
 177                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 178                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 179                 clock-names = "i2s_clk", "i2s_hclk";
 180                 dmas = <&dmac 11>, <&dmac 12>;
 181                 dma-names = "tx", "rx";
 182                 status = "disabled";
 183         };
 184
 185         i2s1: i2s@ff010000 {
 186                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 187                 reg = <0x0 0xff010000 0x0 0x1000>;
 188                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 190                 clock-names = "i2s_clk", "i2s_hclk";
 191                 dmas = <&dmac 14>, <&dmac 15>;
 192                 dma-names = "tx", "rx";
 193                 status = "disabled";
 194         };
 195
 196         i2s2: i2s@ff020000 {
 197                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 198                 reg = <0x0 0xff020000 0x0 0x1000>;
 199                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 201                 clock-names = "i2s_clk", "i2s_hclk";
 202                 dmas = <&dmac 0>, <&dmac 1>;
 203                 dma-names = "tx", "rx";
 204                 status = "disabled";
 205         };
 206
 207         spdif: spdif@ff030000 {
 208                 compatible = "rockchip,rk3328-spdif";
 209                 reg = <0x0 0xff030000 0x0 0x1000>;
 210                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 212                 clock-names = "mclk", "hclk";
 213                 dmas = <&dmac 10>;
 214                 dma-names = "tx";
 215                 pinctrl-names = "default";
 216                 pinctrl-0 = <&spdifm2_tx>;
 217                 status = "disabled";
 218         };
 219
 220         pdm: pdm@ff040000 {
 221                 compatible = "rockchip,pdm";
 222                 reg = <0x0 0xff040000 0x0 0x1000>;
 223                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 224                 clock-names = "pdm_clk", "pdm_hclk";
 225                 dmas = <&dmac 16>;
 226                 dma-names = "rx";
 227                 pinctrl-names = "default", "sleep";
 228                 pinctrl-0 = <&pdmm0_clk
 229                              &pdmm0_sdi0
 230                              &pdmm0_sdi1
 231                              &pdmm0_sdi2
 232                              &pdmm0_sdi3>;
 233                 pinctrl-1 = <&pdmm0_clk_sleep
 234                              &pdmm0_sdi0_sleep
 235                              &pdmm0_sdi1_sleep
 236                              &pdmm0_sdi2_sleep
 237                              &pdmm0_sdi3_sleep>;
 238                 status = "disabled";
 239         };
 240
 241         grf: syscon@ff100000 {
 242                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 243                 reg = <0x0 0xff100000 0x0 0x1000>;
 244                 #address-cells = <1>;
 245                 #size-cells = <1>;
 246
 247                 io_domains: io-domains {
 248                         compatible = "rockchip,rk3328-io-voltage-domain";
 249                         status = "disabled";
 250                 };
 251
 252                 power: power-controller {
 253                         compatible = "rockchip,rk3328-power-controller";
 254                         #power-domain-cells = <1>;
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257
 258                         power-domain@RK3328_PD_HEVC {
 259                                 reg = <RK3328_PD_HEVC>;
 260                         };
 261                         power-domain@RK3328_PD_VIDEO {
 262                                 reg = <RK3328_PD_VIDEO>;
 263                         };
 264                         power-domain@RK3328_PD_VPU {
 265                                 reg = <RK3328_PD_VPU>;
 266                         };
 267                 };
 268
 269                 reboot-mode {
 270                         compatible = "syscon-reboot-mode";
 271                         offset = <0x5c8>;
 272                         mode-normal = <BOOT_NORMAL>;
 273                         mode-recovery = <BOOT_RECOVERY>;
 274                         mode-bootloader = <BOOT_FASTBOOT>;
 275                         mode-loader = <BOOT_BL_DOWNLOAD>;
 276                 };
 277
 278         };
 279
 280         uart0: serial@ff110000 {
 281                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 282                 reg = <0x0 0xff110000 0x0 0x100>;
 283                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 284                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 285                 clock-names = "baudclk", "apb_pclk";
 286                 dmas = <&dmac 2>, <&dmac 3>;
 287                 dma-names = "tx", "rx";
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 290                 reg-io-width = <4>;
 291                 reg-shift = <2>;
 292                 status = "disabled";
 293         };
 294
 295         uart1: serial@ff120000 {
 296                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 297                 reg = <0x0 0xff120000 0x0 0x100>;
 298                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 300                 clock-names = "baudclk", "apb_pclk";
 301                 dmas = <&dmac 4>, <&dmac 5>;
 302                 dma-names = "tx", "rx";
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 305                 reg-io-width = <4>;
 306                 reg-shift = <2>;
 307                 status = "disabled";
 308         };
 309
 310         uart2: serial@ff130000 {
 311                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 312                 reg = <0x0 0xff130000 0x0 0x100>;
 313                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 314                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 315                 clock-names = "baudclk", "apb_pclk";
 316                 dmas = <&dmac 6>, <&dmac 7>;
 317                 dma-names = "tx", "rx";
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&uart2m1_xfer>;
 320                 reg-io-width = <4>;
 321                 reg-shift = <2>;
 322                 status = "disabled";
 323         };
 324
 325         i2c0: i2c@ff150000 {
 326                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 327                 reg = <0x0 0xff150000 0x0 0x1000>;
 328                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 332                 clock-names = "i2c", "pclk";
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&i2c0_xfer>;
 335                 status = "disabled";
 336         };
 337
 338         i2c1: i2c@ff160000 {
 339                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 340                 reg = <0x0 0xff160000 0x0 0x1000>;
 341                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 345                 clock-names = "i2c", "pclk";
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&i2c1_xfer>;
 348                 status = "disabled";
 349         };
 350
 351         i2c2: i2c@ff170000 {
 352                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 353                 reg = <0x0 0xff170000 0x0 0x1000>;
 354                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 358                 clock-names = "i2c", "pclk";
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&i2c2_xfer>;
 361                 status = "disabled";
 362         };
 363
 364         i2c3: i2c@ff180000 {
 365                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 366                 reg = <0x0 0xff180000 0x0 0x1000>;
 367                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 371                 clock-names = "i2c", "pclk";
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&i2c3_xfer>;
 374                 status = "disabled";
 375         };
 376
 377         spi0: spi@ff190000 {
 378                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 379                 reg = <0x0 0xff190000 0x0 0x1000>;
 380                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 384                 clock-names = "spiclk", "apb_pclk";
 385                 dmas = <&dmac 8>, <&dmac 9>;
 386                 dma-names = "tx", "rx";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 389                 status = "disabled";
 390         };
 391
 392         wdt: watchdog@ff1a0000 {
 393                 compatible = "snps,dw-wdt";
 394                 reg = <0x0 0xff1a0000 0x0 0x100>;
 395                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 396         };
 397
 398         pwm0: pwm@ff1b0000 {
 399                 compatible = "rockchip,rk3328-pwm";
 400                 reg = <0x0 0xff1b0000 0x0 0x10>;
 401                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 402                 clock-names = "pwm", "pclk";
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&pwm0_pin>;
 405                 #pwm-cells = <3>;
 406                 status = "disabled";
 407         };
 408
 409         pwm1: pwm@ff1b0010 {
 410                 compatible = "rockchip,rk3328-pwm";
 411                 reg = <0x0 0xff1b0010 0x0 0x10>;
 412                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 413                 clock-names = "pwm", "pclk";
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&pwm1_pin>;
 416                 #pwm-cells = <3>;
 417                 status = "disabled";
 418         };
 419
 420         pwm2: pwm@ff1b0020 {
 421                 compatible = "rockchip,rk3328-pwm";
 422                 reg = <0x0 0xff1b0020 0x0 0x10>;
 423                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 424                 clock-names = "pwm", "pclk";
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&pwm2_pin>;
 427                 #pwm-cells = <3>;
 428                 status = "disabled";
 429         };
 430
 431         pwm3: pwm@ff1b0030 {
 432                 compatible = "rockchip,rk3328-pwm";
 433                 reg = <0x0 0xff1b0030 0x0 0x10>;
 434                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 436                 clock-names = "pwm", "pclk";
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&pwmir_pin>;
 439                 #pwm-cells = <3>;
 440                 status = "disabled";
 441         };
 442
 443         thermal-zones {
 444                 soc_thermal: soc-thermal {
 445                         polling-delay-passive = <20>;
 446                         polling-delay = <1000>;
 447                         sustainable-power = <1000>;
 448
 449                         thermal-sensors = <&tsadc 0>;
 450
 451                         trips {
 452                                 threshold: trip-point0 {
 453                                         temperature = <70000>;
 454                                         hysteresis = <2000>;
 455                                         type = "passive";
 456                                 };
 457                                 target: trip-point1 {
 458                                         temperature = <85000>;
 459                                         hysteresis = <2000>;
 460                                         type = "passive";
 461                                 };
 462                                 soc_crit: soc-crit {
 463                                         temperature = <95000>;
 464                                         hysteresis = <2000>;
 465                                         type = "critical";
 466                                 };
 467                         };
 468
 469                         cooling-maps {
 470                                 map0 {
 471                                         trip = <&target>;
 472                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 473                                         contribution = <4096>;
 474                                 };
 475                         };
 476                 };
 477
 478         };
 479
 480         tsadc: tsadc@ff250000 {
 481                 compatible = "rockchip,rk3328-tsadc";
 482                 reg = <0x0 0xff250000 0x0 0x100>;
 483                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 484                 assigned-clocks = <&cru SCLK_TSADC>;
 485                 assigned-clock-rates = <50000>;
 486                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 487                 clock-names = "tsadc", "apb_pclk";
 488                 pinctrl-names = "init", "default", "sleep";
 489                 pinctrl-0 = <&otp_gpio>;
 490                 pinctrl-1 = <&otp_out>;
 491                 pinctrl-2 = <&otp_gpio>;
 492                 resets = <&cru SRST_TSADC>;
 493                 reset-names = "tsadc-apb";
 494                 rockchip,grf = <&grf>;
 495                 rockchip,hw-tshut-temp = <100000>;
 496                 #thermal-sensor-cells = <1>;
 497                 status = "disabled";
 498         };
 499
 500         efuse: efuse@ff260000 {
 501                 compatible = "rockchip,rk3328-efuse";
 502                 reg = <0x0 0xff260000 0x0 0x50>;
 503                 #address-cells = <1>;
 504                 #size-cells = <1>;
 505                 clocks = <&cru SCLK_EFUSE>;
 506                 clock-names = "pclk_efuse";
 507                 rockchip,efuse-size = <0x20>;
 508
 509                 /* Data cells */
 510                 efuse_id: id@7 {
 511                         reg = <0x07 0x10>;
 512                 };
 513                 cpu_leakage: cpu-leakage@17 {
 514                         reg = <0x17 0x1>;
 515                 };
 516                 logic_leakage: logic-leakage@19 {
 517                         reg = <0x19 0x1>;
 518                 };
 519                 efuse_cpu_version: cpu-version@1a {
 520                         reg = <0x1a 0x1>;
 521                         bits = <3 3>;
 522                 };
 523         };
 524
 525         saradc: adc@ff280000 {
 526                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 527                 reg = <0x0 0xff280000 0x0 0x100>;
 528                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 529                 #io-channel-cells = <1>;
 530                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 531                 clock-names = "saradc", "apb_pclk";
 532                 resets = <&cru SRST_SARADC_P>;
 533                 reset-names = "saradc-apb";
 534                 status = "disabled";
 535         };
 536
 537         gpu: gpu@ff300000 {
 538                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 539                 reg = <0x0 0xff300000 0x0 0x30000>;
 540                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 541                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 542                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 543                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 544                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 545                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 546                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 547                 interrupt-names = "gp",
 548                                   "gpmmu",
 549                                   "pp",
 550                                   "pp0",
 551                                   "ppmmu0",
 552                                   "pp1",
 553                                   "ppmmu1";
 554                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 555                 clock-names = "bus", "core";
 556                 resets = <&cru SRST_GPU_A>;
 557         };
 558
 559         h265e_mmu: iommu@ff330200 {
 560                 compatible = "rockchip,iommu";
 561                 reg = <0x0 0xff330200 0 0x100>;
 562                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 563                 interrupt-names = "h265e_mmu";
 564                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 565                 clock-names = "aclk", "iface";
 566                 #iommu-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         vepu_mmu: iommu@ff340800 {
 571                 compatible = "rockchip,iommu";
 572                 reg = <0x0 0xff340800 0x0 0x40>;
 573                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 574                 interrupt-names = "vepu_mmu";
 575                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 576                 clock-names = "aclk", "iface";
 577                 #iommu-cells = <0>;
 578                 status = "disabled";
 579         };
 580
 581         vpu_mmu: iommu@ff350800 {
 582                 compatible = "rockchip,iommu";
 583                 reg = <0x0 0xff350800 0x0 0x40>;
 584                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 585                 interrupt-names = "vpu_mmu";
 586                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 587                 clock-names = "aclk", "iface";
 588                 #iommu-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         rkvdec_mmu: iommu@ff360480 {
 593                 compatible = "rockchip,iommu";
 594                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 595                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 596                 interrupt-names = "rkvdec_mmu";
 597                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 598                 clock-names = "aclk", "iface";
 599                 #iommu-cells = <0>;
 600                 status = "disabled";
 601         };
 602
 603         vop_mmu: iommu@ff373f00 {
 604                 compatible = "rockchip,iommu";
 605                 reg = <0x0 0xff373f00 0x0 0x100>;
 606                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 607                 interrupt-names = "vop_mmu";
 608                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 609                 clock-names = "aclk", "iface";
 610                 #iommu-cells = <0>;
 611                 status = "disabled";
 612         };
 613
 614         cru: clock-controller@ff440000 {
 615                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 616                 reg = <0x0 0xff440000 0x0 0x1000>;
 617                 rockchip,grf = <&grf>;
 618                 #clock-cells = <1>;
 619                 #reset-cells = <1>;
 620                 assigned-clocks =
 621                         /*
 622                          * CPLL should run at 1200, but that is to high for
 623                          * the initial dividers of most of its children.
 624                          * We need set cpll child clk div first,
 625                          * and then set the cpll frequency.
 626                          */
 627                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 628                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 629                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 630                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 631                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 632                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 633                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 634                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 635                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 636                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 637                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 638                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 639                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 640                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 641                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 642                         <&cru SCLK_RTC32K>;
 643                 assigned-clock-parents =
 644                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 645                         <&cru PLL_GPLL>, <&xin24m>,
 646                         <&xin24m>, <&xin24m>;
 647                 assigned-clock-rates =
 648                         <0>, <61440000>,
 649                         <0>, <24000000>,
 650                         <24000000>, <24000000>,
 651                         <15000000>, <15000000>,
 652                         <100000000>, <100000000>,
 653                         <100000000>, <100000000>,
 654                         <50000000>, <100000000>,
 655                         <100000000>, <100000000>,
 656                         <50000000>, <50000000>,
 657                         <50000000>, <50000000>,
 658                         <24000000>, <600000000>,
 659                         <491520000>, <1200000000>,
 660                         <150000000>, <75000000>,
 661                         <75000000>, <150000000>,
 662                         <75000000>, <75000000>,
 663                         <32768>;
 664         };
 665
 666         usb2phy_grf: syscon@ff450000 {
 667                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 668                              "simple-mfd";
 669                 reg = <0x0 0xff450000 0x0 0x10000>;
 670                 #address-cells = <1>;
 671                 #size-cells = <1>;
 672
 673                 u2phy: usb2-phy@100 {
 674                         compatible = "rockchip,rk3328-usb2phy";
 675                         reg = <0x100 0x10>;
 676                         clocks = <&xin24m>;
 677                         clock-names = "phyclk";
 678                         clock-output-names = "usb480m_phy";
 679                         #clock-cells = <0>;
 680                         assigned-clocks = <&cru USB480M>;
 681                         assigned-clock-parents = <&u2phy>;
 682                         status = "disabled";
 683
 684                         u2phy_otg: otg-port {
 685                                 #phy-cells = <0>;
 686                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 687                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 688                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 689                                 interrupt-names = "otg-bvalid", "otg-id",
 690                                                   "linestate";
 691                                 status = "disabled";
 692                         };
 693
 694                         u2phy_host: host-port {
 695                                 #phy-cells = <0>;
 696                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 697                                 interrupt-names = "linestate";
 698                                 status = "disabled";
 699                         };
 700                 };
 701         };
 702
 703         sdmmc: dwmmc@ff500000 {
 704                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 705                 reg = <0x0 0xff500000 0x0 0x4000>;
 706                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 707                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 708                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 709                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 710                 fifo-depth = <0x100>;
 711                 max-frequency = <150000000>;
 712                 status = "disabled";
 713         };
 714
 715         sdio: dwmmc@ff510000 {
 716                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 717                 reg = <0x0 0xff510000 0x0 0x4000>;
 718                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 719                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 720                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 721                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 722                 fifo-depth = <0x100>;
 723                 max-frequency = <150000000>;
 724                 status = "disabled";
 725         };
 726
 727         emmc: dwmmc@ff520000 {
 728                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 729                 reg = <0x0 0xff520000 0x0 0x4000>;
 730                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 731                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 732                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 733                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 734                 fifo-depth = <0x100>;
 735                 max-frequency = <150000000>;
 736                 status = "disabled";
 737         };
 738
 739         gmac2io: ethernet@ff540000 {
 740                 compatible = "rockchip,rk3328-gmac";
 741                 reg = <0x0 0xff540000 0x0 0x10000>;
 742                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 743                 interrupt-names = "macirq";
 744                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 745                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 746                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 747                          <&cru PCLK_MAC2IO>;
 748                 clock-names = "stmmaceth", "mac_clk_rx",
 749                               "mac_clk_tx", "clk_mac_ref",
 750                               "clk_mac_refout", "aclk_mac",
 751                               "pclk_mac";
 752                 resets = <&cru SRST_GMAC2IO_A>;
 753                 reset-names = "stmmaceth";
 754                 rockchip,grf = <&grf>;
 755                 status = "disabled";
 756         };
 757
 758         gmac2phy: ethernet@ff550000 {
 759                 compatible = "rockchip,rk3328-gmac";
 760                 reg = <0x0 0xff550000 0x0 0x10000>;
 761                 rockchip,grf = <&grf>;
 762                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 763                 interrupt-names = "macirq";
 764                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 765                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 766                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 767                          <&cru SCLK_MAC2PHY_OUT>;
 768                 clock-names = "stmmaceth", "mac_clk_rx",
 769                               "mac_clk_tx", "clk_mac_ref",
 770                               "aclk_mac", "pclk_mac",
 771                               "clk_macphy";
 772                 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
 773                 reset-names = "stmmaceth", "mac-phy";
 774                 phy-mode = "rmii";
 775                 phy-handle = <&phy>;
 776                 status = "disabled";
 777
 778                 mdio {
 779                         compatible = "snps,dwmac-mdio";
 780                         #address-cells = <1>;
 781                         #size-cells = <0>;
 782
 783                         phy: phy@0 {
 784                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 785                                 reg = <0>;
 786                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 787                                 resets = <&cru SRST_MACPHY>;
 788                                 pinctrl-names = "default";
 789                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 790                                 phy-is-integrated;
 791                         };
 792                 };
 793         };
 794
 795         usb20_otg: usb@ff580000 {
 796                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 797                              "snps,dwc2";
 798                 reg = <0x0 0xff580000 0x0 0x40000>;
 799                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 800                 clocks = <&cru HCLK_OTG>;
 801                 clock-names = "otg";
 802                 dr_mode = "otg";
 803                 g-np-tx-fifo-size = <16>;
 804                 g-rx-fifo-size = <280>;
 805                 g-tx-fifo-size = <256 128 128 64 32 16>;
 806                 g-use-dma;
 807                 phys = <&u2phy_otg>;
 808                 phy-names = "usb2-phy";
 809                 status = "disabled";
 810         };
 811
 812         usb_host0_ehci: usb@ff5c0000 {
 813                 compatible = "generic-ehci";
 814                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 815                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 816                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 817                 clock-names = "usbhost", "utmi";
 818                 phys = <&u2phy_host>;
 819                 phy-names = "usb";
 820                 status = "disabled";
 821         };
 822
 823         usb_host0_ohci: usb@ff5d0000 {
 824                 compatible = "generic-ohci";
 825                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 826                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 827                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 828                 clock-names = "usbhost", "utmi";
 829                 phys = <&u2phy_host>;
 830                 phy-names = "usb";
 831                 status = "disabled";
 832         };
 833
 834         gic: interrupt-controller@ff811000 {
 835                 compatible = "arm,gic-400";
 836                 #interrupt-cells = <3>;
 837                 #address-cells = <0>;
 838                 interrupt-controller;
 839                 reg = <0x0 0xff811000 0 0x1000>,
 840                       <0x0 0xff812000 0 0x2000>,
 841                       <0x0 0xff814000 0 0x2000>,
 842                       <0x0 0xff816000 0 0x2000>;
 843                 interrupts = <GIC_PPI 9
 844                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 845         };
 846
 847         pinctrl: pinctrl {
 848                 compatible = "rockchip,rk3328-pinctrl";
 849                 rockchip,grf = <&grf>;
 850                 #address-cells = <2>;
 851                 #size-cells = <2>;
 852                 ranges;
 853
 854                 gpio0: gpio0@ff210000 {
 855                         compatible = "rockchip,gpio-bank";
 856                         reg = <0x0 0xff210000 0x0 0x100>;
 857                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 858                         clocks = <&cru PCLK_GPIO0>;
 859
 860                         gpio-controller;
 861                         #gpio-cells = <2>;
 862
 863                         interrupt-controller;
 864                         #interrupt-cells = <2>;
 865                 };
 866
 867                 gpio1: gpio1@ff220000 {
 868                         compatible = "rockchip,gpio-bank";
 869                         reg = <0x0 0xff220000 0x0 0x100>;
 870                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 871                         clocks = <&cru PCLK_GPIO1>;
 872
 873                         gpio-controller;
 874                         #gpio-cells = <2>;
 875
 876                         interrupt-controller;
 877                         #interrupt-cells = <2>;
 878                 };
 879
 880                 gpio2: gpio2@ff230000 {
 881                         compatible = "rockchip,gpio-bank";
 882                         reg = <0x0 0xff230000 0x0 0x100>;
 883                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 884                         clocks = <&cru PCLK_GPIO2>;
 885
 886                         gpio-controller;
 887                         #gpio-cells = <2>;
 888
 889                         interrupt-controller;
 890                         #interrupt-cells = <2>;
 891                 };
 892
 893                 gpio3: gpio3@ff240000 {
 894                         compatible = "rockchip,gpio-bank";
 895                         reg = <0x0 0xff240000 0x0 0x100>;
 896                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 897                         clocks = <&cru PCLK_GPIO3>;
 898
 899                         gpio-controller;
 900                         #gpio-cells = <2>;
 901
 902                         interrupt-controller;
 903                         #interrupt-cells = <2>;
 904                 };
 905
 906                 pcfg_pull_up: pcfg-pull-up {
 907                         bias-pull-up;
 908                 };
 909
 910                 pcfg_pull_down: pcfg-pull-down {
 911                         bias-pull-down;
 912                 };
 913
 914                 pcfg_pull_none: pcfg-pull-none {
 915                         bias-disable;
 916                 };
 917
 918                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 919                         bias-disable;
 920                         drive-strength = <2>;
 921                 };
 922
 923                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 924                         bias-pull-up;
 925                         drive-strength = <2>;
 926                 };
 927
 928                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 929                         bias-pull-up;
 930                         drive-strength = <4>;
 931                 };
 932
 933                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 934                         bias-disable;
 935                         drive-strength = <4>;
 936                 };
 937
 938                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 939                         bias-pull-down;
 940                         drive-strength = <4>;
 941                 };
 942
 943                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 944                         bias-disable;
 945                         drive-strength = <8>;
 946                 };
 947
 948                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 949                         bias-pull-up;
 950                         drive-strength = <8>;
 951                 };
 952
 953                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 954                         bias-disable;
 955                         drive-strength = <12>;
 956                 };
 957
 958                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 959                         bias-pull-up;
 960                         drive-strength = <12>;
 961                 };
 962
 963                 pcfg_output_high: pcfg-output-high {
 964                         output-high;
 965                 };
 966
 967                 pcfg_output_low: pcfg-output-low {
 968                         output-low;
 969                 };
 970
 971                 pcfg_input_high: pcfg-input-high {
 972                         bias-pull-up;
 973                         input-enable;
 974                 };
 975
 976                 pcfg_input: pcfg-input {
 977                         input-enable;
 978                 };
 979
 980                 i2c0 {
 981                         i2c0_xfer: i2c0-xfer {
 982                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
 983                                                 <2 RK_PD1 1 &pcfg_pull_none>;
 984                         };
 985                 };
 986
 987                 i2c1 {
 988                         i2c1_xfer: i2c1-xfer {
 989                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
 990                                                 <2 RK_PA5 2 &pcfg_pull_none>;
 991                         };
 992                 };
 993
 994                 i2c2 {
 995                         i2c2_xfer: i2c2-xfer {
 996                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
 997                                                 <2 RK_PB6 1 &pcfg_pull_none>;
 998                         };
 999                 };
1000
1001                 i2c3 {
1002                         i2c3_xfer: i2c3-xfer {
1003                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1004                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1005                         };
1006                         i2c3_gpio: i2c3-gpio {
1007                                 rockchip,pins =
1008                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1009                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1010                         };
1011                 };
1012
1013                 hdmi_i2c {
1014                         hdmii2c_xfer: hdmii2c-xfer {
1015                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1016                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1017                         };
1018                 };
1019
1020                 pdm-0 {
1021                         pdmm0_clk: pdmm0-clk {
1022                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1023                         };
1024
1025                         pdmm0_fsync: pdmm0-fsync {
1026                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1027                         };
1028
1029                         pdmm0_sdi0: pdmm0-sdi0 {
1030                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1031                         };
1032
1033                         pdmm0_sdi1: pdmm0-sdi1 {
1034                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1035                         };
1036
1037                         pdmm0_sdi2: pdmm0-sdi2 {
1038                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1039                         };
1040
1041                         pdmm0_sdi3: pdmm0-sdi3 {
1042                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1043                         };
1044
1045                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1046                                 rockchip,pins =
1047                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1048                         };
1049
1050                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1051                                 rockchip,pins =
1052                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1053                         };
1054
1055                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1056                                 rockchip,pins =
1057                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1058                         };
1059
1060                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1061                                 rockchip,pins =
1062                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1063                         };
1064
1065                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1066                                 rockchip,pins =
1067                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1068                         };
1069
1070                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1071                                 rockchip,pins =
1072                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1073                         };
1074                 };
1075
1076                 tsadc {
1077                         otp_gpio: otp-gpio {
1078                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1079                         };
1080
1081                         otp_out: otp-out {
1082                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1083                         };
1084                 };
1085
1086                 uart0 {
1087                         uart0_xfer: uart0-xfer {
1088                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1089                                                 <1 RK_PB0 1 &pcfg_pull_up>;
1090                         };
1091
1092                         uart0_cts: uart0-cts {
1093                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1094                         };
1095
1096                         uart0_rts: uart0-rts {
1097                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1098                         };
1099
1100                         uart0_rts_gpio: uart0-rts-gpio {
1101                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1102                         };
1103                 };
1104
1105                 uart1 {
1106                         uart1_xfer: uart1-xfer {
1107                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1108                                                 <3 RK_PA6 4 &pcfg_pull_up>;
1109                         };
1110
1111                         uart1_cts: uart1-cts {
1112                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1113                         };
1114
1115                         uart1_rts: uart1-rts {
1116                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1117                         };
1118
1119                         uart1_rts_gpio: uart1-rts-gpio {
1120                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1121                         };
1122                 };
1123
1124                 uart2-0 {
1125                         uart2m0_xfer: uart2m0-xfer {
1126                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1127                                                 <1 RK_PA1 2 &pcfg_pull_up>;
1128                         };
1129                 };
1130
1131                 uart2-1 {
1132                         uart2m1_xfer: uart2m1-xfer {
1133                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1134                                                 <2 RK_PA1 1 &pcfg_pull_up>;
1135                         };
1136                 };
1137
1138                 spi0-0 {
1139                         spi0m0_clk: spi0m0-clk {
1140                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1141                         };
1142
1143                         spi0m0_cs0: spi0m0-cs0 {
1144                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1145                         };
1146
1147                         spi0m0_tx: spi0m0-tx {
1148                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1149                         };
1150
1151                         spi0m0_rx: spi0m0-rx {
1152                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1153                         };
1154
1155                         spi0m0_cs1: spi0m0-cs1 {
1156                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1157                         };
1158                 };
1159
1160                 spi0-1 {
1161                         spi0m1_clk: spi0m1-clk {
1162                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1163                         };
1164
1165                         spi0m1_cs0: spi0m1-cs0 {
1166                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1167                         };
1168
1169                         spi0m1_tx: spi0m1-tx {
1170                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1171                         };
1172
1173                         spi0m1_rx: spi0m1-rx {
1174                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1175                         };
1176
1177                         spi0m1_cs1: spi0m1-cs1 {
1178                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1179                         };
1180                 };
1181
1182                 spi0-2 {
1183                         spi0m2_clk: spi0m2-clk {
1184                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1185                         };
1186
1187                         spi0m2_cs0: spi0m2-cs0 {
1188                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1189                         };
1190
1191                         spi0m2_tx: spi0m2-tx {
1192                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1193                         };
1194
1195                         spi0m2_rx: spi0m2-rx {
1196                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1197                         };
1198                 };
1199
1200                 i2s1 {
1201                         i2s1_mclk: i2s1-mclk {
1202                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1203                         };
1204
1205                         i2s1_sclk: i2s1-sclk {
1206                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1207                         };
1208
1209                         i2s1_lrckrx: i2s1-lrckrx {
1210                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1211                         };
1212
1213                         i2s1_lrcktx: i2s1-lrcktx {
1214                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1215                         };
1216
1217                         i2s1_sdi: i2s1-sdi {
1218                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1219                         };
1220
1221                         i2s1_sdo: i2s1-sdo {
1222                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1223                         };
1224
1225                         i2s1_sdio1: i2s1-sdio1 {
1226                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1227                         };
1228
1229                         i2s1_sdio2: i2s1-sdio2 {
1230                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1231                         };
1232
1233                         i2s1_sdio3: i2s1-sdio3 {
1234                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1235                         };
1236
1237                         i2s1_sleep: i2s1-sleep {
1238                                 rockchip,pins =
1239                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1240                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1241                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1242                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1243                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1244                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1245                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1246                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1247                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1248                         };
1249                 };
1250
1251                 i2s2-0 {
1252                         i2s2m0_mclk: i2s2m0-mclk {
1253                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1254                         };
1255
1256                         i2s2m0_sclk: i2s2m0-sclk {
1257                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1258                         };
1259
1260                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1261                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1262                         };
1263
1264                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1265                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1266                         };
1267
1268                         i2s2m0_sdi: i2s2m0-sdi {
1269                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1270                         };
1271
1272                         i2s2m0_sdo: i2s2m0-sdo {
1273                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1274                         };
1275
1276                         i2s2m0_sleep: i2s2m0-sleep {
1277                                 rockchip,pins =
1278                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1279                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1280                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1281                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1282                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1283                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1284                         };
1285                 };
1286
1287                 i2s2-1 {
1288                         i2s2m1_mclk: i2s2m1-mclk {
1289                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1290                         };
1291
1292                         i2s2m1_sclk: i2s2m1-sclk {
1293                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1294                         };
1295
1296                         i2s2m1_lrckrx: i2sm1-lrckrx {
1297                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1298                         };
1299
1300                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1301                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1302                         };
1303
1304                         i2s2m1_sdi: i2s2m1-sdi {
1305                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1306                         };
1307
1308                         i2s2m1_sdo: i2s2m1-sdo {
1309                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1310                         };
1311
1312                         i2s2m1_sleep: i2s2m1-sleep {
1313                                 rockchip,pins =
1314                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1315                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1316                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1317                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1318                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1319                         };
1320                 };
1321
1322                 spdif-0 {
1323                         spdifm0_tx: spdifm0-tx {
1324                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1325                         };
1326                 };
1327
1328                 spdif-1 {
1329                         spdifm1_tx: spdifm1-tx {
1330                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1331                         };
1332                 };
1333
1334                 spdif-2 {
1335                         spdifm2_tx: spdifm2-tx {
1336                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1337                         };
1338                 };
1339
1340                 sdmmc0-0 {
1341                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1342                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1343                         };
1344
1345                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1346                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1347                         };
1348                 };
1349
1350                 sdmmc0-1 {
1351                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1352                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1353                         };
1354
1355                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1356                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1357                         };
1358                 };
1359
1360                 sdmmc0 {
1361                         sdmmc0_clk: sdmmc0-clk {
1362                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1363                         };
1364
1365                         sdmmc0_cmd: sdmmc0-cmd {
1366                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1367                         };
1368
1369                         sdmmc0_dectn: sdmmc0-dectn {
1370                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1371                         };
1372
1373                         sdmmc0_wrprt: sdmmc0-wrprt {
1374                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1375                         };
1376
1377                         sdmmc0_bus1: sdmmc0-bus1 {
1378                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1379                         };
1380
1381                         sdmmc0_bus4: sdmmc0-bus4 {
1382                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1383                                                 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1384                                                 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1385                                                 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1386                         };
1387
1388                         sdmmc0_gpio: sdmmc0-gpio {
1389                                 rockchip,pins =
1390                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1391                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1392                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1393                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1394                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1395                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1396                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1397                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1398                         };
1399                 };
1400
1401                 sdmmc0ext {
1402                         sdmmc0ext_clk: sdmmc0ext-clk {
1403                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1404                         };
1405
1406                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1407                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1408                         };
1409
1410                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1411                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1412                         };
1413
1414                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1415                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1416                         };
1417
1418                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1419                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1420                         };
1421
1422                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1423                                 rockchip,pins =
1424                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1425                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1426                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1427                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1428                         };
1429
1430                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1431                                 rockchip,pins =
1432                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1433                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1434                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1435                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1436                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1437                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1438                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1439                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1440                         };
1441                 };
1442
1443                 sdmmc1 {
1444                         sdmmc1_clk: sdmmc1-clk {
1445                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1446                         };
1447
1448                         sdmmc1_cmd: sdmmc1-cmd {
1449                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1450                         };
1451
1452                         sdmmc1_pwren: sdmmc1-pwren {
1453                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1454                         };
1455
1456                         sdmmc1_wrprt: sdmmc1-wrprt {
1457                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1458                         };
1459
1460                         sdmmc1_dectn: sdmmc1-dectn {
1461                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1462                         };
1463
1464                         sdmmc1_bus1: sdmmc1-bus1 {
1465                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1466                         };
1467
1468                         sdmmc1_bus4: sdmmc1-bus4 {
1469                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1470                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1471                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1472                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1473                         };
1474
1475                         sdmmc1_gpio: sdmmc1-gpio {
1476                                 rockchip,pins =
1477                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1478                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1479                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1480                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1481                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1482                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1483                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1484                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1485                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1486                         };
1487                 };
1488
1489                 emmc {
1490                         emmc_clk: emmc-clk {
1491                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1492                         };
1493
1494                         emmc_cmd: emmc-cmd {
1495                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1496                         };
1497
1498                         emmc_pwren: emmc-pwren {
1499                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1500                         };
1501
1502                         emmc_rstnout: emmc-rstnout {
1503                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1504                         };
1505
1506                         emmc_bus1: emmc-bus1 {
1507                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1508                         };
1509
1510                         emmc_bus4: emmc-bus4 {
1511                                 rockchip,pins =
1512                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1513                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1514                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1515                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1516                         };
1517
1518                         emmc_bus8: emmc-bus8 {
1519                                 rockchip,pins =
1520                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1521                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1522                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1523                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1524                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1525                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1526                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1527                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1528                         };
1529                 };
1530
1531                 pwm0 {
1532                         pwm0_pin: pwm0-pin {
1533                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1534                         };
1535                 };
1536
1537                 pwm1 {
1538                         pwm1_pin: pwm1-pin {
1539                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1540                         };
1541                 };
1542
1543                 pwm2 {
1544                         pwm2_pin: pwm2-pin {
1545                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1546                         };
1547                 };
1548
1549                 pwmir {
1550                         pwmir_pin: pwmir-pin {
1551                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1552                         };
1553                 };
1554
1555                 gmac-1 {
1556                         rgmiim1_pins: rgmiim1-pins {
1557                                 rockchip,pins =
1558                                         /* mac_txclk */
1559                                         <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1560                                         /* mac_rxclk */
1561                                         <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1562                                         /* mac_mdio */
1563                                         <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1564                                         /* mac_txen */
1565                                         <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1566                                         /* mac_clk */
1567                                         <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1568                                         /* mac_rxdv */
1569                                         <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1570                                         /* mac_mdc */
1571                                         <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1572                                         /* mac_rxd1 */
1573                                         <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1574                                         /* mac_rxd0 */
1575                                         <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1576                                         /* mac_txd1 */
1577                                         <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1578                                         /* mac_txd0 */
1579                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1580                                         /* mac_rxd3 */
1581                                         <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1582                                         /* mac_rxd2 */
1583                                         <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1584                                         /* mac_txd3 */
1585                                         <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1586                                         /* mac_txd2 */
1587                                         <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1588
1589                                         /* mac_txclk */
1590                                         <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1591                                         /* mac_txen */
1592                                         <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1593                                         /* mac_clk */
1594                                         <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1595                                         /* mac_txd1 */
1596                                         <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1597                                         /* mac_txd0 */
1598                                         <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1599                                         /* mac_txd3 */
1600                                         <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1601                                         /* mac_txd2 */
1602                                         <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1603                         };
1604
1605                         rmiim1_pins: rmiim1-pins {
1606                                 rockchip,pins =
1607                                         /* mac_mdio */
1608                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1609                                         /* mac_txen */
1610                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1611                                         /* mac_clk */
1612                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1613                                         /* mac_rxer */
1614                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1615                                         /* mac_rxdv */
1616                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1617                                         /* mac_mdc */
1618                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1619                                         /* mac_rxd1 */
1620                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1621                                         /* mac_rxd0 */
1622                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1623                                         /* mac_txd1 */
1624                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1625                                         /* mac_txd0 */
1626                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1627
1628                                         /* mac_mdio */
1629                                         <0 RK_PB3 1 &pcfg_pull_none>,
1630                                         /* mac_txen */
1631                                         <0 RK_PB4 1 &pcfg_pull_none>,
1632                                         /* mac_clk */
1633                                         <0 RK_PD0 1 &pcfg_pull_none>,
1634                                         /* mac_mdc */
1635                                         <0 RK_PC3 1 &pcfg_pull_none>,
1636                                         /* mac_txd1 */
1637                                         <0 RK_PC0 1 &pcfg_pull_none>,
1638                                         /* mac_txd0 */
1639                                         <0 RK_PC1 1 &pcfg_pull_none>;
1640                         };
1641                 };
1642
1643                 gmac2phy {
1644                         fephyled_speed100: fephyled-speed100 {
1645                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1646                         };
1647
1648                         fephyled_speed10: fephyled-speed10 {
1649                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1650                         };
1651
1652                         fephyled_duplex: fephyled-duplex {
1653                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1654                         };
1655
1656                         fephyled_rxm0: fephyled-rxm0 {
1657                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1658                         };
1659
1660                         fephyled_txm0: fephyled-txm0 {
1661                                 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1662                         };
1663
1664                         fephyled_linkm0: fephyled-linkm0 {
1665                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1666                         };
1667
1668                         fephyled_rxm1: fephyled-rxm1 {
1669                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1670                         };
1671
1672                         fephyled_txm1: fephyled-txm1 {
1673                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1674                         };
1675
1676                         fephyled_linkm1: fephyled-linkm1 {
1677                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1678                         };
1679                 };
1680
1681                 tsadc_pin {
1682                         tsadc_int: tsadc-int {
1683                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1684                         };
1685                         tsadc_gpio: tsadc-gpio {
1686                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1687                         };
1688                 };
1689
1690                 hdmi_pin {
1691                         hdmi_cec: hdmi-cec {
1692                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1693                         };
1694
1695                         hdmi_hpd: hdmi-hpd {
1696                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1697                         };
1698                 };
1699
1700                 cif-0 {
1701                         dvp_d2d9_m0:dvp-d2d9-m0 {
1702                                 rockchip,pins =
1703                                         /* cif_d0 */
1704                                         <3 RK_PA4 2 &pcfg_pull_none>,
1705                                         /* cif_d1 */
1706                                         <3 RK_PA5 2 &pcfg_pull_none>,
1707                                         /* cif_d2 */
1708                                         <3 RK_PA6 2 &pcfg_pull_none>,
1709                                         /* cif_d3 */
1710                                         <3 RK_PA7 2 &pcfg_pull_none>,
1711                                         /* cif_d4 */
1712                                         <3 RK_PB0 2 &pcfg_pull_none>,
1713                                         /* cif_d5m0 */
1714                                         <3 RK_PB1 2 &pcfg_pull_none>,
1715                                         /* cif_d6m0 */
1716                                         <3 RK_PB2 2 &pcfg_pull_none>,
1717                                         /* cif_d7m0 */
1718                                         <3 RK_PB3 2 &pcfg_pull_none>,
1719                                         /* cif_href */
1720                                         <3 RK_PA1 2 &pcfg_pull_none>,
1721                                         /* cif_vsync */
1722                                         <3 RK_PA0 2 &pcfg_pull_none>,
1723                                         /* cif_clkoutm0 */
1724                                         <3 RK_PA3 2 &pcfg_pull_none>,
1725                                         /* cif_clkin */
1726                                         <3 RK_PA2 2 &pcfg_pull_none>;
1727                         };
1728                 };
1729
1730                 cif-1 {
1731                         dvp_d2d9_m1:dvp-d2d9-m1 {
1732                                 rockchip,pins =
1733                                         /* cif_d0 */
1734                                         <3 RK_PA4 2 &pcfg_pull_none>,
1735                                         /* cif_d1 */
1736                                         <3 RK_PA5 2 &pcfg_pull_none>,
1737                                         /* cif_d2 */
1738                                         <3 RK_PA6 2 &pcfg_pull_none>,
1739                                         /* cif_d3 */
1740                                         <3 RK_PA7 2 &pcfg_pull_none>,
1741                                         /* cif_d4 */
1742                                         <3 RK_PB0 2 &pcfg_pull_none>,
1743                                         /* cif_d5m1 */
1744                                         <2 RK_PC0 4 &pcfg_pull_none>,
1745                                         /* cif_d6m1 */
1746                                         <2 RK_PC1 4 &pcfg_pull_none>,
1747                                         /* cif_d7m1 */
1748                                         <2 RK_PC2 4 &pcfg_pull_none>,
1749                                         /* cif_href */
1750                                         <3 RK_PA1 2 &pcfg_pull_none>,
1751                                         /* cif_vsync */
1752                                         <3 RK_PA0 2 &pcfg_pull_none>,
1753                                         /* cif_clkoutm1 */
1754                                         <2 RK_PB7 4 &pcfg_pull_none>,
1755                                         /* cif_clkin */
1756                                         <3 RK_PA2 2 &pcfg_pull_none>;
1757                         };
1758                 };
1759         };
1760 };