arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 mmc0 = &sdio0;
  33                 mmc1 = &sdmmc;
  34                 mmc2 = &sdhci;
  35                 serial0 = &uart0;
  36                 serial1 = &uart1;
  37                 serial2 = &uart2;
  38                 serial3 = &uart3;
  39                 serial4 = &uart4;
  40         };
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 cpu-map {
  47                         cluster0 {
  48                                 core0 {
  49                                         cpu = <&cpu_l0>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&cpu_l1>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&cpu_l2>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&cpu_l3>;
  59                                 };
  60                         };
  61
  62                         cluster1 {
  63                                 core0 {
  64                                         cpu = <&cpu_b0>;
  65                                 };
  66                                 core1 {
  67                                         cpu = <&cpu_b1>;
  68                                 };
  69                         };
  70                 };
  71
  72                 cpu_l0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77                         clocks = <&cru ARMCLKL>;
  78                         #cooling-cells = <2>; /* min followed by max */
  79                         dynamic-power-coefficient = <100>;
  80                 };
  81
  82                 cpu_l1: cpu@1 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         reg = <0x0 0x1>;
  86                         enable-method = "psci";
  87                         clocks = <&cru ARMCLKL>;
  88                         #cooling-cells = <2>; /* min followed by max */
  89                         dynamic-power-coefficient = <100>;
  90                 };
  91
  92                 cpu_l2: cpu@2 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         reg = <0x0 0x2>;
  96                         enable-method = "psci";
  97                         clocks = <&cru ARMCLKL>;
  98                         #cooling-cells = <2>; /* min followed by max */
  99                         dynamic-power-coefficient = <100>;
 100                 };
 101
 102                 cpu_l3: cpu@3 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a53", "arm,armv8";
 105                         reg = <0x0 0x3>;
 106                         enable-method = "psci";
 107                         clocks = <&cru ARMCLKL>;
 108                         #cooling-cells = <2>; /* min followed by max */
 109                         dynamic-power-coefficient = <100>;
 110                 };
 111
 112                 cpu_b0: cpu@100 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a72", "arm,armv8";
 115                         reg = <0x0 0x100>;
 116                         enable-method = "psci";
 117                         clocks = <&cru ARMCLKB>;
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <436>;
 120                 };
 121
 122                 cpu_b1: cpu@101 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a72", "arm,armv8";
 125                         reg = <0x0 0x101>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKB>;
 128                         #cooling-cells = <2>; /* min followed by max */
 129                         dynamic-power-coefficient = <436>;
 130                 };
 131         };
 132
 133         display-subsystem {
 134                 compatible = "rockchip,display-subsystem";
 135                 ports = <&vopl_out>, <&vopb_out>;
 136         };
 137
 138         pmu_a53 {
 139                 compatible = "arm,cortex-a53-pmu";
 140                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 141         };
 142
 143         pmu_a72 {
 144                 compatible = "arm,cortex-a72-pmu";
 145                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 146         };
 147
 148         psci {
 149                 compatible = "arm,psci-1.0";
 150                 method = "smc";
 151         };
 152
 153         timer {
 154                 compatible = "arm,armv8-timer";
 155                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 156                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 157                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 158                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 159                 arm,no-tick-in-suspend;
 160         };
 161
 162         xin24m: xin24m {
 163                 compatible = "fixed-clock";
 164                 clock-frequency = <24000000>;
 165                 clock-output-names = "xin24m";
 166                 #clock-cells = <0>;
 167         };
 168
 169         amba {
 170                 compatible = "simple-bus";
 171                 #address-cells = <2>;
 172                 #size-cells = <2>;
 173                 ranges;
 174
 175                 dmac_bus: dma-controller@ff6d0000 {
 176                         compatible = "arm,pl330", "arm,primecell";
 177                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 178                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 179                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 180                         #dma-cells = <1>;
 181                         clocks = <&cru ACLK_DMAC0_PERILP>;
 182                         clock-names = "apb_pclk";
 183                 };
 184
 185                 dmac_peri: dma-controller@ff6e0000 {
 186                         compatible = "arm,pl330", "arm,primecell";
 187                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 188                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 189                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 190                         #dma-cells = <1>;
 191                         clocks = <&cru ACLK_DMAC1_PERILP>;
 192                         clock-names = "apb_pclk";
 193                 };
 194         };
 195
 196         pcie0: pcie@f8000000 {
 197                 compatible = "rockchip,rk3399-pcie";
 198                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 199                       <0x0 0xfd000000 0x0 0x1000000>;
 200                 reg-names = "axi-base", "apb-base";
 201                 device_type = "pci";
 202                 #address-cells = <3>;
 203                 #size-cells = <2>;
 204                 #interrupt-cells = <1>;
 205                 aspm-no-l0s;
 206                 bus-range = <0x0 0x1f>;
 207                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 208                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 209                 clock-names = "aclk", "aclk-perf",
 210                               "hclk", "pm";
 211                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 212                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 213                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 214                 interrupt-names = "sys", "legacy", "client";
 215                 interrupt-map-mask = <0 0 0 7>;
 216                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 217                                 <0 0 0 2 &pcie0_intc 1>,
 218                                 <0 0 0 3 &pcie0_intc 2>,
 219                                 <0 0 0 4 &pcie0_intc 3>;
 220                 max-link-speed = <1>;
 221                 msi-map = <0x0 &its 0x0 0x1000>;
 222                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 223                        <&pcie_phy 2>, <&pcie_phy 3>;
 224                 phy-names = "pcie-phy-0", "pcie-phy-1",
 225                             "pcie-phy-2", "pcie-phy-3";
 226                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
 227                           0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 228                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 229                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 230                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 231                          <&cru SRST_A_PCIE>;
 232                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 233                               "pm", "pclk", "aclk";
 234                 status = "disabled";
 235
 236                 pcie0_intc: interrupt-controller {
 237                         interrupt-controller;
 238                         #address-cells = <0>;
 239                         #interrupt-cells = <1>;
 240                 };
 241         };
 242
 243         gmac: ethernet@fe300000 {
 244                 compatible = "rockchip,rk3399-gmac";
 245                 reg = <0x0 0xfe300000 0x0 0x10000>;
 246                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 247                 interrupt-names = "macirq";
 248                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 249                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 250                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 251                          <&cru PCLK_GMAC>;
 252                 clock-names = "stmmaceth", "mac_clk_rx",
 253                               "mac_clk_tx", "clk_mac_ref",
 254                               "clk_mac_refout", "aclk_mac",
 255                               "pclk_mac";
 256                 power-domains = <&power RK3399_PD_GMAC>;
 257                 resets = <&cru SRST_A_GMAC>;
 258                 reset-names = "stmmaceth";
 259                 rockchip,grf = <&grf>;
 260                 status = "disabled";
 261         };
 262
 263         sdio0: dwmmc@fe310000 {
 264                 compatible = "rockchip,rk3399-dw-mshc",
 265                              "rockchip,rk3288-dw-mshc";
 266                 reg = <0x0 0xfe310000 0x0 0x4000>;
 267                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 268                 max-frequency = <150000000>;
 269                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 270                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 271                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 272                 fifo-depth = <0x100>;
 273                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 274                 resets = <&cru SRST_SDIO0>;
 275                 reset-names = "reset";
 276                 status = "disabled";
 277         };
 278
 279         sdmmc: dwmmc@fe320000 {
 280                 compatible = "rockchip,rk3399-dw-mshc",
 281                              "rockchip,rk3288-dw-mshc";
 282                 reg = <0x0 0xfe320000 0x0 0x4000>;
 283                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 284                 max-frequency = <150000000>;
 285                 assigned-clocks = <&cru HCLK_SD>;
 286                 assigned-clock-rates = <200000000>;
 287                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 288                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 289                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 290                 fifo-depth = <0x100>;
 291                 power-domains = <&power RK3399_PD_SD>;
 292                 resets = <&cru SRST_SDMMC>;
 293                 reset-names = "reset";
 294                 status = "disabled";
 295         };
 296
 297         sdhci: sdhci@fe330000 {
 298                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 299                 reg = <0x0 0xfe330000 0x0 0x10000>;
 300                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 301                 arasan,soc-ctl-syscon = <&grf>;
 302                 assigned-clocks = <&cru SCLK_EMMC>;
 303                 assigned-clock-rates = <200000000>;
 304                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 305                 clock-names = "clk_xin", "clk_ahb";
 306                 clock-output-names = "emmc_cardclock";
 307                 #clock-cells = <0>;
 308                 phys = <&emmc_phy>;
 309                 phy-names = "phy_arasan";
 310                 power-domains = <&power RK3399_PD_EMMC>;
 311                 disable-cqe-dcmd;
 312                 status = "disabled";
 313         };
 314
 315         usb_host0_ehci: usb@fe380000 {
 316                 compatible = "generic-ehci";
 317                 reg = <0x0 0xfe380000 0x0 0x20000>;
 318                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 319                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 320                          <&u2phy0>;
 321                 clock-names = "usbhost", "arbiter",
 322                               "utmi";
 323                 phys = <&u2phy0_host>;
 324                 phy-names = "usb";
 325                 status = "disabled";
 326         };
 327
 328         usb_host0_ohci: usb@fe3a0000 {
 329                 compatible = "generic-ohci";
 330                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 331                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 332                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 333                          <&u2phy0>;
 334                 clock-names = "usbhost", "arbiter",
 335                               "utmi";
 336                 phys = <&u2phy0_host>;
 337                 phy-names = "usb";
 338                 status = "disabled";
 339         };
 340
 341         usb_host1_ehci: usb@fe3c0000 {
 342                 compatible = "generic-ehci";
 343                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 344                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 345                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 346                          <&u2phy1>;
 347                 clock-names = "usbhost", "arbiter",
 348                               "utmi";
 349                 phys = <&u2phy1_host>;
 350                 phy-names = "usb";
 351                 status = "disabled";
 352         };
 353
 354         usb_host1_ohci: usb@fe3e0000 {
 355                 compatible = "generic-ohci";
 356                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 357                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 358                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 359                          <&u2phy1>;
 360                 clock-names = "usbhost", "arbiter",
 361                               "utmi";
 362                 phys = <&u2phy1_host>;
 363                 phy-names = "usb";
 364                 status = "disabled";
 365         };
 366
 367         usbdrd3_0: usb@fe800000 {
 368                 compatible = "rockchip,rk3399-dwc3";
 369                 #address-cells = <2>;
 370                 #size-cells = <2>;
 371                 ranges;
 372                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 373                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 374                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 375                 clock-names = "ref_clk", "suspend_clk",
 376                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 377                               "aclk_usb3", "grf_clk";
 378                 resets = <&cru SRST_A_USB3_OTG0>;
 379                 reset-names = "usb3-otg";
 380                 status = "disabled";
 381
 382                 usbdrd_dwc3_0: usb@fe800000 {
 383                         compatible = "snps,dwc3";
 384                         reg = <0x0 0xfe800000 0x0 0x100000>;
 385                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 386                         dr_mode = "otg";
 387                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 388                         phy-names = "usb2-phy", "usb3-phy";
 389                         phy_type = "utmi_wide";
 390                         snps,dis_enblslpm_quirk;
 391                         snps,dis-u2-freeclk-exists-quirk;
 392                         snps,dis_u2_susphy_quirk;
 393                         snps,dis-del-phy-power-chg-quirk;
 394                         snps,dis-tx-ipgap-linecheck-quirk;
 395                         power-domains = <&power RK3399_PD_USB3>;
 396                         status = "disabled";
 397                 };
 398         };
 399
 400         usbdrd3_1: usb@fe900000 {
 401                 compatible = "rockchip,rk3399-dwc3";
 402                 #address-cells = <2>;
 403                 #size-cells = <2>;
 404                 ranges;
 405                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 406                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 407                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 408                 clock-names = "ref_clk", "suspend_clk",
 409                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 410                               "aclk_usb3", "grf_clk";
 411                 resets = <&cru SRST_A_USB3_OTG1>;
 412                 reset-names = "usb3-otg";
 413                 status = "disabled";
 414
 415                 usbdrd_dwc3_1: usb@fe900000 {
 416                         compatible = "snps,dwc3";
 417                         reg = <0x0 0xfe900000 0x0 0x100000>;
 418                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 419                         dr_mode = "otg";
 420                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 421                         phy-names = "usb2-phy", "usb3-phy";
 422                         phy_type = "utmi_wide";
 423                         snps,dis_enblslpm_quirk;
 424                         snps,dis-u2-freeclk-exists-quirk;
 425                         snps,dis_u2_susphy_quirk;
 426                         snps,dis-del-phy-power-chg-quirk;
 427                         snps,dis-tx-ipgap-linecheck-quirk;
 428                         power-domains = <&power RK3399_PD_USB3>;
 429                         status = "disabled";
 430                 };
 431         };
 432
 433         cdn_dp: dp@fec00000 {
 434                 compatible = "rockchip,rk3399-cdn-dp";
 435                 reg = <0x0 0xfec00000 0x0 0x100000>;
 436                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 437                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
 438                 assigned-clock-rates = <100000000>, <200000000>;
 439                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 440                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 441                 clock-names = "core-clk", "pclk", "spdif", "grf";
 442                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 443                 power-domains = <&power RK3399_PD_HDCP>;
 444                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 445                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 446                 reset-names = "spdif", "dptx", "apb", "core";
 447                 rockchip,grf = <&grf>;
 448                 #sound-dai-cells = <1>;
 449                 status = "disabled";
 450
 451                 ports {
 452                         dp_in: port {
 453                                 #address-cells = <1>;
 454                                 #size-cells = <0>;
 455
 456                                 dp_in_vopb: endpoint@0 {
 457                                         reg = <0>;
 458                                         remote-endpoint = <&vopb_out_dp>;
 459                                 };
 460
 461                                 dp_in_vopl: endpoint@1 {
 462                                         reg = <1>;
 463                                         remote-endpoint = <&vopl_out_dp>;
 464                                 };
 465                         };
 466                 };
 467         };
 468
 469         gic: interrupt-controller@fee00000 {
 470                 compatible = "arm,gic-v3";
 471                 #interrupt-cells = <4>;
 472                 #address-cells = <2>;
 473                 #size-cells = <2>;
 474                 ranges;
 475                 interrupt-controller;
 476
 477                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 478                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 479                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 480                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 481                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 482                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 483                 its: interrupt-controller@fee20000 {
 484                         compatible = "arm,gic-v3-its";
 485                         msi-controller;
 486                         reg = <0x0 0xfee20000 0x0 0x20000>;
 487                 };
 488
 489                 ppi-partitions {
 490                         ppi_cluster0: interrupt-partition-0 {
 491                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 492                         };
 493
 494                         ppi_cluster1: interrupt-partition-1 {
 495                                 affinity = <&cpu_b0 &cpu_b1>;
 496                         };
 497                 };
 498         };
 499
 500         saradc: saradc@ff100000 {
 501                 compatible = "rockchip,rk3399-saradc";
 502                 reg = <0x0 0xff100000 0x0 0x100>;
 503                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 504                 #io-channel-cells = <1>;
 505                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 506                 clock-names = "saradc", "apb_pclk";
 507                 resets = <&cru SRST_P_SARADC>;
 508                 reset-names = "saradc-apb";
 509                 status = "disabled";
 510         };
 511
 512         i2c1: i2c@ff110000 {
 513                 compatible = "rockchip,rk3399-i2c";
 514                 reg = <0x0 0xff110000 0x0 0x1000>;
 515                 assigned-clocks = <&cru SCLK_I2C1>;
 516                 assigned-clock-rates = <200000000>;
 517                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 518                 clock-names = "i2c", "pclk";
 519                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c1_xfer>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 status = "disabled";
 525         };
 526
 527         i2c2: i2c@ff120000 {
 528                 compatible = "rockchip,rk3399-i2c";
 529                 reg = <0x0 0xff120000 0x0 0x1000>;
 530                 assigned-clocks = <&cru SCLK_I2C2>;
 531                 assigned-clock-rates = <200000000>;
 532                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 533                 clock-names = "i2c", "pclk";
 534                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&i2c2_xfer>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         i2c3: i2c@ff130000 {
 543                 compatible = "rockchip,rk3399-i2c";
 544                 reg = <0x0 0xff130000 0x0 0x1000>;
 545                 assigned-clocks = <&cru SCLK_I2C3>;
 546                 assigned-clock-rates = <200000000>;
 547                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 548                 clock-names = "i2c", "pclk";
 549                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c3_xfer>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         i2c5: i2c@ff140000 {
 558                 compatible = "rockchip,rk3399-i2c";
 559                 reg = <0x0 0xff140000 0x0 0x1000>;
 560                 assigned-clocks = <&cru SCLK_I2C5>;
 561                 assigned-clock-rates = <200000000>;
 562                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 563                 clock-names = "i2c", "pclk";
 564                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&i2c5_xfer>;
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 status = "disabled";
 570         };
 571
 572         i2c6: i2c@ff150000 {
 573                 compatible = "rockchip,rk3399-i2c";
 574                 reg = <0x0 0xff150000 0x0 0x1000>;
 575                 assigned-clocks = <&cru SCLK_I2C6>;
 576                 assigned-clock-rates = <200000000>;
 577                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 578                 clock-names = "i2c", "pclk";
 579                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&i2c6_xfer>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 status = "disabled";
 585         };
 586
 587         i2c7: i2c@ff160000 {
 588                 compatible = "rockchip,rk3399-i2c";
 589                 reg = <0x0 0xff160000 0x0 0x1000>;
 590                 assigned-clocks = <&cru SCLK_I2C7>;
 591                 assigned-clock-rates = <200000000>;
 592                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 593                 clock-names = "i2c", "pclk";
 594                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 595                 pinctrl-names = "default";
 596                 pinctrl-0 = <&i2c7_xfer>;
 597                 #address-cells = <1>;
 598                 #size-cells = <0>;
 599                 status = "disabled";
 600         };
 601
 602         uart0: serial@ff180000 {
 603                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 604                 reg = <0x0 0xff180000 0x0 0x100>;
 605                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 606                 clock-names = "baudclk", "apb_pclk";
 607                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 608                 reg-shift = <2>;
 609                 reg-io-width = <4>;
 610                 pinctrl-names = "default";
 611                 pinctrl-0 = <&uart0_xfer>;
 612                 status = "disabled";
 613         };
 614
 615         uart1: serial@ff190000 {
 616                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 617                 reg = <0x0 0xff190000 0x0 0x100>;
 618                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 619                 clock-names = "baudclk", "apb_pclk";
 620                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 621                 reg-shift = <2>;
 622                 reg-io-width = <4>;
 623                 pinctrl-names = "default";
 624                 pinctrl-0 = <&uart1_xfer>;
 625                 status = "disabled";
 626         };
 627
 628         uart2: serial@ff1a0000 {
 629                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 630                 reg = <0x0 0xff1a0000 0x0 0x100>;
 631                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 632                 clock-names = "baudclk", "apb_pclk";
 633                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 634                 reg-shift = <2>;
 635                 reg-io-width = <4>;
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&uart2c_xfer>;
 638                 status = "disabled";
 639         };
 640
 641         uart3: serial@ff1b0000 {
 642                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 643                 reg = <0x0 0xff1b0000 0x0 0x100>;
 644                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 645                 clock-names = "baudclk", "apb_pclk";
 646                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 647                 reg-shift = <2>;
 648                 reg-io-width = <4>;
 649                 pinctrl-names = "default";
 650                 pinctrl-0 = <&uart3_xfer>;
 651                 status = "disabled";
 652         };
 653
 654         spi0: spi@ff1c0000 {
 655                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 656                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 657                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 658                 clock-names = "spiclk", "apb_pclk";
 659                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 660                 pinctrl-names = "default";
 661                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 status = "disabled";
 665         };
 666
 667         spi1: spi@ff1d0000 {
 668                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 669                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 670                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 671                 clock-names = "spiclk", "apb_pclk";
 672                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 673                 pinctrl-names = "default";
 674                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 675                 #address-cells = <1>;
 676                 #size-cells = <0>;
 677                 status = "disabled";
 678         };
 679
 680         spi2: spi@ff1e0000 {
 681                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 682                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 683                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 684                 clock-names = "spiclk", "apb_pclk";
 685                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 688                 #address-cells = <1>;
 689                 #size-cells = <0>;
 690                 status = "disabled";
 691         };
 692
 693         spi4: spi@ff1f0000 {
 694                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 695                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 696                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 697                 clock-names = "spiclk", "apb_pclk";
 698                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 699                 pinctrl-names = "default";
 700                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 status = "disabled";
 704         };
 705
 706         spi5: spi@ff200000 {
 707                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 708                 reg = <0x0 0xff200000 0x0 0x1000>;
 709                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 710                 clock-names = "spiclk", "apb_pclk";
 711                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 712                 pinctrl-names = "default";
 713                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 714                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 715                 #address-cells = <1>;
 716                 #size-cells = <0>;
 717                 status = "disabled";
 718         };
 719
 720         thermal_zones: thermal-zones {
 721                 cpu_thermal: cpu {
 722                         polling-delay-passive = <100>;
 723                         polling-delay = <1000>;
 724
 725                         thermal-sensors = <&tsadc 0>;
 726
 727                         trips {
 728                                 cpu_alert0: cpu_alert0 {
 729                                         temperature = <70000>;
 730                                         hysteresis = <2000>;
 731                                         type = "passive";
 732                                 };
 733                                 cpu_alert1: cpu_alert1 {
 734                                         temperature = <75000>;
 735                                         hysteresis = <2000>;
 736                                         type = "passive";
 737                                 };
 738                                 cpu_crit: cpu_crit {
 739                                         temperature = <95000>;
 740                                         hysteresis = <2000>;
 741                                         type = "critical";
 742                                 };
 743                         };
 744
 745                         cooling-maps {
 746                                 map0 {
 747                                         trip = <&cpu_alert0>;
 748                                         cooling-device =
 749                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 750                                 };
 751                                 map1 {
 752                                         trip = <&cpu_alert1>;
 753                                         cooling-device =
 754                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 755                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 756                                 };
 757                         };
 758                 };
 759
 760                 gpu_thermal: gpu {
 761                         polling-delay-passive = <100>;
 762                         polling-delay = <1000>;
 763
 764                         thermal-sensors = <&tsadc 1>;
 765
 766                         trips {
 767                                 gpu_alert0: gpu_alert0 {
 768                                         temperature = <75000>;
 769                                         hysteresis = <2000>;
 770                                         type = "passive";
 771                                 };
 772                                 gpu_crit: gpu_crit {
 773                                         temperature = <95000>;
 774                                         hysteresis = <2000>;
 775                                         type = "critical";
 776                                 };
 777                         };
 778
 779                         cooling-maps {
 780                                 map0 {
 781                                         trip = <&gpu_alert0>;
 782                                         cooling-device =
 783                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 784                                 };
 785                         };
 786                 };
 787         };
 788
 789         tsadc: tsadc@ff260000 {
 790                 compatible = "rockchip,rk3399-tsadc";
 791                 reg = <0x0 0xff260000 0x0 0x100>;
 792                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 793                 assigned-clocks = <&cru SCLK_TSADC>;
 794                 assigned-clock-rates = <750000>;
 795                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 796                 clock-names = "tsadc", "apb_pclk";
 797                 resets = <&cru SRST_TSADC>;
 798                 reset-names = "tsadc-apb";
 799                 rockchip,grf = <&grf>;
 800                 rockchip,hw-tshut-temp = <95000>;
 801                 pinctrl-names = "init", "default", "sleep";
 802                 pinctrl-0 = <&otp_gpio>;
 803                 pinctrl-1 = <&otp_out>;
 804                 pinctrl-2 = <&otp_gpio>;
 805                 #thermal-sensor-cells = <1>;
 806                 status = "disabled";
 807         };
 808
 809         qos_emmc: qos@ffa58000 {
 810                 compatible = "syscon";
 811                 reg = <0x0 0xffa58000 0x0 0x20>;
 812         };
 813
 814         qos_gmac: qos@ffa5c000 {
 815                 compatible = "syscon";
 816                 reg = <0x0 0xffa5c000 0x0 0x20>;
 817         };
 818
 819         qos_pcie: qos@ffa60080 {
 820                 compatible = "syscon";
 821                 reg = <0x0 0xffa60080 0x0 0x20>;
 822         };
 823
 824         qos_usb_host0: qos@ffa60100 {
 825                 compatible = "syscon";
 826                 reg = <0x0 0xffa60100 0x0 0x20>;
 827         };
 828
 829         qos_usb_host1: qos@ffa60180 {
 830                 compatible = "syscon";
 831                 reg = <0x0 0xffa60180 0x0 0x20>;
 832         };
 833
 834         qos_usb_otg0: qos@ffa70000 {
 835                 compatible = "syscon";
 836                 reg = <0x0 0xffa70000 0x0 0x20>;
 837         };
 838
 839         qos_usb_otg1: qos@ffa70080 {
 840                 compatible = "syscon";
 841                 reg = <0x0 0xffa70080 0x0 0x20>;
 842         };
 843
 844         qos_sd: qos@ffa74000 {
 845                 compatible = "syscon";
 846                 reg = <0x0 0xffa74000 0x0 0x20>;
 847         };
 848
 849         qos_sdioaudio: qos@ffa76000 {
 850                 compatible = "syscon";
 851                 reg = <0x0 0xffa76000 0x0 0x20>;
 852         };
 853
 854         qos_hdcp: qos@ffa90000 {
 855                 compatible = "syscon";
 856                 reg = <0x0 0xffa90000 0x0 0x20>;
 857         };
 858
 859         qos_iep: qos@ffa98000 {
 860                 compatible = "syscon";
 861                 reg = <0x0 0xffa98000 0x0 0x20>;
 862         };
 863
 864         qos_isp0_m0: qos@ffaa0000 {
 865                 compatible = "syscon";
 866                 reg = <0x0 0xffaa0000 0x0 0x20>;
 867         };
 868
 869         qos_isp0_m1: qos@ffaa0080 {
 870                 compatible = "syscon";
 871                 reg = <0x0 0xffaa0080 0x0 0x20>;
 872         };
 873
 874         qos_isp1_m0: qos@ffaa8000 {
 875                 compatible = "syscon";
 876                 reg = <0x0 0xffaa8000 0x0 0x20>;
 877         };
 878
 879         qos_isp1_m1: qos@ffaa8080 {
 880                 compatible = "syscon";
 881                 reg = <0x0 0xffaa8080 0x0 0x20>;
 882         };
 883
 884         qos_rga_r: qos@ffab0000 {
 885                 compatible = "syscon";
 886                 reg = <0x0 0xffab0000 0x0 0x20>;
 887         };
 888
 889         qos_rga_w: qos@ffab0080 {
 890                 compatible = "syscon";
 891                 reg = <0x0 0xffab0080 0x0 0x20>;
 892         };
 893
 894         qos_video_m0: qos@ffab8000 {
 895                 compatible = "syscon";
 896                 reg = <0x0 0xffab8000 0x0 0x20>;
 897         };
 898
 899         qos_video_m1_r: qos@ffac0000 {
 900                 compatible = "syscon";
 901                 reg = <0x0 0xffac0000 0x0 0x20>;
 902         };
 903
 904         qos_video_m1_w: qos@ffac0080 {
 905                 compatible = "syscon";
 906                 reg = <0x0 0xffac0080 0x0 0x20>;
 907         };
 908
 909         qos_vop_big_r: qos@ffac8000 {
 910                 compatible = "syscon";
 911                 reg = <0x0 0xffac8000 0x0 0x20>;
 912         };
 913
 914         qos_vop_big_w: qos@ffac8080 {
 915                 compatible = "syscon";
 916                 reg = <0x0 0xffac8080 0x0 0x20>;
 917         };
 918
 919         qos_vop_little: qos@ffad0000 {
 920                 compatible = "syscon";
 921                 reg = <0x0 0xffad0000 0x0 0x20>;
 922         };
 923
 924         qos_perihp: qos@ffad8080 {
 925                 compatible = "syscon";
 926                 reg = <0x0 0xffad8080 0x0 0x20>;
 927         };
 928
 929         qos_gpu: qos@ffae0000 {
 930                 compatible = "syscon";
 931                 reg = <0x0 0xffae0000 0x0 0x20>;
 932         };
 933
 934         pmu: power-management@ff310000 {
 935                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 936                 reg = <0x0 0xff310000 0x0 0x1000>;
 937
 938                 /*
 939                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 940                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 941                  * Some of the power domains are grouped together for every
 942                  * voltage domain.
 943                  * The detail contents as below.
 944                  */
 945                 power: power-controller {
 946                         compatible = "rockchip,rk3399-power-controller";
 947                         #power-domain-cells = <1>;
 948                         #address-cells = <1>;
 949                         #size-cells = <0>;
 950
 951                         /* These power domains are grouped by VD_CENTER */
 952                         pd_iep@RK3399_PD_IEP {
 953                                 reg = <RK3399_PD_IEP>;
 954                                 clocks = <&cru ACLK_IEP>,
 955                                          <&cru HCLK_IEP>;
 956                                 pm_qos = <&qos_iep>;
 957                         };
 958                         pd_rga@RK3399_PD_RGA {
 959                                 reg = <RK3399_PD_RGA>;
 960                                 clocks = <&cru ACLK_RGA>,
 961                                          <&cru HCLK_RGA>;
 962                                 pm_qos = <&qos_rga_r>,
 963                                          <&qos_rga_w>;
 964                         };
 965                         pd_vcodec@RK3399_PD_VCODEC {
 966                                 reg = <RK3399_PD_VCODEC>;
 967                                 clocks = <&cru ACLK_VCODEC>,
 968                                          <&cru HCLK_VCODEC>;
 969                                 pm_qos = <&qos_video_m0>;
 970                         };
 971                         pd_vdu@RK3399_PD_VDU {
 972                                 reg = <RK3399_PD_VDU>;
 973                                 clocks = <&cru ACLK_VDU>,
 974                                          <&cru HCLK_VDU>;
 975                                 pm_qos = <&qos_video_m1_r>,
 976                                          <&qos_video_m1_w>;
 977                         };
 978
 979                         /* These power domains are grouped by VD_GPU */
 980                         pd_gpu@RK3399_PD_GPU {
 981                                 reg = <RK3399_PD_GPU>;
 982                                 clocks = <&cru ACLK_GPU>;
 983                                 pm_qos = <&qos_gpu>;
 984                         };
 985
 986                         /* These power domains are grouped by VD_LOGIC */
 987                         pd_edp@RK3399_PD_EDP {
 988                                 reg = <RK3399_PD_EDP>;
 989                                 clocks = <&cru PCLK_EDP_CTRL>;
 990                         };
 991                         pd_emmc@RK3399_PD_EMMC {
 992                                 reg = <RK3399_PD_EMMC>;
 993                                 clocks = <&cru ACLK_EMMC>;
 994                                 pm_qos = <&qos_emmc>;
 995                         };
 996                         pd_gmac@RK3399_PD_GMAC {
 997                                 reg = <RK3399_PD_GMAC>;
 998                                 clocks = <&cru ACLK_GMAC>,
 999                                          <&cru PCLK_GMAC>;
1000                                 pm_qos = <&qos_gmac>;
1001                         };
1002                         pd_sd@RK3399_PD_SD {
1003                                 reg = <RK3399_PD_SD>;
1004                                 clocks = <&cru HCLK_SDMMC>,
1005                                          <&cru SCLK_SDMMC>;
1006                                 pm_qos = <&qos_sd>;
1007                         };
1008                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1009                                 reg = <RK3399_PD_SDIOAUDIO>;
1010                                 clocks = <&cru HCLK_SDIO>;
1011                                 pm_qos = <&qos_sdioaudio>;
1012                         };
1013                         pd_usb3@RK3399_PD_USB3 {
1014                                 reg = <RK3399_PD_USB3>;
1015                                 clocks = <&cru ACLK_USB3>;
1016                                 pm_qos = <&qos_usb_otg0>,
1017                                          <&qos_usb_otg1>;
1018                         };
1019                         pd_vio@RK3399_PD_VIO {
1020                                 reg = <RK3399_PD_VIO>;
1021                                 #address-cells = <1>;
1022                                 #size-cells = <0>;
1023
1024                                 pd_hdcp@RK3399_PD_HDCP {
1025                                         reg = <RK3399_PD_HDCP>;
1026                                         clocks = <&cru ACLK_HDCP>,
1027                                                  <&cru HCLK_HDCP>,
1028                                                  <&cru PCLK_HDCP>;
1029                                         pm_qos = <&qos_hdcp>;
1030                                 };
1031                                 pd_isp0@RK3399_PD_ISP0 {
1032                                         reg = <RK3399_PD_ISP0>;
1033                                         clocks = <&cru ACLK_ISP0>,
1034                                                  <&cru HCLK_ISP0>;
1035                                         pm_qos = <&qos_isp0_m0>,
1036                                                  <&qos_isp0_m1>;
1037                                 };
1038                                 pd_isp1@RK3399_PD_ISP1 {
1039                                         reg = <RK3399_PD_ISP1>;
1040                                         clocks = <&cru ACLK_ISP1>,
1041                                                  <&cru HCLK_ISP1>;
1042                                         pm_qos = <&qos_isp1_m0>,
1043                                                  <&qos_isp1_m1>;
1044                                 };
1045                                 pd_tcpc0@RK3399_PD_TCPC0 {
1046                                         reg = <RK3399_PD_TCPD0>;
1047                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1048                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1049                                 };
1050                                 pd_tcpc1@RK3399_PD_TCPC1 {
1051                                         reg = <RK3399_PD_TCPD1>;
1052                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1053                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1054                                 };
1055                                 pd_vo@RK3399_PD_VO {
1056                                         reg = <RK3399_PD_VO>;
1057                                         #address-cells = <1>;
1058                                         #size-cells = <0>;
1059
1060                                         pd_vopb@RK3399_PD_VOPB {
1061                                                 reg = <RK3399_PD_VOPB>;
1062                                                 clocks = <&cru ACLK_VOP0>,
1063                                                          <&cru HCLK_VOP0>;
1064                                                 pm_qos = <&qos_vop_big_r>,
1065                                                          <&qos_vop_big_w>;
1066                                         };
1067                                         pd_vopl@RK3399_PD_VOPL {
1068                                                 reg = <RK3399_PD_VOPL>;
1069                                                 clocks = <&cru ACLK_VOP1>,
1070                                                          <&cru HCLK_VOP1>;
1071                                                 pm_qos = <&qos_vop_little>;
1072                                         };
1073                                 };
1074                         };
1075                 };
1076         };
1077
1078         pmugrf: syscon@ff320000 {
1079                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1080                 reg = <0x0 0xff320000 0x0 0x1000>;
1081                 #address-cells = <1>;
1082                 #size-cells = <1>;
1083
1084                 pmu_io_domains: io-domains {
1085                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1086                         status = "disabled";
1087                 };
1088         };
1089
1090         spi3: spi@ff350000 {
1091                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1092                 reg = <0x0 0xff350000 0x0 0x1000>;
1093                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1094                 clock-names = "spiclk", "apb_pclk";
1095                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1096                 pinctrl-names = "default";
1097                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1098                 #address-cells = <1>;
1099                 #size-cells = <0>;
1100                 status = "disabled";
1101         };
1102
1103         uart4: serial@ff370000 {
1104                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1105                 reg = <0x0 0xff370000 0x0 0x100>;
1106                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1107                 clock-names = "baudclk", "apb_pclk";
1108                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1109                 reg-shift = <2>;
1110                 reg-io-width = <4>;
1111                 pinctrl-names = "default";
1112                 pinctrl-0 = <&uart4_xfer>;
1113                 status = "disabled";
1114         };
1115
1116         i2c0: i2c@ff3c0000 {
1117                 compatible = "rockchip,rk3399-i2c";
1118                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1119                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1120                 assigned-clock-rates = <200000000>;
1121                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1122                 clock-names = "i2c", "pclk";
1123                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1124                 pinctrl-names = "default";
1125                 pinctrl-0 = <&i2c0_xfer>;
1126                 #address-cells = <1>;
1127                 #size-cells = <0>;
1128                 status = "disabled";
1129         };
1130
1131         i2c4: i2c@ff3d0000 {
1132                 compatible = "rockchip,rk3399-i2c";
1133                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1134                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1135                 assigned-clock-rates = <200000000>;
1136                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1137                 clock-names = "i2c", "pclk";
1138                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1139                 pinctrl-names = "default";
1140                 pinctrl-0 = <&i2c4_xfer>;
1141                 #address-cells = <1>;
1142                 #size-cells = <0>;
1143                 status = "disabled";
1144         };
1145
1146         i2c8: i2c@ff3e0000 {
1147                 compatible = "rockchip,rk3399-i2c";
1148                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1149                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1150                 assigned-clock-rates = <200000000>;
1151                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1152                 clock-names = "i2c", "pclk";
1153                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1154                 pinctrl-names = "default";
1155                 pinctrl-0 = <&i2c8_xfer>;
1156                 #address-cells = <1>;
1157                 #size-cells = <0>;
1158                 status = "disabled";
1159         };
1160
1161         pwm0: pwm@ff420000 {
1162                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1163                 reg = <0x0 0xff420000 0x0 0x10>;
1164                 #pwm-cells = <3>;
1165                 pinctrl-names = "default";
1166                 pinctrl-0 = <&pwm0_pin>;
1167                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1168                 clock-names = "pwm";
1169                 status = "disabled";
1170         };
1171
1172         pwm1: pwm@ff420010 {
1173                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1174                 reg = <0x0 0xff420010 0x0 0x10>;
1175                 #pwm-cells = <3>;
1176                 pinctrl-names = "default";
1177                 pinctrl-0 = <&pwm1_pin>;
1178                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1179                 clock-names = "pwm";
1180                 status = "disabled";
1181         };
1182
1183         pwm2: pwm@ff420020 {
1184                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1185                 reg = <0x0 0xff420020 0x0 0x10>;
1186                 #pwm-cells = <3>;
1187                 pinctrl-names = "default";
1188                 pinctrl-0 = <&pwm2_pin>;
1189                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1190                 clock-names = "pwm";
1191                 status = "disabled";
1192         };
1193
1194         pwm3: pwm@ff420030 {
1195                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1196                 reg = <0x0 0xff420030 0x0 0x10>;
1197                 #pwm-cells = <3>;
1198                 pinctrl-names = "default";
1199                 pinctrl-0 = <&pwm3a_pin>;
1200                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1201                 clock-names = "pwm";
1202                 status = "disabled";
1203         };
1204
1205         vpu_mmu: iommu@ff650800 {
1206                 compatible = "rockchip,iommu";
1207                 reg = <0x0 0xff650800 0x0 0x40>;
1208                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1209                 interrupt-names = "vpu_mmu";
1210                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1211                 clock-names = "aclk", "iface";
1212                 #iommu-cells = <0>;
1213                 status = "disabled";
1214         };
1215
1216         vdec_mmu: iommu@ff660480 {
1217                 compatible = "rockchip,iommu";
1218                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1219                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1220                 interrupt-names = "vdec_mmu";
1221                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1222                 clock-names = "aclk", "iface";
1223                 #iommu-cells = <0>;
1224                 status = "disabled";
1225         };
1226
1227         iep_mmu: iommu@ff670800 {
1228                 compatible = "rockchip,iommu";
1229                 reg = <0x0 0xff670800 0x0 0x40>;
1230                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1231                 interrupt-names = "iep_mmu";
1232                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1233                 clock-names = "aclk", "iface";
1234                 #iommu-cells = <0>;
1235                 status = "disabled";
1236         };
1237
1238         rga: rga@ff680000 {
1239                 compatible = "rockchip,rk3399-rga";
1240                 reg = <0x0 0xff680000 0x0 0x10000>;
1241                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1242                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1243                 clock-names = "aclk", "hclk", "sclk";
1244                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1245                 reset-names = "core", "axi", "ahb";
1246                 power-domains = <&power RK3399_PD_RGA>;
1247         };
1248
1249         efuse0: efuse@ff690000 {
1250                 compatible = "rockchip,rk3399-efuse";
1251                 reg = <0x0 0xff690000 0x0 0x80>;
1252                 #address-cells = <1>;
1253                 #size-cells = <1>;
1254                 clocks = <&cru PCLK_EFUSE1024NS>;
1255                 clock-names = "pclk_efuse";
1256
1257                 /* Data cells */
1258                 cpu_id: cpu-id@7 {
1259                         reg = <0x07 0x10>;
1260                 };
1261                 cpub_leakage: cpu-leakage@17 {
1262                         reg = <0x17 0x1>;
1263                 };
1264                 gpu_leakage: gpu-leakage@18 {
1265                         reg = <0x18 0x1>;
1266                 };
1267                 center_leakage: center-leakage@19 {
1268                         reg = <0x19 0x1>;
1269                 };
1270                 cpul_leakage: cpu-leakage@1a {
1271                         reg = <0x1a 0x1>;
1272                 };
1273                 logic_leakage: logic-leakage@1b {
1274                         reg = <0x1b 0x1>;
1275                 };
1276                 wafer_info: wafer-info@1c {
1277                         reg = <0x1c 0x1>;
1278                 };
1279         };
1280
1281         pmucru: pmu-clock-controller@ff750000 {
1282                 compatible = "rockchip,rk3399-pmucru";
1283                 reg = <0x0 0xff750000 0x0 0x1000>;
1284                 rockchip,grf = <&pmugrf>;
1285                 #clock-cells = <1>;
1286                 #reset-cells = <1>;
1287                 assigned-clocks = <&pmucru PLL_PPLL>;
1288                 assigned-clock-rates = <676000000>;
1289         };
1290
1291         cru: clock-controller@ff760000 {
1292                 compatible = "rockchip,rk3399-cru";
1293                 reg = <0x0 0xff760000 0x0 0x1000>;
1294                 rockchip,grf = <&grf>;
1295                 #clock-cells = <1>;
1296                 #reset-cells = <1>;
1297                 assigned-clocks =
1298                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1299                         <&cru PLL_NPLL>,
1300                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1301                         <&cru PCLK_PERIHP>,
1302                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1303                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1304                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1305                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1306                         <&cru ACLK_GIC_PRE>,
1307                         <&cru PCLK_DDR>;
1308                 assigned-clock-rates =
1309                          <594000000>,  <800000000>,
1310                         <1000000000>,
1311                          <150000000>,   <75000000>,
1312                           <37500000>,
1313                          <100000000>,  <100000000>,
1314                           <50000000>, <600000000>,
1315                          <100000000>,   <50000000>,
1316                          <400000000>, <400000000>,
1317                          <200000000>,
1318                          <200000000>;
1319         };
1320
1321         grf: syscon@ff770000 {
1322                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1323                 reg = <0x0 0xff770000 0x0 0x10000>;
1324                 #address-cells = <1>;
1325                 #size-cells = <1>;
1326
1327                 io_domains: io-domains {
1328                         compatible = "rockchip,rk3399-io-voltage-domain";
1329                         status = "disabled";
1330                 };
1331
1332                 u2phy0: usb2-phy@e450 {
1333                         compatible = "rockchip,rk3399-usb2phy";
1334                         reg = <0xe450 0x10>;
1335                         clocks = <&cru SCLK_USB2PHY0_REF>;
1336                         clock-names = "phyclk";
1337                         #clock-cells = <0>;
1338                         clock-output-names = "clk_usbphy0_480m";
1339                         status = "disabled";
1340
1341                         u2phy0_host: host-port {
1342                                 #phy-cells = <0>;
1343                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1344                                 interrupt-names = "linestate";
1345                                 status = "disabled";
1346                         };
1347
1348                         u2phy0_otg: otg-port {
1349                                 #phy-cells = <0>;
1350                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1351                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1352                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1353                                 interrupt-names = "otg-bvalid", "otg-id",
1354                                                   "linestate";
1355                                 status = "disabled";
1356                         };
1357                 };
1358
1359                 u2phy1: usb2-phy@e460 {
1360                         compatible = "rockchip,rk3399-usb2phy";
1361                         reg = <0xe460 0x10>;
1362                         clocks = <&cru SCLK_USB2PHY1_REF>;
1363                         clock-names = "phyclk";
1364                         #clock-cells = <0>;
1365                         clock-output-names = "clk_usbphy1_480m";
1366                         status = "disabled";
1367
1368                         u2phy1_host: host-port {
1369                                 #phy-cells = <0>;
1370                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1371                                 interrupt-names = "linestate";
1372                                 status = "disabled";
1373                         };
1374
1375                         u2phy1_otg: otg-port {
1376                                 #phy-cells = <0>;
1377                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1378                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1379                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1380                                 interrupt-names = "otg-bvalid", "otg-id",
1381                                                   "linestate";
1382                                 status = "disabled";
1383                         };
1384                 };
1385
1386                 emmc_phy: phy@f780 {
1387                         compatible = "rockchip,rk3399-emmc-phy";
1388                         reg = <0xf780 0x24>;
1389                         clocks = <&sdhci>;
1390                         clock-names = "emmcclk";
1391                         #phy-cells = <0>;
1392                         status = "disabled";
1393                 };
1394
1395                 pcie_phy: pcie-phy {
1396                         compatible = "rockchip,rk3399-pcie-phy";
1397                         clocks = <&cru SCLK_PCIEPHY_REF>;
1398                         clock-names = "refclk";
1399                         #phy-cells = <1>;
1400                         resets = <&cru SRST_PCIEPHY>;
1401                         reset-names = "phy";
1402                         status = "disabled";
1403                 };
1404         };
1405
1406         tcphy0: phy@ff7c0000 {
1407                 compatible = "rockchip,rk3399-typec-phy";
1408                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1409                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1410                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1411                 clock-names = "tcpdcore", "tcpdphy-ref";
1412                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1413                 assigned-clock-rates = <50000000>;
1414                 power-domains = <&power RK3399_PD_TCPD0>;
1415                 resets = <&cru SRST_UPHY0>,
1416                          <&cru SRST_UPHY0_PIPE_L00>,
1417                          <&cru SRST_P_UPHY0_TCPHY>;
1418                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1419                 rockchip,grf = <&grf>;
1420                 status = "disabled";
1421
1422                 tcphy0_dp: dp-port {
1423                         #phy-cells = <0>;
1424                 };
1425
1426                 tcphy0_usb3: usb3-port {
1427                         #phy-cells = <0>;
1428                 };
1429         };
1430
1431         tcphy1: phy@ff800000 {
1432                 compatible = "rockchip,rk3399-typec-phy";
1433                 reg = <0x0 0xff800000 0x0 0x40000>;
1434                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1435                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1436                 clock-names = "tcpdcore", "tcpdphy-ref";
1437                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1438                 assigned-clock-rates = <50000000>;
1439                 power-domains = <&power RK3399_PD_TCPD1>;
1440                 resets = <&cru SRST_UPHY1>,
1441                          <&cru SRST_UPHY1_PIPE_L00>,
1442                          <&cru SRST_P_UPHY1_TCPHY>;
1443                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1444                 rockchip,grf = <&grf>;
1445                 status = "disabled";
1446
1447                 tcphy1_dp: dp-port {
1448                         #phy-cells = <0>;
1449                 };
1450
1451                 tcphy1_usb3: usb3-port {
1452                         #phy-cells = <0>;
1453                 };
1454         };
1455
1456         watchdog@ff848000 {
1457                 compatible = "snps,dw-wdt";
1458                 reg = <0x0 0xff848000 0x0 0x100>;
1459                 clocks = <&cru PCLK_WDT>;
1460                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1461         };
1462
1463         rktimer: rktimer@ff850000 {
1464                 compatible = "rockchip,rk3399-timer";
1465                 reg = <0x0 0xff850000 0x0 0x1000>;
1466                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1467                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1468                 clock-names = "pclk", "timer";
1469         };
1470
1471         spdif: spdif@ff870000 {
1472                 compatible = "rockchip,rk3399-spdif";
1473                 reg = <0x0 0xff870000 0x0 0x1000>;
1474                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1475                 dmas = <&dmac_bus 7>;
1476                 dma-names = "tx";
1477                 clock-names = "mclk", "hclk";
1478                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1479                 pinctrl-names = "default";
1480                 pinctrl-0 = <&spdif_bus>;
1481                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1482                 #sound-dai-cells = <0>;
1483                 status = "disabled";
1484         };
1485
1486         i2s0: i2s@ff880000 {
1487                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1488                 reg = <0x0 0xff880000 0x0 0x1000>;
1489                 rockchip,grf = <&grf>;
1490                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1491                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1492                 dma-names = "tx", "rx";
1493                 clock-names = "i2s_clk", "i2s_hclk";
1494                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1495                 pinctrl-names = "default";
1496                 pinctrl-0 = <&i2s0_8ch_bus>;
1497                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1498                 #sound-dai-cells = <0>;
1499                 status = "disabled";
1500         };
1501
1502         i2s1: i2s@ff890000 {
1503                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1504                 reg = <0x0 0xff890000 0x0 0x1000>;
1505                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1506                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1507                 dma-names = "tx", "rx";
1508                 clock-names = "i2s_clk", "i2s_hclk";
1509                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1510                 pinctrl-names = "default";
1511                 pinctrl-0 = <&i2s1_2ch_bus>;
1512                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1513                 #sound-dai-cells = <0>;
1514                 status = "disabled";
1515         };
1516
1517         i2s2: i2s@ff8a0000 {
1518                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1519                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1520                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1521                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1522                 dma-names = "tx", "rx";
1523                 clock-names = "i2s_clk", "i2s_hclk";
1524                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1525                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1526                 #sound-dai-cells = <0>;
1527                 status = "disabled";
1528         };
1529
1530         vopl: vop@ff8f0000 {
1531                 compatible = "rockchip,rk3399-vop-lit";
1532                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1533                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1534                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1535                 assigned-clock-rates = <400000000>, <100000000>;
1536                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1537                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1538                 iommus = <&vopl_mmu>;
1539                 power-domains = <&power RK3399_PD_VOPL>;
1540                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1541                 reset-names = "axi", "ahb", "dclk";
1542                 status = "disabled";
1543
1544                 vopl_out: port {
1545                         #address-cells = <1>;
1546                         #size-cells = <0>;
1547
1548                         vopl_out_mipi: endpoint@0 {
1549                                 reg = <0>;
1550                                 remote-endpoint = <&mipi_in_vopl>;
1551                         };
1552
1553                         vopl_out_edp: endpoint@1 {
1554                                 reg = <1>;
1555                                 remote-endpoint = <&edp_in_vopl>;
1556                         };
1557
1558                         vopl_out_hdmi: endpoint@2 {
1559                                 reg = <2>;
1560                                 remote-endpoint = <&hdmi_in_vopl>;
1561                         };
1562
1563                         vopl_out_mipi1: endpoint@3 {
1564                                 reg = <3>;
1565                                 remote-endpoint = <&mipi1_in_vopl>;
1566                         };
1567
1568                         vopl_out_dp: endpoint@4 {
1569                                 reg = <4>;
1570                                 remote-endpoint = <&dp_in_vopl>;
1571                         };
1572                 };
1573         };
1574
1575         vopl_mmu: iommu@ff8f3f00 {
1576                 compatible = "rockchip,iommu";
1577                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1578                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1579                 interrupt-names = "vopl_mmu";
1580                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1581                 clock-names = "aclk", "iface";
1582                 power-domains = <&power RK3399_PD_VOPL>;
1583                 #iommu-cells = <0>;
1584                 status = "disabled";
1585         };
1586
1587         vopb: vop@ff900000 {
1588                 compatible = "rockchip,rk3399-vop-big";
1589                 reg = <0x0 0xff900000 0x0 0x3efc>;
1590                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1591                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1592                 assigned-clock-rates = <400000000>, <100000000>;
1593                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1594                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1595                 iommus = <&vopb_mmu>;
1596                 power-domains = <&power RK3399_PD_VOPB>;
1597                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1598                 reset-names = "axi", "ahb", "dclk";
1599                 status = "disabled";
1600
1601                 vopb_out: port {
1602                         #address-cells = <1>;
1603                         #size-cells = <0>;
1604
1605                         vopb_out_edp: endpoint@0 {
1606                                 reg = <0>;
1607                                 remote-endpoint = <&edp_in_vopb>;
1608                         };
1609
1610                         vopb_out_mipi: endpoint@1 {
1611                                 reg = <1>;
1612                                 remote-endpoint = <&mipi_in_vopb>;
1613                         };
1614
1615                         vopb_out_hdmi: endpoint@2 {
1616                                 reg = <2>;
1617                                 remote-endpoint = <&hdmi_in_vopb>;
1618                         };
1619
1620                         vopb_out_mipi1: endpoint@3 {
1621                                 reg = <3>;
1622                                 remote-endpoint = <&mipi1_in_vopb>;
1623                         };
1624
1625                         vopb_out_dp: endpoint@4 {
1626                                 reg = <4>;
1627                                 remote-endpoint = <&dp_in_vopb>;
1628                         };
1629                 };
1630         };
1631
1632         vopb_mmu: iommu@ff903f00 {
1633                 compatible = "rockchip,iommu";
1634                 reg = <0x0 0xff903f00 0x0 0x100>;
1635                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1636                 interrupt-names = "vopb_mmu";
1637                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1638                 clock-names = "aclk", "iface";
1639                 power-domains = <&power RK3399_PD_VOPB>;
1640                 #iommu-cells = <0>;
1641                 status = "disabled";
1642         };
1643
1644         isp0_mmu: iommu@ff914000 {
1645                 compatible = "rockchip,iommu";
1646                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1647                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1648                 interrupt-names = "isp0_mmu";
1649                 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1650                 clock-names = "aclk", "iface";
1651                 #iommu-cells = <0>;
1652                 power-domains = <&power RK3399_PD_ISP0>;
1653                 rockchip,disable-mmu-reset;
1654         };
1655
1656         isp1_mmu: iommu@ff924000 {
1657                 compatible = "rockchip,iommu";
1658                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1659                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1660                 interrupt-names = "isp1_mmu";
1661                 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1662                 clock-names = "aclk", "iface";
1663                 #iommu-cells = <0>;
1664                 power-domains = <&power RK3399_PD_ISP1>;
1665                 rockchip,disable-mmu-reset;
1666         };
1667
1668         hdmi_sound: hdmi-sound {
1669                 compatible = "simple-audio-card";
1670                 simple-audio-card,format = "i2s";
1671                 simple-audio-card,mclk-fs = <256>;
1672                 simple-audio-card,name = "hdmi-sound";
1673                 status = "disabled";
1674
1675                 simple-audio-card,cpu {
1676                         sound-dai = <&i2s2>;
1677                 };
1678                 simple-audio-card,codec {
1679                         sound-dai = <&hdmi>;
1680                 };
1681         };
1682
1683         hdmi: hdmi@ff940000 {
1684                 compatible = "rockchip,rk3399-dw-hdmi";
1685                 reg = <0x0 0xff940000 0x0 0x20000>;
1686                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1687                 clocks = <&cru PCLK_HDMI_CTRL>,
1688                          <&cru SCLK_HDMI_SFR>,
1689                          <&cru SCLK_HDMI_CEC>,
1690                          <&cru PCLK_VIO_GRF>,
1691                          <&cru PLL_VPLL>;
1692                 clock-names = "iahb", "isfr", "cec", "grf", "vpll";
1693                 power-domains = <&power RK3399_PD_HDCP>;
1694                 reg-io-width = <4>;
1695                 rockchip,grf = <&grf>;
1696                 #sound-dai-cells = <0>;
1697                 status = "disabled";
1698
1699                 ports {
1700                         hdmi_in: port {
1701                                 #address-cells = <1>;
1702                                 #size-cells = <0>;
1703
1704                                 hdmi_in_vopb: endpoint@0 {
1705                                         reg = <0>;
1706                                         remote-endpoint = <&vopb_out_hdmi>;
1707                                 };
1708                                 hdmi_in_vopl: endpoint@1 {
1709                                         reg = <1>;
1710                                         remote-endpoint = <&vopl_out_hdmi>;
1711                                 };
1712                         };
1713                 };
1714         };
1715
1716         mipi_dsi: mipi@ff960000 {
1717                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1718                 reg = <0x0 0xff960000 0x0 0x8000>;
1719                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1720                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1721                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1722                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1723                 power-domains = <&power RK3399_PD_VIO>;
1724                 resets = <&cru SRST_P_MIPI_DSI0>;
1725                 reset-names = "apb";
1726                 rockchip,grf = <&grf>;
1727                 status = "disabled";
1728
1729                 ports {
1730                         #address-cells = <1>;
1731                         #size-cells = <0>;
1732
1733                         mipi_in: port@0 {
1734                                 reg = <0>;
1735                                 #address-cells = <1>;
1736                                 #size-cells = <0>;
1737
1738                                 mipi_in_vopb: endpoint@0 {
1739                                         reg = <0>;
1740                                         remote-endpoint = <&vopb_out_mipi>;
1741                                 };
1742                                 mipi_in_vopl: endpoint@1 {
1743                                         reg = <1>;
1744                                         remote-endpoint = <&vopl_out_mipi>;
1745                                 };
1746                         };
1747                 };
1748         };
1749
1750         mipi_dsi1: mipi@ff968000 {
1751                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1752                 reg = <0x0 0xff968000 0x0 0x8000>;
1753                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1754                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1755                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1756                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1757                 power-domains = <&power RK3399_PD_VIO>;
1758                 resets = <&cru SRST_P_MIPI_DSI1>;
1759                 reset-names = "apb";
1760                 rockchip,grf = <&grf>;
1761                 status = "disabled";
1762
1763                 ports {
1764                         #address-cells = <1>;
1765                         #size-cells = <0>;
1766
1767                         mipi1_in: port@0 {
1768                                 reg = <0>;
1769                                 #address-cells = <1>;
1770                                 #size-cells = <0>;
1771
1772                                 mipi1_in_vopb: endpoint@0 {
1773                                         reg = <0>;
1774                                         remote-endpoint = <&vopb_out_mipi1>;
1775                                 };
1776
1777                                 mipi1_in_vopl: endpoint@1 {
1778                                         reg = <1>;
1779                                         remote-endpoint = <&vopl_out_mipi1>;
1780                                 };
1781                         };
1782                 };
1783         };
1784
1785         edp: edp@ff970000 {
1786                 compatible = "rockchip,rk3399-edp";
1787                 reg = <0x0 0xff970000 0x0 0x8000>;
1788                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1789                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1790                 clock-names = "dp", "pclk", "grf";
1791                 pinctrl-names = "default";
1792                 pinctrl-0 = <&edp_hpd>;
1793                 power-domains = <&power RK3399_PD_EDP>;
1794                 resets = <&cru SRST_P_EDP_CTRL>;
1795                 reset-names = "dp";
1796                 rockchip,grf = <&grf>;
1797                 status = "disabled";
1798
1799                 ports {
1800                         #address-cells = <1>;
1801                         #size-cells = <0>;
1802                         edp_in: port@0 {
1803                                 reg = <0>;
1804                                 #address-cells = <1>;
1805                                 #size-cells = <0>;
1806
1807                                 edp_in_vopb: endpoint@0 {
1808                                         reg = <0>;
1809                                         remote-endpoint = <&vopb_out_edp>;
1810                                 };
1811
1812                                 edp_in_vopl: endpoint@1 {
1813                                         reg = <1>;
1814                                         remote-endpoint = <&vopl_out_edp>;
1815                                 };
1816                         };
1817                 };
1818         };
1819
1820         gpu: gpu@ff9a0000 {
1821                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1822                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1823                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1824                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1825                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1826                 interrupt-names = "job", "mmu", "gpu";
1827                 clocks = <&cru ACLK_GPU>;
1828                 power-domains = <&power RK3399_PD_GPU>;
1829                 status = "disabled";
1830         };
1831
1832         pinctrl: pinctrl {
1833                 compatible = "rockchip,rk3399-pinctrl";
1834                 rockchip,grf = <&grf>;
1835                 rockchip,pmu = <&pmugrf>;
1836                 #address-cells = <2>;
1837                 #size-cells = <2>;
1838                 ranges;
1839
1840                 gpio0: gpio0@ff720000 {
1841                         compatible = "rockchip,gpio-bank";
1842                         reg = <0x0 0xff720000 0x0 0x100>;
1843                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1844                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1845
1846                         gpio-controller;
1847                         #gpio-cells = <0x2>;
1848
1849                         interrupt-controller;
1850                         #interrupt-cells = <0x2>;
1851                 };
1852
1853                 gpio1: gpio1@ff730000 {
1854                         compatible = "rockchip,gpio-bank";
1855                         reg = <0x0 0xff730000 0x0 0x100>;
1856                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1857                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1858
1859                         gpio-controller;
1860                         #gpio-cells = <0x2>;
1861
1862                         interrupt-controller;
1863                         #interrupt-cells = <0x2>;
1864                 };
1865
1866                 gpio2: gpio2@ff780000 {
1867                         compatible = "rockchip,gpio-bank";
1868                         reg = <0x0 0xff780000 0x0 0x100>;
1869                         clocks = <&cru PCLK_GPIO2>;
1870                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1871
1872                         gpio-controller;
1873                         #gpio-cells = <0x2>;
1874
1875                         interrupt-controller;
1876                         #interrupt-cells = <0x2>;
1877                 };
1878
1879                 gpio3: gpio3@ff788000 {
1880                         compatible = "rockchip,gpio-bank";
1881                         reg = <0x0 0xff788000 0x0 0x100>;
1882                         clocks = <&cru PCLK_GPIO3>;
1883                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1884
1885                         gpio-controller;
1886                         #gpio-cells = <0x2>;
1887
1888                         interrupt-controller;
1889                         #interrupt-cells = <0x2>;
1890                 };
1891
1892                 gpio4: gpio4@ff790000 {
1893                         compatible = "rockchip,gpio-bank";
1894                         reg = <0x0 0xff790000 0x0 0x100>;
1895                         clocks = <&cru PCLK_GPIO4>;
1896                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1897
1898                         gpio-controller;
1899                         #gpio-cells = <0x2>;
1900
1901                         interrupt-controller;
1902                         #interrupt-cells = <0x2>;
1903                 };
1904
1905                 pcfg_pull_up: pcfg-pull-up {
1906                         bias-pull-up;
1907                 };
1908
1909                 pcfg_pull_down: pcfg-pull-down {
1910                         bias-pull-down;
1911                 };
1912
1913                 pcfg_pull_none: pcfg-pull-none {
1914                         bias-disable;
1915                 };
1916
1917                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1918                         bias-disable;
1919                         drive-strength = <12>;
1920                 };
1921
1922                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1923                         bias-disable;
1924                         drive-strength = <13>;
1925                 };
1926
1927                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1928                         bias-disable;
1929                         drive-strength = <18>;
1930                 };
1931
1932                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1933                         bias-disable;
1934                         drive-strength = <20>;
1935                 };
1936
1937                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1938                         bias-pull-up;
1939                         drive-strength = <2>;
1940                 };
1941
1942                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1943                         bias-pull-up;
1944                         drive-strength = <8>;
1945                 };
1946
1947                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
1948                         bias-pull-up;
1949                         drive-strength = <18>;
1950                 };
1951
1952                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1953                         bias-pull-up;
1954                         drive-strength = <20>;
1955                 };
1956
1957                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1958                         bias-pull-down;
1959                         drive-strength = <4>;
1960                 };
1961
1962                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
1963                         bias-pull-down;
1964                         drive-strength = <8>;
1965                 };
1966
1967                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1968                         bias-pull-down;
1969                         drive-strength = <12>;
1970                 };
1971
1972                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
1973                         bias-pull-down;
1974                         drive-strength = <18>;
1975                 };
1976
1977                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
1978                         bias-pull-down;
1979                         drive-strength = <20>;
1980                 };
1981
1982                 pcfg_output_high: pcfg-output-high {
1983                         output-high;
1984                 };
1985
1986                 pcfg_output_low: pcfg-output-low {
1987                         output-low;
1988                 };
1989
1990                 clock {
1991                         clk_32k: clk-32k {
1992                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1993                         };
1994                 };
1995
1996                 edp {
1997                         edp_hpd: edp-hpd {
1998                                 rockchip,pins =
1999                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2000                         };
2001                 };
2002
2003                 gmac {
2004                         rgmii_pins: rgmii-pins {
2005                                 rockchip,pins =
2006                                         /* mac_txclk */
2007                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2008                                         /* mac_rxclk */
2009                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2010                                         /* mac_mdio */
2011                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2012                                         /* mac_txen */
2013                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2014                                         /* mac_clk */
2015                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2016                                         /* mac_rxdv */
2017                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2018                                         /* mac_mdc */
2019                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2020                                         /* mac_rxd1 */
2021                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2022                                         /* mac_rxd0 */
2023                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2024                                         /* mac_txd1 */
2025                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2026                                         /* mac_txd0 */
2027                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2028                                         /* mac_rxd3 */
2029                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2030                                         /* mac_rxd2 */
2031                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2032                                         /* mac_txd3 */
2033                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2034                                         /* mac_txd2 */
2035                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2036                         };
2037
2038                         rmii_pins: rmii-pins {
2039                                 rockchip,pins =
2040                                         /* mac_mdio */
2041                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2042                                         /* mac_txen */
2043                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2044                                         /* mac_clk */
2045                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2046                                         /* mac_rxer */
2047                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2048                                         /* mac_rxdv */
2049                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2050                                         /* mac_mdc */
2051                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2052                                         /* mac_rxd1 */
2053                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2054                                         /* mac_rxd0 */
2055                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2056                                         /* mac_txd1 */
2057                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2058                                         /* mac_txd0 */
2059                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2060                         };
2061                 };
2062
2063                 i2c0 {
2064                         i2c0_xfer: i2c0-xfer {
2065                                 rockchip,pins =
2066                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2067                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2068                         };
2069                 };
2070
2071                 i2c1 {
2072                         i2c1_xfer: i2c1-xfer {
2073                                 rockchip,pins =
2074                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2075                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2076                         };
2077                 };
2078
2079                 i2c2 {
2080                         i2c2_xfer: i2c2-xfer {
2081                                 rockchip,pins =
2082                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2083                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2084                         };
2085                 };
2086
2087                 i2c3 {
2088                         i2c3_xfer: i2c3-xfer {
2089                                 rockchip,pins =
2090                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2091                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2092                         };
2093                 };
2094
2095                 i2c4 {
2096                         i2c4_xfer: i2c4-xfer {
2097                                 rockchip,pins =
2098                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2099                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2100                         };
2101                 };
2102
2103                 i2c5 {
2104                         i2c5_xfer: i2c5-xfer {
2105                                 rockchip,pins =
2106                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2107                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2108                         };
2109                 };
2110
2111                 i2c6 {
2112                         i2c6_xfer: i2c6-xfer {
2113                                 rockchip,pins =
2114                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2115                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2116                         };
2117                 };
2118
2119                 i2c7 {
2120                         i2c7_xfer: i2c7-xfer {
2121                                 rockchip,pins =
2122                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2123                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2124                         };
2125                 };
2126
2127                 i2c8 {
2128                         i2c8_xfer: i2c8-xfer {
2129                                 rockchip,pins =
2130                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2131                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2132                         };
2133                 };
2134
2135                 i2s0 {
2136                         i2s0_2ch_bus: i2s0-2ch-bus {
2137                                 rockchip,pins =
2138                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2139                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2140                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2141                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2142                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2143                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2144                         };
2145
2146                         i2s0_8ch_bus: i2s0-8ch-bus {
2147                                 rockchip,pins =
2148                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2149                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2150                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2151                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2152                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2153                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2154                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2155                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2156                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2157                         };
2158                 };
2159
2160                 i2s1 {
2161                         i2s1_2ch_bus: i2s1-2ch-bus {
2162                                 rockchip,pins =
2163                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2164                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2165                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2166                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2167                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2168                         };
2169                 };
2170
2171                 sdio0 {
2172                         sdio0_bus1: sdio0-bus1 {
2173                                 rockchip,pins =
2174                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2175                         };
2176
2177                         sdio0_bus4: sdio0-bus4 {
2178                                 rockchip,pins =
2179                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2180                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2181                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2182                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2183                         };
2184
2185                         sdio0_cmd: sdio0-cmd {
2186                                 rockchip,pins =
2187                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2188                         };
2189
2190                         sdio0_clk: sdio0-clk {
2191                                 rockchip,pins =
2192                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2193                         };
2194
2195                         sdio0_cd: sdio0-cd {
2196                                 rockchip,pins =
2197                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2198                         };
2199
2200                         sdio0_pwr: sdio0-pwr {
2201                                 rockchip,pins =
2202                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2203                         };
2204
2205                         sdio0_bkpwr: sdio0-bkpwr {
2206                                 rockchip,pins =
2207                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2208                         };
2209
2210                         sdio0_wp: sdio0-wp {
2211                                 rockchip,pins =
2212                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2213                         };
2214
2215                         sdio0_int: sdio0-int {
2216                                 rockchip,pins =
2217                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2218                         };
2219                 };
2220
2221                 sdmmc {
2222                         sdmmc_bus1: sdmmc-bus1 {
2223                                 rockchip,pins =
2224                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2225                         };
2226
2227                         sdmmc_bus4: sdmmc-bus4 {
2228                                 rockchip,pins =
2229                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2230                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2231                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2232                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2233                         };
2234
2235                         sdmmc_clk: sdmmc-clk {
2236                                 rockchip,pins =
2237                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2238                         };
2239
2240                         sdmmc_cmd: sdmmc-cmd {
2241                                 rockchip,pins =
2242                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2243                         };
2244
2245                         sdmmc_cd: sdmmc-cd {
2246                                 rockchip,pins =
2247                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2248                         };
2249
2250                         sdmmc_wp: sdmmc-wp {
2251                                 rockchip,pins =
2252                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2253                         };
2254                 };
2255
2256                 suspend {
2257                         ap_pwroff: ap-pwroff {
2258                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2259                         };
2260
2261                         ddrio_pwroff: ddrio-pwroff {
2262                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2263                         };
2264                 };
2265
2266                 spdif {
2267                         spdif_bus: spdif-bus {
2268                                 rockchip,pins =
2269                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2270                         };
2271
2272                         spdif_bus_1: spdif-bus-1 {
2273                                 rockchip,pins =
2274                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2275                         };
2276                 };
2277
2278                 spi0 {
2279                         spi0_clk: spi0-clk {
2280                                 rockchip,pins =
2281                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2282                         };
2283                         spi0_cs0: spi0-cs0 {
2284                                 rockchip,pins =
2285                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2286                         };
2287                         spi0_cs1: spi0-cs1 {
2288                                 rockchip,pins =
2289                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2290                         };
2291                         spi0_tx: spi0-tx {
2292                                 rockchip,pins =
2293                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2294                         };
2295                         spi0_rx: spi0-rx {
2296                                 rockchip,pins =
2297                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2298                         };
2299                 };
2300
2301                 spi1 {
2302                         spi1_clk: spi1-clk {
2303                                 rockchip,pins =
2304                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2305                         };
2306                         spi1_cs0: spi1-cs0 {
2307                                 rockchip,pins =
2308                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2309                         };
2310                         spi1_rx: spi1-rx {
2311                                 rockchip,pins =
2312                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2313                         };
2314                         spi1_tx: spi1-tx {
2315                                 rockchip,pins =
2316                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2317                         };
2318                 };
2319
2320                 spi2 {
2321                         spi2_clk: spi2-clk {
2322                                 rockchip,pins =
2323                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2324                         };
2325                         spi2_cs0: spi2-cs0 {
2326                                 rockchip,pins =
2327                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2328                         };
2329                         spi2_rx: spi2-rx {
2330                                 rockchip,pins =
2331                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2332                         };
2333                         spi2_tx: spi2-tx {
2334                                 rockchip,pins =
2335                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2336                         };
2337                 };
2338
2339                 spi3 {
2340                         spi3_clk: spi3-clk {
2341                                 rockchip,pins =
2342                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2343                         };
2344                         spi3_cs0: spi3-cs0 {
2345                                 rockchip,pins =
2346                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2347                         };
2348                         spi3_rx: spi3-rx {
2349                                 rockchip,pins =
2350                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2351                         };
2352                         spi3_tx: spi3-tx {
2353                                 rockchip,pins =
2354                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2355                         };
2356                 };
2357
2358                 spi4 {
2359                         spi4_clk: spi4-clk {
2360                                 rockchip,pins =
2361                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2362                         };
2363                         spi4_cs0: spi4-cs0 {
2364                                 rockchip,pins =
2365                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2366                         };
2367                         spi4_rx: spi4-rx {
2368                                 rockchip,pins =
2369                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2370                         };
2371                         spi4_tx: spi4-tx {
2372                                 rockchip,pins =
2373                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2374                         };
2375                 };
2376
2377                 spi5 {
2378                         spi5_clk: spi5-clk {
2379                                 rockchip,pins =
2380                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2381                         };
2382                         spi5_cs0: spi5-cs0 {
2383                                 rockchip,pins =
2384                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2385                         };
2386                         spi5_rx: spi5-rx {
2387                                 rockchip,pins =
2388                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2389                         };
2390                         spi5_tx: spi5-tx {
2391                                 rockchip,pins =
2392                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2393                         };
2394                 };
2395
2396                 testclk {
2397                         test_clkout0: test-clkout0 {
2398                                 rockchip,pins =
2399                                         <0 0 RK_FUNC_1 &pcfg_pull_none>;
2400                         };
2401
2402                         test_clkout1: test-clkout1 {
2403                                 rockchip,pins =
2404                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
2405                         };
2406
2407                         test_clkout2: test-clkout2 {
2408                                 rockchip,pins =
2409                                         <0 8 RK_FUNC_3 &pcfg_pull_none>;
2410                         };
2411                 };
2412
2413                 tsadc {
2414                         otp_gpio: otp-gpio {
2415                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2416                         };
2417
2418                         otp_out: otp-out {
2419                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2420                         };
2421                 };
2422
2423                 uart0 {
2424                         uart0_xfer: uart0-xfer {
2425                                 rockchip,pins =
2426                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2427                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2428                         };
2429
2430                         uart0_cts: uart0-cts {
2431                                 rockchip,pins =
2432                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2433                         };
2434
2435                         uart0_rts: uart0-rts {
2436                                 rockchip,pins =
2437                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2438                         };
2439                 };
2440
2441                 uart1 {
2442                         uart1_xfer: uart1-xfer {
2443                                 rockchip,pins =
2444                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2445                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2446                         };
2447                 };
2448
2449                 uart2a {
2450                         uart2a_xfer: uart2a-xfer {
2451                                 rockchip,pins =
2452                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2453                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2454                         };
2455                 };
2456
2457                 uart2b {
2458                         uart2b_xfer: uart2b-xfer {
2459                                 rockchip,pins =
2460                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2461                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2462                         };
2463                 };
2464
2465                 uart2c {
2466                         uart2c_xfer: uart2c-xfer {
2467                                 rockchip,pins =
2468                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2469                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2470                         };
2471                 };
2472
2473                 uart3 {
2474                         uart3_xfer: uart3-xfer {
2475                                 rockchip,pins =
2476                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2477                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2478                         };
2479
2480                         uart3_cts: uart3-cts {
2481                                 rockchip,pins =
2482                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2483                         };
2484
2485                         uart3_rts: uart3-rts {
2486                                 rockchip,pins =
2487                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2488                         };
2489                 };
2490
2491                 uart4 {
2492                         uart4_xfer: uart4-xfer {
2493                                 rockchip,pins =
2494                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2495                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2496                         };
2497                 };
2498
2499                 uarthdcp {
2500                         uarthdcp_xfer: uarthdcp-xfer {
2501                                 rockchip,pins =
2502                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2503                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2504                         };
2505                 };
2506
2507                 pwm0 {
2508                         pwm0_pin: pwm0-pin {
2509                                 rockchip,pins =
2510                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2511                         };
2512
2513                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2514                                 rockchip,pins =
2515                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>;
2516                         };
2517
2518                         vop0_pwm_pin: vop0-pwm-pin {
2519                                 rockchip,pins =
2520                                         <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2521                         };
2522
2523                         vop1_pwm_pin: vop1-pwm-pin {
2524                                 rockchip,pins =
2525                                         <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2526                         };
2527                 };
2528
2529                 pwm1 {
2530                         pwm1_pin: pwm1-pin {
2531                                 rockchip,pins =
2532                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2533                         };
2534
2535                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2536                                 rockchip,pins =
2537                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>;
2538                         };
2539                 };
2540
2541                 pwm2 {
2542                         pwm2_pin: pwm2-pin {
2543                                 rockchip,pins =
2544                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2545                         };
2546
2547                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2548                                 rockchip,pins =
2549                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
2550                         };
2551                 };
2552
2553                 pwm3a {
2554                         pwm3a_pin: pwm3a-pin {
2555                                 rockchip,pins =
2556                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2557                         };
2558                 };
2559
2560                 pwm3b {
2561                         pwm3b_pin: pwm3b-pin {
2562                                 rockchip,pins =
2563                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2564                         };
2565                 };
2566
2567                 hdmi {
2568                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2569                                 rockchip,pins =
2570                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2571                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2572                         };
2573
2574                         hdmi_cec: hdmi-cec {
2575                                 rockchip,pins =
2576                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2577                         };
2578                 };
2579
2580                 pcie {
2581                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2582                                 rockchip,pins =
2583                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2584                         };
2585
2586                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2587                                 rockchip,pins =
2588                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2589                         };
2590                 };
2591
2592         };
2593 };