arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PXs3 SoC
   3  *
   4  * Copyright (C) 2017 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 /memreserve/ 0x80000000 0x02000000;
  11
  12 / {
  13         compatible = "socionext,uniphier-pxs3";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&gic>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu-map {
  23                         cluster0 {
  24                                 core0 {
  25                                         cpu = <&cpu0>;
  26                                 };
  27                                 core1 {
  28                                         cpu = <&cpu1>;
  29                                 };
  30                                 core2 {
  31                                         cpu = <&cpu2>;
  32                                 };
  33                                 core3 {
  34                                         cpu = <&cpu3>;
  35                                 };
  36                         };
  37                 };
  38
  39                 cpu0: cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53", "arm,armv8";
  42                         reg = <0 0x000>;
  43                         clocks = <&sys_clk 33>;
  44                         enable-method = "psci";
  45                         operating-points-v2 = <&cluster0_opp>;
  46                 };
  47
  48                 cpu1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53", "arm,armv8";
  51                         reg = <0 0x001>;
  52                         clocks = <&sys_clk 33>;
  53                         enable-method = "psci";
  54                         operating-points-v2 = <&cluster0_opp>;
  55                 };
  56
  57                 cpu2: cpu@2 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53", "arm,armv8";
  60                         reg = <0 0x002>;
  61                         clocks = <&sys_clk 33>;
  62                         enable-method = "psci";
  63                         operating-points-v2 = <&cluster0_opp>;
  64                 };
  65
  66                 cpu3: cpu@3 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53", "arm,armv8";
  69                         reg = <0 0x003>;
  70                         clocks = <&sys_clk 33>;
  71                         enable-method = "psci";
  72                         operating-points-v2 = <&cluster0_opp>;
  73                 };
  74         };
  75
  76         cluster0_opp: opp_table {
  77                 compatible = "operating-points-v2";
  78                 opp-shared;
  79
  80                 opp-250000000 {
  81                         opp-hz = /bits/ 64 <250000000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-325000000 {
  85                         opp-hz = /bits/ 64 <325000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-500000000 {
  89                         opp-hz = /bits/ 64 <500000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-650000000 {
  93                         opp-hz = /bits/ 64 <650000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96                 opp-666667000 {
  97                         opp-hz = /bits/ 64 <666667000>;
  98                         clock-latency-ns = <300>;
  99                 };
 100                 opp-866667000 {
 101                         opp-hz = /bits/ 64 <866667000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-1000000000 {
 105                         opp-hz = /bits/ 64 <1000000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108                 opp-1300000000 {
 109                         opp-hz = /bits/ 64 <1300000000>;
 110                         clock-latency-ns = <300>;
 111                 };
 112         };
 113
 114         psci {
 115                 compatible = "arm,psci-1.0";
 116                 method = "smc";
 117         };
 118
 119         clocks {
 120                 refclk: ref {
 121                         compatible = "fixed-clock";
 122                         #clock-cells = <0>;
 123                         clock-frequency = <25000000>;
 124                 };
 125         };
 126
 127         timer {
 128                 compatible = "arm,armv8-timer";
 129                 interrupts = <1 13 4>,
 130                              <1 14 4>,
 131                              <1 11 4>,
 132                              <1 10 4>;
 133         };
 134
 135         soc@0 {
 136                 compatible = "simple-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges = <0 0 0 0xffffffff>;
 140
 141                 serial0: serial@54006800 {
 142                         compatible = "socionext,uniphier-uart";
 143                         status = "disabled";
 144                         reg = <0x54006800 0x40>;
 145                         interrupts = <0 33 4>;
 146                         pinctrl-names = "default";
 147                         pinctrl-0 = <&pinctrl_uart0>;
 148                         clocks = <&peri_clk 0>;
 149                 };
 150
 151                 serial1: serial@54006900 {
 152                         compatible = "socionext,uniphier-uart";
 153                         status = "disabled";
 154                         reg = <0x54006900 0x40>;
 155                         interrupts = <0 35 4>;
 156                         pinctrl-names = "default";
 157                         pinctrl-0 = <&pinctrl_uart1>;
 158                         clocks = <&peri_clk 1>;
 159                 };
 160
 161                 serial2: serial@54006a00 {
 162                         compatible = "socionext,uniphier-uart";
 163                         status = "disabled";
 164                         reg = <0x54006a00 0x40>;
 165                         interrupts = <0 37 4>;
 166                         pinctrl-names = "default";
 167                         pinctrl-0 = <&pinctrl_uart2>;
 168                         clocks = <&peri_clk 2>;
 169                 };
 170
 171                 serial3: serial@54006b00 {
 172                         compatible = "socionext,uniphier-uart";
 173                         status = "disabled";
 174                         reg = <0x54006b00 0x40>;
 175                         interrupts = <0 177 4>;
 176                         pinctrl-names = "default";
 177                         pinctrl-0 = <&pinctrl_uart3>;
 178                         clocks = <&peri_clk 3>;
 179                 };
 180
 181                 i2c0: i2c@58780000 {
 182                         compatible = "socionext,uniphier-fi2c";
 183                         status = "disabled";
 184                         reg = <0x58780000 0x80>;
 185                         #address-cells = <1>;
 186                         #size-cells = <0>;
 187                         interrupts = <0 41 4>;
 188                         pinctrl-names = "default";
 189                         pinctrl-0 = <&pinctrl_i2c0>;
 190                         clocks = <&peri_clk 4>;
 191                         clock-frequency = <100000>;
 192                 };
 193
 194                 i2c1: i2c@58781000 {
 195                         compatible = "socionext,uniphier-fi2c";
 196                         status = "disabled";
 197                         reg = <0x58781000 0x80>;
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200                         interrupts = <0 42 4>;
 201                         pinctrl-names = "default";
 202                         pinctrl-0 = <&pinctrl_i2c1>;
 203                         clocks = <&peri_clk 5>;
 204                         clock-frequency = <100000>;
 205                 };
 206
 207                 i2c2: i2c@58782000 {
 208                         compatible = "socionext,uniphier-fi2c";
 209                         status = "disabled";
 210                         reg = <0x58782000 0x80>;
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                         interrupts = <0 43 4>;
 214                         pinctrl-names = "default";
 215                         pinctrl-0 = <&pinctrl_i2c2>;
 216                         clocks = <&peri_clk 6>;
 217                         clock-frequency = <100000>;
 218                 };
 219
 220                 i2c3: i2c@58783000 {
 221                         compatible = "socionext,uniphier-fi2c";
 222                         status = "disabled";
 223                         reg = <0x58783000 0x80>;
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                         interrupts = <0 44 4>;
 227                         pinctrl-names = "default";
 228                         pinctrl-0 = <&pinctrl_i2c3>;
 229                         clocks = <&peri_clk 7>;
 230                         clock-frequency = <100000>;
 231                 };
 232
 233                 /* chip-internal connection for HDMI */
 234                 i2c6: i2c@58786000 {
 235                         compatible = "socionext,uniphier-fi2c";
 236                         reg = <0x58786000 0x80>;
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239                         interrupts = <0 26 4>;
 240                         clocks = <&peri_clk 10>;
 241                         clock-frequency = <400000>;
 242                 };
 243
 244                 system_bus: system-bus@58c00000 {
 245                         compatible = "socionext,uniphier-system-bus";
 246                         status = "disabled";
 247                         reg = <0x58c00000 0x400>;
 248                         #address-cells = <2>;
 249                         #size-cells = <1>;
 250                         pinctrl-names = "default";
 251                         pinctrl-0 = <&pinctrl_system_bus>;
 252                 };
 253
 254                 smpctrl@59801000 {
 255                         compatible = "socionext,uniphier-smpctrl";
 256                         reg = <0x59801000 0x400>;
 257                 };
 258
 259                 sdctrl@59810000 {
 260                         compatible = "socionext,uniphier-pxs3-sdctrl",
 261                                      "simple-mfd", "syscon";
 262                         reg = <0x59810000 0x400>;
 263
 264                         sd_clk: clock {
 265                                 compatible = "socionext,uniphier-pxs3-sd-clock";
 266                                 #clock-cells = <1>;
 267                         };
 268
 269                         sd_rst: reset {
 270                                 compatible = "socionext,uniphier-pxs3-sd-reset";
 271                                 #reset-cells = <1>;
 272                         };
 273                 };
 274
 275                 perictrl@59820000 {
 276                         compatible = "socionext,uniphier-pxs3-perictrl",
 277                                      "simple-mfd", "syscon";
 278                         reg = <0x59820000 0x200>;
 279
 280                         peri_clk: clock {
 281                                 compatible = "socionext,uniphier-pxs3-peri-clock";
 282                                 #clock-cells = <1>;
 283                         };
 284
 285                         peri_rst: reset {
 286                                 compatible = "socionext,uniphier-pxs3-peri-reset";
 287                                 #reset-cells = <1>;
 288                         };
 289                 };
 290
 291                 emmc: sdhc@5a000000 {
 292                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 293                         reg = <0x5a000000 0x400>;
 294                         interrupts = <0 78 4>;
 295                         pinctrl-names = "default";
 296                         pinctrl-0 = <&pinctrl_emmc>;
 297                         clocks = <&sys_clk 4>;
 298                         bus-width = <8>;
 299                         mmc-ddr-1_8v;
 300                         mmc-hs200-1_8v;
 301                         cdns,phy-input-delay-legacy = <4>;
 302                         cdns,phy-input-delay-mmc-highspeed = <2>;
 303                         cdns,phy-input-delay-mmc-ddr = <3>;
 304                         cdns,phy-dll-delay-sdclk = <21>;
 305                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 306                 };
 307
 308                 soc-glue@5f800000 {
 309                         compatible = "socionext,uniphier-pxs3-soc-glue",
 310                                      "simple-mfd", "syscon";
 311                         reg = <0x5f800000 0x2000>;
 312
 313                         pinctrl: pinctrl {
 314                                 compatible = "socionext,uniphier-pxs3-pinctrl";
 315                         };
 316                 };
 317
 318                 aidet: aidet@5fc20000 {
 319                         compatible = "socionext,uniphier-pxs3-aidet";
 320                         reg = <0x5fc20000 0x200>;
 321                         interrupt-controller;
 322                         #interrupt-cells = <2>;
 323                 };
 324
 325                 gic: interrupt-controller@5fe00000 {
 326                         compatible = "arm,gic-v3";
 327                         reg = <0x5fe00000 0x10000>,     /* GICD */
 328                               <0x5fe80000 0x80000>;     /* GICR */
 329                         interrupt-controller;
 330                         #interrupt-cells = <3>;
 331                         interrupts = <1 9 4>;
 332                 };
 333
 334                 sysctrl@61840000 {
 335                         compatible = "socionext,uniphier-pxs3-sysctrl",
 336                                      "simple-mfd", "syscon";
 337                         reg = <0x61840000 0x10000>;
 338
 339                         sys_clk: clock {
 340                                 compatible = "socionext,uniphier-pxs3-clock";
 341                                 #clock-cells = <1>;
 342                         };
 343
 344                         sys_rst: reset {
 345                                 compatible = "socionext,uniphier-pxs3-reset";
 346                                 #reset-cells = <1>;
 347                         };
 348
 349                         watchdog {
 350                                 compatible = "socionext,uniphier-wdt";
 351                         };
 352                 };
 353
 354                 nand: nand@68000000 {
 355                         compatible = "socionext,uniphier-denali-nand-v5b";
 356                         status = "disabled";
 357                         reg-names = "nand_data", "denali_reg";
 358                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 359                         interrupts = <0 65 4>;
 360                         pinctrl-names = "default";
 361                         pinctrl-0 = <&pinctrl_nand>;
 362                         clocks = <&sys_clk 2>;
 363                 };
 364         };
 365 };
 366
 367 #include "uniphier-pinctrl.dtsi"