2 * Device Tree Source for UniPhier PXs3 SoC
4 * Copyright (C) 2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-pxs3";
16 interrupt-parent = <&gic>;
41 compatible = "arm,cortex-a53", "arm,armv8";
43 clocks = <&sys_clk 33>;
44 enable-method = "psci";
45 operating-points-v2 = <&cluster0_opp>;
50 compatible = "arm,cortex-a53", "arm,armv8";
52 clocks = <&sys_clk 33>;
53 enable-method = "psci";
54 operating-points-v2 = <&cluster0_opp>;
59 compatible = "arm,cortex-a53", "arm,armv8";
61 clocks = <&sys_clk 33>;
62 enable-method = "psci";
63 operating-points-v2 = <&cluster0_opp>;
68 compatible = "arm,cortex-a53", "arm,armv8";
70 clocks = <&sys_clk 33>;
71 enable-method = "psci";
72 operating-points-v2 = <&cluster0_opp>;
76 cluster0_opp: opp_table {
77 compatible = "operating-points-v2";
81 opp-hz = /bits/ 64 <250000000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <325000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <500000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <650000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <666667000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <866667000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <1000000000>;
106 clock-latency-ns = <300>;
109 opp-hz = /bits/ 64 <1300000000>;
110 clock-latency-ns = <300>;
115 compatible = "arm,psci-1.0";
121 compatible = "fixed-clock";
123 clock-frequency = <25000000>;
128 compatible = "arm,armv8-timer";
129 interrupts = <1 13 4>,
136 compatible = "simple-bus";
137 #address-cells = <1>;
139 ranges = <0 0 0 0xffffffff>;
141 serial0: serial@54006800 {
142 compatible = "socionext,uniphier-uart";
144 reg = <0x54006800 0x40>;
145 interrupts = <0 33 4>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_uart0>;
148 clocks = <&peri_clk 0>;
151 serial1: serial@54006900 {
152 compatible = "socionext,uniphier-uart";
154 reg = <0x54006900 0x40>;
155 interrupts = <0 35 4>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_uart1>;
158 clocks = <&peri_clk 1>;
161 serial2: serial@54006a00 {
162 compatible = "socionext,uniphier-uart";
164 reg = <0x54006a00 0x40>;
165 interrupts = <0 37 4>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_uart2>;
168 clocks = <&peri_clk 2>;
171 serial3: serial@54006b00 {
172 compatible = "socionext,uniphier-uart";
174 reg = <0x54006b00 0x40>;
175 interrupts = <0 177 4>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_uart3>;
178 clocks = <&peri_clk 3>;
182 compatible = "socionext,uniphier-fi2c";
184 reg = <0x58780000 0x80>;
185 #address-cells = <1>;
187 interrupts = <0 41 4>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_i2c0>;
190 clocks = <&peri_clk 4>;
191 clock-frequency = <100000>;
195 compatible = "socionext,uniphier-fi2c";
197 reg = <0x58781000 0x80>;
198 #address-cells = <1>;
200 interrupts = <0 42 4>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c1>;
203 clocks = <&peri_clk 5>;
204 clock-frequency = <100000>;
208 compatible = "socionext,uniphier-fi2c";
210 reg = <0x58782000 0x80>;
211 #address-cells = <1>;
213 interrupts = <0 43 4>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_i2c2>;
216 clocks = <&peri_clk 6>;
217 clock-frequency = <100000>;
221 compatible = "socionext,uniphier-fi2c";
223 reg = <0x58783000 0x80>;
224 #address-cells = <1>;
226 interrupts = <0 44 4>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_i2c3>;
229 clocks = <&peri_clk 7>;
230 clock-frequency = <100000>;
233 /* chip-internal connection for HDMI */
235 compatible = "socionext,uniphier-fi2c";
236 reg = <0x58786000 0x80>;
237 #address-cells = <1>;
239 interrupts = <0 26 4>;
240 clocks = <&peri_clk 10>;
241 clock-frequency = <400000>;
244 system_bus: system-bus@58c00000 {
245 compatible = "socionext,uniphier-system-bus";
247 reg = <0x58c00000 0x400>;
248 #address-cells = <2>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_system_bus>;
255 compatible = "socionext,uniphier-smpctrl";
256 reg = <0x59801000 0x400>;
260 compatible = "socionext,uniphier-pxs3-sdctrl",
261 "simple-mfd", "syscon";
262 reg = <0x59810000 0x400>;
265 compatible = "socionext,uniphier-pxs3-sd-clock";
270 compatible = "socionext,uniphier-pxs3-sd-reset";
276 compatible = "socionext,uniphier-pxs3-perictrl",
277 "simple-mfd", "syscon";
278 reg = <0x59820000 0x200>;
281 compatible = "socionext,uniphier-pxs3-peri-clock";
286 compatible = "socionext,uniphier-pxs3-peri-reset";
291 emmc: sdhc@5a000000 {
292 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
293 reg = <0x5a000000 0x400>;
294 interrupts = <0 78 4>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_emmc>;
297 clocks = <&sys_clk 4>;
301 cdns,phy-input-delay-legacy = <4>;
302 cdns,phy-input-delay-mmc-highspeed = <2>;
303 cdns,phy-input-delay-mmc-ddr = <3>;
304 cdns,phy-dll-delay-sdclk = <21>;
305 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
309 compatible = "socionext,uniphier-pxs3-soc-glue",
310 "simple-mfd", "syscon";
311 reg = <0x5f800000 0x2000>;
314 compatible = "socionext,uniphier-pxs3-pinctrl";
318 aidet: aidet@5fc20000 {
319 compatible = "socionext,uniphier-pxs3-aidet";
320 reg = <0x5fc20000 0x200>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
325 gic: interrupt-controller@5fe00000 {
326 compatible = "arm,gic-v3";
327 reg = <0x5fe00000 0x10000>, /* GICD */
328 <0x5fe80000 0x80000>; /* GICR */
329 interrupt-controller;
330 #interrupt-cells = <3>;
331 interrupts = <1 9 4>;
335 compatible = "socionext,uniphier-pxs3-sysctrl",
336 "simple-mfd", "syscon";
337 reg = <0x61840000 0x10000>;
340 compatible = "socionext,uniphier-pxs3-clock";
345 compatible = "socionext,uniphier-pxs3-reset";
350 compatible = "socionext,uniphier-wdt";
354 nand: nand@68000000 {
355 compatible = "socionext,uniphier-denali-nand-v5b";
357 reg-names = "nand_data", "denali_reg";
358 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
359 interrupts = <0 65 4>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_nand>;
362 clocks = <&sys_clk 2>;
367 #include "uniphier-pinctrl.dtsi"