2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <asm/cputype.h>
21 #define CTR_L1IP_SHIFT 14
22 #define CTR_L1IP_MASK 3
23 #define CTR_DMINLINE_SHIFT 16
24 #define CTR_IMINLINE_SHIFT 0
25 #define CTR_IMINLINE_MASK 0xf
26 #define CTR_ERG_SHIFT 20
27 #define CTR_CWG_SHIFT 24
28 #define CTR_CWG_MASK 15
29 #define CTR_IDC_SHIFT 28
30 #define CTR_DIC_SHIFT 29
32 #define CTR_CACHE_MINLINE_MASK \
33 (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
35 #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
37 #define ICACHE_POLICY_VPIPT 0
38 #define ICACHE_POLICY_VIPT 2
39 #define ICACHE_POLICY_PIPT 3
41 #define L1_CACHE_SHIFT (6)
42 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
45 * Memory returned by kmalloc() may be used for DMA, so we must make
46 * sure that all such allocations are cache aligned. Otherwise,
47 * unrelated code may cause parts of the buffer to be read into the
48 * cache before the transfer is done, causing old data to be seen by
51 #define ARCH_DMA_MINALIGN (128)
55 #include <linux/bitops.h>
57 #define ICACHEF_ALIASING 0
58 #define ICACHEF_VPIPT 1
59 extern unsigned long __icache_flags;
62 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
63 * permitted in the I-cache.
65 static inline int icache_is_aliasing(void)
67 return test_bit(ICACHEF_ALIASING, &__icache_flags);
70 static inline int icache_is_vpipt(void)
72 return test_bit(ICACHEF_VPIPT, &__icache_flags);
75 static inline u32 cache_type_cwg(void)
77 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
80 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
82 static inline int cache_line_size(void)
84 u32 cwg = cache_type_cwg();
85 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
88 #endif /* __ASSEMBLY__ */