arch/arm64/include/asm/processor.h

   1 /*
   2  * Based on arch/arm/include/asm/processor.h
   3  *
   4  * Copyright (C) 1995-1999 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_PROCESSOR_H
  20 #define __ASM_PROCESSOR_H
  21
  22 #define TASK_SIZE_64            (UL(1) << VA_BITS)
  23
  24 #define KERNEL_DS       UL(-1)
  25 #define USER_DS         (TASK_SIZE_64 - 1)
  26
  27 #ifndef __ASSEMBLY__
  28
  29 /*
  30  * Default implementation of macro that returns current
  31  * instruction pointer ("program counter").
  32  */
  33 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  34
  35 #ifdef __KERNEL__
  36
  37 #include <linux/build_bug.h>
  38 #include <linux/cache.h>
  39 #include <linux/init.h>
  40 #include <linux/stddef.h>
  41 #include <linux/string.h>
  42
  43 #include <asm/alternative.h>
  44 #include <asm/cpufeature.h>
  45 #include <asm/hw_breakpoint.h>
  46 #include <asm/lse.h>
  47 #include <asm/pgtable-hwdef.h>
  48 #include <asm/ptrace.h>
  49 #include <asm/types.h>
  50
  51 /*
  52  * TASK_SIZE - the maximum size of a user space task.
  53  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
  54  */
  55 #ifdef CONFIG_COMPAT
  56 #ifdef CONFIG_ARM64_64K_PAGES
  57 /*
  58  * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
  59  * by the compat vectors page.
  60  */
  61 #define TASK_SIZE_32            UL(0x100000000)
  62 #else
  63 #define TASK_SIZE_32            (UL(0x100000000) - PAGE_SIZE)
  64 #endif /* CONFIG_ARM64_64K_PAGES */
  65 #define TASK_SIZE               (test_thread_flag(TIF_32BIT) ? \
  66                                 TASK_SIZE_32 : TASK_SIZE_64)
  67 #define TASK_SIZE_OF(tsk)       (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
  68                                 TASK_SIZE_32 : TASK_SIZE_64)
  69 #else
  70 #define TASK_SIZE               TASK_SIZE_64
  71 #endif /* CONFIG_COMPAT */
  72
  73 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 4))
  74
  75 #define STACK_TOP_MAX           TASK_SIZE_64
  76 #ifdef CONFIG_COMPAT
  77 #define AARCH32_VECTORS_BASE    0xffff0000
  78 #define STACK_TOP               (test_thread_flag(TIF_32BIT) ? \
  79                                 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
  80 #else
  81 #define STACK_TOP               STACK_TOP_MAX
  82 #endif /* CONFIG_COMPAT */
  83
  84 extern phys_addr_t arm64_dma_phys_limit;
  85 #define ARCH_LOW_ADDRESS_LIMIT  (arm64_dma_phys_limit - 1)
  86
  87 struct debug_info {
  88 #ifdef CONFIG_HAVE_HW_BREAKPOINT
  89         /* Have we suspended stepping by a debugger? */
  90         int                     suspended_step;
  91         /* Allow breakpoints and watchpoints to be disabled for this thread. */
  92         int                     bps_disabled;
  93         int                     wps_disabled;
  94         /* Hardware breakpoints pinned to this task. */
  95         struct perf_event       *hbp_break[ARM_MAX_BRP];
  96         struct perf_event       *hbp_watch[ARM_MAX_WRP];
  97 #endif
  98 };
  99
 100 struct cpu_context {
 101         unsigned long x19;
 102         unsigned long x20;
 103         unsigned long x21;
 104         unsigned long x22;
 105         unsigned long x23;
 106         unsigned long x24;
 107         unsigned long x25;
 108         unsigned long x26;
 109         unsigned long x27;
 110         unsigned long x28;
 111         unsigned long fp;
 112         unsigned long sp;
 113         unsigned long pc;
 114 };
 115
 116 struct thread_struct {
 117         struct cpu_context      cpu_context;    /* cpu context */
 118
 119         /*
 120          * Whitelisted fields for hardened usercopy:
 121          * Maintainers must ensure manually that this contains no
 122          * implicit padding.
 123          */
 124         struct {
 125                 unsigned long   tp_value;       /* TLS register */
 126                 unsigned long   tp2_value;
 127                 struct user_fpsimd_state fpsimd_state;
 128         } uw;
 129
 130         unsigned int            fpsimd_cpu;
 131         void                    *sve_state;     /* SVE registers, if any */
 132         unsigned int            sve_vl;         /* SVE vector length */
 133         unsigned int            sve_vl_onexec;  /* SVE vl after next exec */
 134         unsigned long           fault_address;  /* fault info */
 135         unsigned long           fault_code;     /* ESR_EL1 value */
 136         struct debug_info       debug;          /* debugging */
 137 };
 138
 139 static inline void arch_thread_struct_whitelist(unsigned long *offset,
 140                                                 unsigned long *size)
 141 {
 142         /* Verify that there is no padding among the whitelisted fields: */
 143         BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
 144                      sizeof_field(struct thread_struct, uw.tp_value) +
 145                      sizeof_field(struct thread_struct, uw.tp2_value) +
 146                      sizeof_field(struct thread_struct, uw.fpsimd_state));
 147
 148         *offset = offsetof(struct thread_struct, uw);
 149         *size = sizeof_field(struct thread_struct, uw);
 150 }
 151
 152 #ifdef CONFIG_COMPAT
 153 #define task_user_tls(t)                                                \
 154 ({                                                                      \
 155         unsigned long *__tls;                                           \
 156         if (is_compat_thread(task_thread_info(t)))                      \
 157                 __tls = &(t)->thread.uw.tp2_value;                      \
 158         else                                                            \
 159                 __tls = &(t)->thread.uw.tp_value;                       \
 160         __tls;                                                          \
 161  })
 162 #else
 163 #define task_user_tls(t)        (&(t)->thread.uw.tp_value)
 164 #endif
 165
 166 /* Sync TPIDR_EL0 back to thread_struct for current */
 167 void tls_preserve_current_state(void);
 168
 169 #define INIT_THREAD {                           \
 170         .fpsimd_cpu = NR_CPUS,                  \
 171 }
 172
 173 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
 174 {
 175         s32 previous_syscall = regs->syscallno;
 176         memset(regs, 0, sizeof(*regs));
 177         regs->syscallno = previous_syscall;
 178         regs->pc = pc;
 179 }
 180
 181 static inline void set_ssbs_bit(struct pt_regs *regs)
 182 {
 183         regs->pstate |= PSR_SSBS_BIT;
 184 }
 185
 186 static inline void set_compat_ssbs_bit(struct pt_regs *regs)
 187 {
 188         regs->pstate |= PSR_AA32_SSBS_BIT;
 189 }
 190
 191 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
 192                                 unsigned long sp)
 193 {
 194         start_thread_common(regs, pc);
 195         regs->pstate = PSR_MODE_EL0t;
 196
 197         if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
 198                 set_ssbs_bit(regs);
 199
 200         regs->sp = sp;
 201 }
 202
 203 #ifdef CONFIG_COMPAT
 204 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
 205                                        unsigned long sp)
 206 {
 207         start_thread_common(regs, pc);
 208         regs->pstate = PSR_AA32_MODE_USR;
 209         if (pc & 1)
 210                 regs->pstate |= PSR_AA32_T_BIT;
 211
 212 #ifdef __AARCH64EB__
 213         regs->pstate |= PSR_AA32_E_BIT;
 214 #endif
 215
 216         if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
 217                 set_compat_ssbs_bit(regs);
 218
 219         regs->compat_sp = sp;
 220 }
 221 #endif
 222
 223 /* Forward declaration, a strange C thing */
 224 struct task_struct;
 225
 226 /* Free all resources held by a thread. */
 227 extern void release_thread(struct task_struct *);
 228
 229 unsigned long get_wchan(struct task_struct *p);
 230
 231 static inline void cpu_relax(void)
 232 {
 233         asm volatile("yield" ::: "memory");
 234 }
 235
 236 /* Thread switching */
 237 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
 238                                          struct task_struct *next);
 239
 240 #define task_pt_regs(p) \
 241         ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
 242
 243 #define KSTK_EIP(tsk)   ((unsigned long)task_pt_regs(tsk)->pc)
 244 #define KSTK_ESP(tsk)   user_stack_pointer(task_pt_regs(tsk))
 245
 246 /*
 247  * Prefetching support
 248  */
 249 #define ARCH_HAS_PREFETCH
 250 static inline void prefetch(const void *ptr)
 251 {
 252         asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
 253 }
 254
 255 #define ARCH_HAS_PREFETCHW
 256 static inline void prefetchw(const void *ptr)
 257 {
 258         asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
 259 }
 260
 261 #define ARCH_HAS_SPINLOCK_PREFETCH
 262 static inline void spin_lock_prefetch(const void *ptr)
 263 {
 264         asm volatile(ARM64_LSE_ATOMIC_INSN(
 265                      "prfm pstl1strm, %a0",
 266                      "nop") : : "p" (ptr));
 267 }
 268
 269 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 270
 271 #endif
 272
 273 void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused);
 274 void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused);
 275 void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused);
 276
 277 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
 278 extern void __init minsigstksz_setup(void);
 279
 280 /*
 281  * Not at the top of the file due to a direct #include cycle between
 282  * <asm/fpsimd.h> and <asm/processor.h>.  Deferring this #include
 283  * ensures that contents of processor.h are visible to fpsimd.h even if
 284  * processor.h is included first.
 285  *
 286  * These prctl helpers are the only things in this file that require
 287  * fpsimd.h.  The core code expects them to be in this header.
 288  */
 289 #include <asm/fpsimd.h>
 290
 291 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
 292 #define SVE_SET_VL(arg) sve_set_current_vl(arg)
 293 #define SVE_GET_VL()    sve_get_current_vl()
 294
 295 /*
 296  * For CONFIG_GCC_PLUGIN_STACKLEAK
 297  *
 298  * These need to be macros because otherwise we get stuck in a nightmare
 299  * of header definitions for the use of task_stack_page.
 300  */
 301
 302 #define current_top_of_stack()                                                  \
 303 ({                                                                              \
 304         struct stack_info _info;                                                \
 305         BUG_ON(!on_accessible_stack(current, current_stack_pointer, &_info));   \
 306         _info.high;                                                             \
 307 })
 308 #define on_thread_stack()       (on_task_stack(current, current_stack_pointer, NULL))
 309
 310 #endif /* __ASSEMBLY__ */
 311 #endif /* __ASM_PROCESSOR_H */