arch/arm64/kernel/armv8_deprecated.c

   1 /*
   2  *  Copyright (C) 2014 ARM Limited
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/cpu.h>
  10 #include <linux/init.h>
  11 #include <linux/list.h>
  12 #include <linux/perf_event.h>
  13 #include <linux/sched.h>
  14 #include <linux/slab.h>
  15 #include <linux/sysctl.h>
  16
  17 #include <asm/alternative.h>
  18 #include <asm/cpufeature.h>
  19 #include <asm/insn.h>
  20 #include <asm/opcodes.h>
  21 #include <asm/sysreg.h>
  22 #include <asm/system_misc.h>
  23 #include <asm/traps.h>
  24 #include <asm/uaccess.h>
  25 #include <asm/cpufeature.h>
  26
  27 #define CREATE_TRACE_POINTS
  28 #include "trace-events-emulation.h"
  29
  30 /*
  31  * The runtime support for deprecated instruction support can be in one of
  32  * following three states -
  33  *
  34  * 0 = undef
  35  * 1 = emulate (software emulation)
  36  * 2 = hw (supported in hardware)
  37  */
  38 enum insn_emulation_mode {
  39         INSN_UNDEF,
  40         INSN_EMULATE,
  41         INSN_HW,
  42 };
  43
  44 enum legacy_insn_status {
  45         INSN_DEPRECATED,
  46         INSN_OBSOLETE,
  47 };
  48
  49 struct insn_emulation_ops {
  50         const char              *name;
  51         enum legacy_insn_status status;
  52         struct undef_hook       *hooks;
  53         int                     (*set_hw_mode)(bool enable);
  54 };
  55
  56 struct insn_emulation {
  57         struct list_head node;
  58         struct insn_emulation_ops *ops;
  59         int current_mode;
  60         int min;
  61         int max;
  62 };
  63
  64 static LIST_HEAD(insn_emulation);
  65 static int nr_insn_emulated;
  66 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
  67
  68 static void register_emulation_hooks(struct insn_emulation_ops *ops)
  69 {
  70         struct undef_hook *hook;
  71
  72         BUG_ON(!ops->hooks);
  73
  74         for (hook = ops->hooks; hook->instr_mask; hook++)
  75                 register_undef_hook(hook);
  76
  77         pr_notice("Registered %s emulation handler\n", ops->name);
  78 }
  79
  80 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
  81 {
  82         struct undef_hook *hook;
  83
  84         BUG_ON(!ops->hooks);
  85
  86         for (hook = ops->hooks; hook->instr_mask; hook++)
  87                 unregister_undef_hook(hook);
  88
  89         pr_notice("Removed %s emulation handler\n", ops->name);
  90 }
  91
  92 static void enable_insn_hw_mode(void *data)
  93 {
  94         struct insn_emulation *insn = (struct insn_emulation *)data;
  95         if (insn->ops->set_hw_mode)
  96                 insn->ops->set_hw_mode(true);
  97 }
  98
  99 static void disable_insn_hw_mode(void *data)
 100 {
 101         struct insn_emulation *insn = (struct insn_emulation *)data;
 102         if (insn->ops->set_hw_mode)
 103                 insn->ops->set_hw_mode(false);
 104 }
 105
 106 /* Run set_hw_mode(mode) on all active CPUs */
 107 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
 108 {
 109         if (!insn->ops->set_hw_mode)
 110                 return -EINVAL;
 111         if (enable)
 112                 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
 113         else
 114                 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
 115         return 0;
 116 }
 117
 118 /*
 119  * Run set_hw_mode for all insns on a starting CPU.
 120  * Returns:
 121  *  0           - If all the hooks ran successfully.
 122  * -EINVAL      - At least one hook is not supported by the CPU.
 123  */
 124 static int run_all_insn_set_hw_mode(unsigned long cpu)
 125 {
 126         int rc = 0;
 127         unsigned long flags;
 128         struct insn_emulation *insn;
 129
 130         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 131         list_for_each_entry(insn, &insn_emulation, node) {
 132                 bool enable = (insn->current_mode == INSN_HW);
 133                 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
 134                         pr_warn("CPU[%ld] cannot support the emulation of %s",
 135                                 cpu, insn->ops->name);
 136                         rc = -EINVAL;
 137                 }
 138         }
 139         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 140         return rc;
 141 }
 142
 143 static int update_insn_emulation_mode(struct insn_emulation *insn,
 144                                        enum insn_emulation_mode prev)
 145 {
 146         int ret = 0;
 147
 148         switch (prev) {
 149         case INSN_UNDEF: /* Nothing to be done */
 150                 break;
 151         case INSN_EMULATE:
 152                 remove_emulation_hooks(insn->ops);
 153                 break;
 154         case INSN_HW:
 155                 if (!run_all_cpu_set_hw_mode(insn, false))
 156                         pr_notice("Disabled %s support\n", insn->ops->name);
 157                 break;
 158         }
 159
 160         switch (insn->current_mode) {
 161         case INSN_UNDEF:
 162                 break;
 163         case INSN_EMULATE:
 164                 register_emulation_hooks(insn->ops);
 165                 break;
 166         case INSN_HW:
 167                 ret = run_all_cpu_set_hw_mode(insn, true);
 168                 if (!ret)
 169                         pr_notice("Enabled %s support\n", insn->ops->name);
 170                 break;
 171         }
 172
 173         return ret;
 174 }
 175
 176 static void register_insn_emulation(struct insn_emulation_ops *ops)
 177 {
 178         unsigned long flags;
 179         struct insn_emulation *insn;
 180
 181         insn = kzalloc(sizeof(*insn), GFP_KERNEL);
 182         insn->ops = ops;
 183         insn->min = INSN_UNDEF;
 184
 185         switch (ops->status) {
 186         case INSN_DEPRECATED:
 187                 insn->current_mode = INSN_EMULATE;
 188                 /* Disable the HW mode if it was turned on at early boot time */
 189                 run_all_cpu_set_hw_mode(insn, false);
 190                 insn->max = INSN_HW;
 191                 break;
 192         case INSN_OBSOLETE:
 193                 insn->current_mode = INSN_UNDEF;
 194                 insn->max = INSN_EMULATE;
 195                 break;
 196         }
 197
 198         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 199         list_add(&insn->node, &insn_emulation);
 200         nr_insn_emulated++;
 201         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 202
 203         /* Register any handlers if required */
 204         update_insn_emulation_mode(insn, INSN_UNDEF);
 205 }
 206
 207 static int emulation_proc_handler(struct ctl_table *table, int write,
 208                                   void __user *buffer, size_t *lenp,
 209                                   loff_t *ppos)
 210 {
 211         int ret = 0;
 212         struct insn_emulation *insn = (struct insn_emulation *) table->data;
 213         enum insn_emulation_mode prev_mode = insn->current_mode;
 214
 215         table->data = &insn->current_mode;
 216         ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
 217
 218         if (ret || !write || prev_mode == insn->current_mode)
 219                 goto ret;
 220
 221         ret = update_insn_emulation_mode(insn, prev_mode);
 222         if (ret) {
 223                 /* Mode change failed, revert to previous mode. */
 224                 insn->current_mode = prev_mode;
 225                 update_insn_emulation_mode(insn, INSN_UNDEF);
 226         }
 227 ret:
 228         table->data = insn;
 229         return ret;
 230 }
 231
 232 static struct ctl_table ctl_abi[] = {
 233         {
 234                 .procname = "abi",
 235                 .mode = 0555,
 236         },
 237         { }
 238 };
 239
 240 static void register_insn_emulation_sysctl(struct ctl_table *table)
 241 {
 242         unsigned long flags;
 243         int i = 0;
 244         struct insn_emulation *insn;
 245         struct ctl_table *insns_sysctl, *sysctl;
 246
 247         insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
 248                               GFP_KERNEL);
 249
 250         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 251         list_for_each_entry(insn, &insn_emulation, node) {
 252                 sysctl = &insns_sysctl[i];
 253
 254                 sysctl->mode = 0644;
 255                 sysctl->maxlen = sizeof(int);
 256
 257                 sysctl->procname = insn->ops->name;
 258                 sysctl->data = insn;
 259                 sysctl->extra1 = &insn->min;
 260                 sysctl->extra2 = &insn->max;
 261                 sysctl->proc_handler = emulation_proc_handler;
 262                 i++;
 263         }
 264         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 265
 266         table->child = insns_sysctl;
 267         register_sysctl_table(table);
 268 }
 269
 270 /*
 271  *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
 272  *  store-exclusive.
 273  *
 274  *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
 275  *  Where: Rt  = destination
 276  *         Rt2 = source
 277  *         Rn  = address
 278  */
 279
 280 /*
 281  * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
 282  */
 283 #define __user_swpX_asm(data, addr, res, temp, B)               \
 284         __asm__ __volatile__(                                   \
 285         ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN,    \
 286                     CONFIG_ARM64_PAN)                           \
 287         "0:     ldxr"B"         %w2, [%3]\n"                    \
 288         "1:     stxr"B"         %w0, %w1, [%3]\n"               \
 289         "       cbz             %w0, 2f\n"                      \
 290         "       mov             %w0, %w4\n"                     \
 291         "       b               3f\n"                           \
 292         "2:\n"                                                  \
 293         "       mov             %w1, %w2\n"                     \
 294         "3:\n"                                                  \
 295         "       .pushsection     .fixup,\"ax\"\n"               \
 296         "       .align          2\n"                            \
 297         "4:     mov             %w0, %w5\n"                     \
 298         "       b               3b\n"                           \
 299         "       .popsection"                                    \
 300         "       .pushsection     __ex_table,\"a\"\n"            \
 301         "       .align          3\n"                            \
 302         "       .quad           0b, 4b\n"                       \
 303         "       .quad           1b, 4b\n"                       \
 304         "       .popsection\n"                                  \
 305         ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,    \
 306                 CONFIG_ARM64_PAN)                               \
 307         : "=&r" (res), "+r" (data), "=&r" (temp)                \
 308         : "r" ((unsigned long)addr), "i" (-EAGAIN),             \
 309           "i" (-EFAULT)                                         \
 310         : "memory")
 311
 312 #define __user_swp_asm(data, addr, res, temp) \
 313         __user_swpX_asm(data, addr, res, temp, "")
 314 #define __user_swpb_asm(data, addr, res, temp) \
 315         __user_swpX_asm(data, addr, res, temp, "b")
 316
 317 /*
 318  * Bit 22 of the instruction encoding distinguishes between
 319  * the SWP and SWPB variants (bit set means SWPB).
 320  */
 321 #define TYPE_SWPB (1 << 22)
 322
 323 /*
 324  * Set up process info to signal segmentation fault - called on access error.
 325  */
 326 static void set_segfault(struct pt_regs *regs, unsigned long addr)
 327 {
 328         siginfo_t info;
 329
 330         down_read(&current->mm->mmap_sem);
 331         if (find_vma(current->mm, addr) == NULL)
 332                 info.si_code = SEGV_MAPERR;
 333         else
 334                 info.si_code = SEGV_ACCERR;
 335         up_read(&current->mm->mmap_sem);
 336
 337         info.si_signo = SIGSEGV;
 338         info.si_errno = 0;
 339         info.si_addr  = (void *) instruction_pointer(regs);
 340
 341         pr_debug("SWP{B} emulation: access caused memory abort!\n");
 342         arm64_notify_die("Illegal memory access", regs, &info, 0);
 343 }
 344
 345 static int emulate_swpX(unsigned int address, unsigned int *data,
 346                         unsigned int type)
 347 {
 348         unsigned int res = 0;
 349
 350         if ((type != TYPE_SWPB) && (address & 0x3)) {
 351                 /* SWP to unaligned address not permitted */
 352                 pr_debug("SWP instruction on unaligned pointer!\n");
 353                 return -EFAULT;
 354         }
 355
 356         while (1) {
 357                 unsigned long temp;
 358
 359                 if (type == TYPE_SWPB)
 360                         __user_swpb_asm(*data, address, res, temp);
 361                 else
 362                         __user_swp_asm(*data, address, res, temp);
 363
 364                 if (likely(res != -EAGAIN) || signal_pending(current))
 365                         break;
 366
 367                 cond_resched();
 368         }
 369
 370         return res;
 371 }
 372
 373 /*
 374  * swp_handler logs the id of calling process, dissects the instruction, sanity
 375  * checks the memory location, calls emulate_swpX for the actual operation and
 376  * deals with fixup/error handling before returning
 377  */
 378 static int swp_handler(struct pt_regs *regs, u32 instr)
 379 {
 380         u32 destreg, data, type, address = 0;
 381         int rn, rt2, res = 0;
 382
 383         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 384
 385         type = instr & TYPE_SWPB;
 386
 387         switch (arm_check_condition(instr, regs->pstate)) {
 388         case ARM_OPCODE_CONDTEST_PASS:
 389                 break;
 390         case ARM_OPCODE_CONDTEST_FAIL:
 391                 /* Condition failed - return to next instruction */
 392                 goto ret;
 393         case ARM_OPCODE_CONDTEST_UNCOND:
 394                 /* If unconditional encoding - not a SWP, undef */
 395                 return -EFAULT;
 396         default:
 397                 return -EINVAL;
 398         }
 399
 400         rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
 401         rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
 402
 403         address = (u32)regs->user_regs.regs[rn];
 404         data    = (u32)regs->user_regs.regs[rt2];
 405         destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
 406
 407         pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
 408                 rn, address, destreg,
 409                 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
 410
 411         /* Check access in reasonable access range for both SWP and SWPB */
 412         if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
 413                 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
 414                         address);
 415                 goto fault;
 416         }
 417
 418         res = emulate_swpX(address, &data, type);
 419         if (res == -EFAULT)
 420                 goto fault;
 421         else if (res == 0)
 422                 regs->user_regs.regs[destreg] = data;
 423
 424 ret:
 425         if (type == TYPE_SWPB)
 426                 trace_instruction_emulation("swpb", regs->pc);
 427         else
 428                 trace_instruction_emulation("swp", regs->pc);
 429
 430         pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
 431                         current->comm, (unsigned long)current->pid, regs->pc);
 432
 433         regs->pc += 4;
 434         return 0;
 435
 436 fault:
 437         set_segfault(regs, address);
 438
 439         return 0;
 440 }
 441
 442 /*
 443  * Only emulate SWP/SWPB executed in ARM state/User mode.
 444  * The kernel must be SWP free and SWP{B} does not exist in Thumb.
 445  */
 446 static struct undef_hook swp_hooks[] = {
 447         {
 448                 .instr_mask     = 0x0fb00ff0,
 449                 .instr_val      = 0x01000090,
 450                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 451                 .pstate_val     = COMPAT_PSR_MODE_USR,
 452                 .fn             = swp_handler
 453         },
 454         { }
 455 };
 456
 457 static struct insn_emulation_ops swp_ops = {
 458         .name = "swp",
 459         .status = INSN_OBSOLETE,
 460         .hooks = swp_hooks,
 461         .set_hw_mode = NULL,
 462 };
 463
 464 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
 465 {
 466         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 467
 468         switch (arm_check_condition(instr, regs->pstate)) {
 469         case ARM_OPCODE_CONDTEST_PASS:
 470                 break;
 471         case ARM_OPCODE_CONDTEST_FAIL:
 472                 /* Condition failed - return to next instruction */
 473                 goto ret;
 474         case ARM_OPCODE_CONDTEST_UNCOND:
 475                 /* If unconditional encoding - not a barrier instruction */
 476                 return -EFAULT;
 477         default:
 478                 return -EINVAL;
 479         }
 480
 481         switch (aarch32_insn_mcr_extract_crm(instr)) {
 482         case 10:
 483                 /*
 484                  * dmb - mcr p15, 0, Rt, c7, c10, 5
 485                  * dsb - mcr p15, 0, Rt, c7, c10, 4
 486                  */
 487                 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
 488                         dmb(sy);
 489                         trace_instruction_emulation(
 490                                 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
 491                 } else {
 492                         dsb(sy);
 493                         trace_instruction_emulation(
 494                                 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
 495                 }
 496                 break;
 497         case 5:
 498                 /*
 499                  * isb - mcr p15, 0, Rt, c7, c5, 4
 500                  *
 501                  * Taking an exception or returning from one acts as an
 502                  * instruction barrier. So no explicit barrier needed here.
 503                  */
 504                 trace_instruction_emulation(
 505                         "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
 506                 break;
 507         }
 508
 509 ret:
 510         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
 511                         current->comm, (unsigned long)current->pid, regs->pc);
 512
 513         regs->pc += 4;
 514         return 0;
 515 }
 516
 517 static int cp15_barrier_set_hw_mode(bool enable)
 518 {
 519         if (enable)
 520                 config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
 521         else
 522                 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
 523         return 0;
 524 }
 525
 526 static struct undef_hook cp15_barrier_hooks[] = {
 527         {
 528                 .instr_mask     = 0x0fff0fdf,
 529                 .instr_val      = 0x0e070f9a,
 530                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 531                 .pstate_val     = COMPAT_PSR_MODE_USR,
 532                 .fn             = cp15barrier_handler,
 533         },
 534         {
 535                 .instr_mask     = 0x0fff0fff,
 536                 .instr_val      = 0x0e070f95,
 537                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 538                 .pstate_val     = COMPAT_PSR_MODE_USR,
 539                 .fn             = cp15barrier_handler,
 540         },
 541         { }
 542 };
 543
 544 static struct insn_emulation_ops cp15_barrier_ops = {
 545         .name = "cp15_barrier",
 546         .status = INSN_DEPRECATED,
 547         .hooks = cp15_barrier_hooks,
 548         .set_hw_mode = cp15_barrier_set_hw_mode,
 549 };
 550
 551 static int setend_set_hw_mode(bool enable)
 552 {
 553         if (!cpu_supports_mixed_endian_el0())
 554                 return -EINVAL;
 555
 556         if (enable)
 557                 config_sctlr_el1(SCTLR_EL1_SED, 0);
 558         else
 559                 config_sctlr_el1(0, SCTLR_EL1_SED);
 560         return 0;
 561 }
 562
 563 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
 564 {
 565         char *insn;
 566
 567         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 568
 569         if (big_endian) {
 570                 insn = "setend be";
 571                 regs->pstate |= COMPAT_PSR_E_BIT;
 572         } else {
 573                 insn = "setend le";
 574                 regs->pstate &= ~COMPAT_PSR_E_BIT;
 575         }
 576
 577         trace_instruction_emulation(insn, regs->pc);
 578         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
 579                         current->comm, (unsigned long)current->pid, regs->pc);
 580
 581         return 0;
 582 }
 583
 584 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
 585 {
 586         int rc = compat_setend_handler(regs, (instr >> 9) & 1);
 587         regs->pc += 4;
 588         return rc;
 589 }
 590
 591 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
 592 {
 593         int rc = compat_setend_handler(regs, (instr >> 3) & 1);
 594         regs->pc += 2;
 595         return rc;
 596 }
 597
 598 static struct undef_hook setend_hooks[] = {
 599         {
 600                 .instr_mask     = 0xfffffdff,
 601                 .instr_val      = 0xf1010000,
 602                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 603                 .pstate_val     = COMPAT_PSR_MODE_USR,
 604                 .fn             = a32_setend_handler,
 605         },
 606         {
 607                 /* Thumb mode */
 608                 .instr_mask     = 0xfffffff7,
 609                 .instr_val      = 0x0000b650,
 610                 .pstate_mask    = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
 611                 .pstate_val     = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
 612                 .fn             = t16_setend_handler,
 613         },
 614         {}
 615 };
 616
 617 static struct insn_emulation_ops setend_ops = {
 618         .name = "setend",
 619         .status = INSN_DEPRECATED,
 620         .hooks = setend_hooks,
 621         .set_hw_mode = setend_set_hw_mode,
 622 };
 623
 624 static int insn_cpu_hotplug_notify(struct notifier_block *b,
 625                               unsigned long action, void *hcpu)
 626 {
 627         int rc = 0;
 628         if ((action & ~CPU_TASKS_FROZEN) == CPU_STARTING)
 629                 rc = run_all_insn_set_hw_mode((unsigned long)hcpu);
 630
 631         return notifier_from_errno(rc);
 632 }
 633
 634 static struct notifier_block insn_cpu_hotplug_notifier = {
 635         .notifier_call = insn_cpu_hotplug_notify,
 636 };
 637
 638 /*
 639  * Invoked as late_initcall, since not needed before init spawned.
 640  */
 641 static int __init armv8_deprecated_init(void)
 642 {
 643         if (IS_ENABLED(CONFIG_SWP_EMULATION))
 644                 register_insn_emulation(&swp_ops);
 645
 646         if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
 647                 register_insn_emulation(&cp15_barrier_ops);
 648
 649         if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
 650                 if(system_supports_mixed_endian_el0())
 651                         register_insn_emulation(&setend_ops);
 652                 else
 653                         pr_info("setend instruction emulation is not supported on the system");
 654         }
 655
 656         register_cpu_notifier(&insn_cpu_hotplug_notifier);
 657         register_insn_emulation_sysctl(ctl_abi);
 658
 659         return 0;
 660 }
 661
 662 late_initcall(armv8_deprecated_init);