arch/arm64/kernel/armv8_deprecated.c

   1 /*
   2  *  Copyright (C) 2014 ARM Limited
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/cpu.h>
  10 #include <linux/init.h>
  11 #include <linux/list.h>
  12 #include <linux/perf_event.h>
  13 #include <linux/sched.h>
  14 #include <linux/slab.h>
  15 #include <linux/sysctl.h>
  16 #include <linux/uaccess.h>
  17
  18 #include <asm/cpufeature.h>
  19 #include <asm/insn.h>
  20 #include <asm/sysreg.h>
  21 #include <asm/system_misc.h>
  22 #include <asm/traps.h>
  23 #include <asm/kprobes.h>
  24
  25 #define CREATE_TRACE_POINTS
  26 #include "trace-events-emulation.h"
  27
  28 /*
  29  * The runtime support for deprecated instruction support can be in one of
  30  * following three states -
  31  *
  32  * 0 = undef
  33  * 1 = emulate (software emulation)
  34  * 2 = hw (supported in hardware)
  35  */
  36 enum insn_emulation_mode {
  37         INSN_UNDEF,
  38         INSN_EMULATE,
  39         INSN_HW,
  40 };
  41
  42 enum legacy_insn_status {
  43         INSN_DEPRECATED,
  44         INSN_OBSOLETE,
  45 };
  46
  47 struct insn_emulation_ops {
  48         const char              *name;
  49         enum legacy_insn_status status;
  50         struct undef_hook       *hooks;
  51         int                     (*set_hw_mode)(bool enable);
  52 };
  53
  54 struct insn_emulation {
  55         struct list_head node;
  56         struct insn_emulation_ops *ops;
  57         int current_mode;
  58         int min;
  59         int max;
  60 };
  61
  62 static LIST_HEAD(insn_emulation);
  63 static int nr_insn_emulated __initdata;
  64 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
  65 static DEFINE_MUTEX(insn_emulation_mutex);
  66
  67 static void register_emulation_hooks(struct insn_emulation_ops *ops)
  68 {
  69         struct undef_hook *hook;
  70
  71         BUG_ON(!ops->hooks);
  72
  73         for (hook = ops->hooks; hook->instr_mask; hook++)
  74                 register_undef_hook(hook);
  75
  76         pr_notice("Registered %s emulation handler\n", ops->name);
  77 }
  78
  79 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
  80 {
  81         struct undef_hook *hook;
  82
  83         BUG_ON(!ops->hooks);
  84
  85         for (hook = ops->hooks; hook->instr_mask; hook++)
  86                 unregister_undef_hook(hook);
  87
  88         pr_notice("Removed %s emulation handler\n", ops->name);
  89 }
  90
  91 static void enable_insn_hw_mode(void *data)
  92 {
  93         struct insn_emulation *insn = (struct insn_emulation *)data;
  94         if (insn->ops->set_hw_mode)
  95                 insn->ops->set_hw_mode(true);
  96 }
  97
  98 static void disable_insn_hw_mode(void *data)
  99 {
 100         struct insn_emulation *insn = (struct insn_emulation *)data;
 101         if (insn->ops->set_hw_mode)
 102                 insn->ops->set_hw_mode(false);
 103 }
 104
 105 /* Run set_hw_mode(mode) on all active CPUs */
 106 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
 107 {
 108         if (!insn->ops->set_hw_mode)
 109                 return -EINVAL;
 110         if (enable)
 111                 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
 112         else
 113                 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
 114         return 0;
 115 }
 116
 117 /*
 118  * Run set_hw_mode for all insns on a starting CPU.
 119  * Returns:
 120  *  0           - If all the hooks ran successfully.
 121  * -EINVAL      - At least one hook is not supported by the CPU.
 122  */
 123 static int run_all_insn_set_hw_mode(unsigned int cpu)
 124 {
 125         int rc = 0;
 126         unsigned long flags;
 127         struct insn_emulation *insn;
 128
 129         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 130         list_for_each_entry(insn, &insn_emulation, node) {
 131                 bool enable = (insn->current_mode == INSN_HW);
 132                 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
 133                         pr_warn("CPU[%u] cannot support the emulation of %s",
 134                                 cpu, insn->ops->name);
 135                         rc = -EINVAL;
 136                 }
 137         }
 138         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 139         return rc;
 140 }
 141
 142 static int update_insn_emulation_mode(struct insn_emulation *insn,
 143                                        enum insn_emulation_mode prev)
 144 {
 145         int ret = 0;
 146
 147         switch (prev) {
 148         case INSN_UNDEF: /* Nothing to be done */
 149                 break;
 150         case INSN_EMULATE:
 151                 remove_emulation_hooks(insn->ops);
 152                 break;
 153         case INSN_HW:
 154                 if (!run_all_cpu_set_hw_mode(insn, false))
 155                         pr_notice("Disabled %s support\n", insn->ops->name);
 156                 break;
 157         }
 158
 159         switch (insn->current_mode) {
 160         case INSN_UNDEF:
 161                 break;
 162         case INSN_EMULATE:
 163                 register_emulation_hooks(insn->ops);
 164                 break;
 165         case INSN_HW:
 166                 ret = run_all_cpu_set_hw_mode(insn, true);
 167                 if (!ret)
 168                         pr_notice("Enabled %s support\n", insn->ops->name);
 169                 break;
 170         }
 171
 172         return ret;
 173 }
 174
 175 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
 176 {
 177         unsigned long flags;
 178         struct insn_emulation *insn;
 179
 180         insn = kzalloc(sizeof(*insn), GFP_KERNEL);
 181         if (!insn)
 182                 return;
 183
 184         insn->ops = ops;
 185         insn->min = INSN_UNDEF;
 186
 187         switch (ops->status) {
 188         case INSN_DEPRECATED:
 189                 insn->current_mode = INSN_EMULATE;
 190                 /* Disable the HW mode if it was turned on at early boot time */
 191                 run_all_cpu_set_hw_mode(insn, false);
 192                 insn->max = INSN_HW;
 193                 break;
 194         case INSN_OBSOLETE:
 195                 insn->current_mode = INSN_UNDEF;
 196                 insn->max = INSN_EMULATE;
 197                 break;
 198         }
 199
 200         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 201         list_add(&insn->node, &insn_emulation);
 202         nr_insn_emulated++;
 203         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 204
 205         /* Register any handlers if required */
 206         update_insn_emulation_mode(insn, INSN_UNDEF);
 207 }
 208
 209 static int emulation_proc_handler(struct ctl_table *table, int write,
 210                                   void __user *buffer, size_t *lenp,
 211                                   loff_t *ppos)
 212 {
 213         int ret = 0;
 214         struct insn_emulation *insn = container_of(table->data, struct insn_emulation, current_mode);
 215         enum insn_emulation_mode prev_mode = insn->current_mode;
 216
 217         mutex_lock(&insn_emulation_mutex);
 218         ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
 219
 220         if (ret || !write || prev_mode == insn->current_mode)
 221                 goto ret;
 222
 223         ret = update_insn_emulation_mode(insn, prev_mode);
 224         if (ret) {
 225                 /* Mode change failed, revert to previous mode. */
 226                 insn->current_mode = prev_mode;
 227                 update_insn_emulation_mode(insn, INSN_UNDEF);
 228         }
 229 ret:
 230         mutex_unlock(&insn_emulation_mutex);
 231         return ret;
 232 }
 233
 234 static void __init register_insn_emulation_sysctl(void)
 235 {
 236         unsigned long flags;
 237         int i = 0;
 238         struct insn_emulation *insn;
 239         struct ctl_table *insns_sysctl, *sysctl;
 240
 241         insns_sysctl = kcalloc(nr_insn_emulated + 1, sizeof(*sysctl),
 242                                GFP_KERNEL);
 243         if (!insns_sysctl)
 244                 return;
 245
 246         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 247         list_for_each_entry(insn, &insn_emulation, node) {
 248                 sysctl = &insns_sysctl[i];
 249
 250                 sysctl->mode = 0644;
 251                 sysctl->maxlen = sizeof(int);
 252
 253                 sysctl->procname = insn->ops->name;
 254                 sysctl->data = &insn->current_mode;
 255                 sysctl->extra1 = &insn->min;
 256                 sysctl->extra2 = &insn->max;
 257                 sysctl->proc_handler = emulation_proc_handler;
 258                 i++;
 259         }
 260         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 261
 262         register_sysctl("abi", insns_sysctl);
 263 }
 264
 265 /*
 266  *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
 267  *  store-exclusive.
 268  *
 269  *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
 270  *  Where: Rt  = destination
 271  *         Rt2 = source
 272  *         Rn  = address
 273  */
 274
 275 /*
 276  * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
 277  */
 278
 279 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
 280 #define __SWP_LL_SC_LOOPS       4
 281
 282 #define __user_swpX_asm(data, addr, res, temp, temp2, B)        \
 283 do {                                                            \
 284         uaccess_enable();                                       \
 285         __asm__ __volatile__(                                   \
 286         "       mov             %w3, %w7\n"                     \
 287         "0:     ldxr"B"         %w2, [%4]\n"                    \
 288         "1:     stxr"B"         %w0, %w1, [%4]\n"               \
 289         "       cbz             %w0, 2f\n"                      \
 290         "       sub             %w3, %w3, #1\n"                 \
 291         "       cbnz            %w3, 0b\n"                      \
 292         "       mov             %w0, %w5\n"                     \
 293         "       b               3f\n"                           \
 294         "2:\n"                                                  \
 295         "       mov             %w1, %w2\n"                     \
 296         "3:\n"                                                  \
 297         "       .pushsection     .fixup,\"ax\"\n"               \
 298         "       .align          2\n"                            \
 299         "4:     mov             %w0, %w6\n"                     \
 300         "       b               3b\n"                           \
 301         "       .popsection"                                    \
 302         _ASM_EXTABLE(0b, 4b)                                    \
 303         _ASM_EXTABLE(1b, 4b)                                    \
 304         : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
 305         : "r" ((unsigned long)addr), "i" (-EAGAIN),             \
 306           "i" (-EFAULT),                                        \
 307           "i" (__SWP_LL_SC_LOOPS)                               \
 308         : "memory");                                            \
 309         uaccess_disable();                                      \
 310 } while (0)
 311
 312 #define __user_swp_asm(data, addr, res, temp, temp2) \
 313         __user_swpX_asm(data, addr, res, temp, temp2, "")
 314 #define __user_swpb_asm(data, addr, res, temp, temp2) \
 315         __user_swpX_asm(data, addr, res, temp, temp2, "b")
 316
 317 /*
 318  * Bit 22 of the instruction encoding distinguishes between
 319  * the SWP and SWPB variants (bit set means SWPB).
 320  */
 321 #define TYPE_SWPB (1 << 22)
 322
 323 static int emulate_swpX(unsigned int address, unsigned int *data,
 324                         unsigned int type)
 325 {
 326         unsigned int res = 0;
 327
 328         if ((type != TYPE_SWPB) && (address & 0x3)) {
 329                 /* SWP to unaligned address not permitted */
 330                 pr_debug("SWP instruction on unaligned pointer!\n");
 331                 return -EFAULT;
 332         }
 333
 334         while (1) {
 335                 unsigned long temp, temp2;
 336
 337                 if (type == TYPE_SWPB)
 338                         __user_swpb_asm(*data, address, res, temp, temp2);
 339                 else
 340                         __user_swp_asm(*data, address, res, temp, temp2);
 341
 342                 if (likely(res != -EAGAIN) || signal_pending(current))
 343                         break;
 344
 345                 cond_resched();
 346         }
 347
 348         return res;
 349 }
 350
 351 #define ARM_OPCODE_CONDTEST_FAIL   0
 352 #define ARM_OPCODE_CONDTEST_PASS   1
 353 #define ARM_OPCODE_CONDTEST_UNCOND 2
 354
 355 #define ARM_OPCODE_CONDITION_UNCOND     0xf
 356
 357 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
 358 {
 359         u32 cc_bits  = opcode >> 28;
 360
 361         if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
 362                 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
 363                         return ARM_OPCODE_CONDTEST_PASS;
 364                 else
 365                         return ARM_OPCODE_CONDTEST_FAIL;
 366         }
 367         return ARM_OPCODE_CONDTEST_UNCOND;
 368 }
 369
 370 /*
 371  * swp_handler logs the id of calling process, dissects the instruction, sanity
 372  * checks the memory location, calls emulate_swpX for the actual operation and
 373  * deals with fixup/error handling before returning
 374  */
 375 static int swp_handler(struct pt_regs *regs, u32 instr)
 376 {
 377         u32 destreg, data, type, address = 0;
 378         const void __user *user_ptr;
 379         int rn, rt2, res = 0;
 380
 381         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 382
 383         type = instr & TYPE_SWPB;
 384
 385         switch (aarch32_check_condition(instr, regs->pstate)) {
 386         case ARM_OPCODE_CONDTEST_PASS:
 387                 break;
 388         case ARM_OPCODE_CONDTEST_FAIL:
 389                 /* Condition failed - return to next instruction */
 390                 goto ret;
 391         case ARM_OPCODE_CONDTEST_UNCOND:
 392                 /* If unconditional encoding - not a SWP, undef */
 393                 return -EFAULT;
 394         default:
 395                 return -EINVAL;
 396         }
 397
 398         rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
 399         rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
 400
 401         address = (u32)regs->user_regs.regs[rn];
 402         data    = (u32)regs->user_regs.regs[rt2];
 403         destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
 404
 405         pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
 406                 rn, address, destreg,
 407                 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
 408
 409         /* Check access in reasonable access range for both SWP and SWPB */
 410         user_ptr = (const void __user *)(unsigned long)(address & ~3);
 411         if (!access_ok(VERIFY_WRITE, user_ptr, 4)) {
 412                 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
 413                         address);
 414                 goto fault;
 415         }
 416
 417         res = emulate_swpX(address, &data, type);
 418         if (res == -EFAULT)
 419                 goto fault;
 420         else if (res == 0)
 421                 regs->user_regs.regs[destreg] = data;
 422
 423 ret:
 424         if (type == TYPE_SWPB)
 425                 trace_instruction_emulation("swpb", regs->pc);
 426         else
 427                 trace_instruction_emulation("swp", regs->pc);
 428
 429         pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
 430                         current->comm, (unsigned long)current->pid, regs->pc);
 431
 432         arm64_skip_faulting_instruction(regs, 4);
 433         return 0;
 434
 435 fault:
 436         pr_debug("SWP{B} emulation: access caused memory abort!\n");
 437         arm64_notify_segfault(address);
 438
 439         return 0;
 440 }
 441
 442 /*
 443  * Only emulate SWP/SWPB executed in ARM state/User mode.
 444  * The kernel must be SWP free and SWP{B} does not exist in Thumb.
 445  */
 446 static struct undef_hook swp_hooks[] = {
 447         {
 448                 .instr_mask     = 0x0fb00ff0,
 449                 .instr_val      = 0x01000090,
 450                 .pstate_mask    = PSR_AA32_MODE_MASK,
 451                 .pstate_val     = PSR_AA32_MODE_USR,
 452                 .fn             = swp_handler
 453         },
 454         { }
 455 };
 456
 457 static struct insn_emulation_ops swp_ops = {
 458         .name = "swp",
 459         .status = INSN_OBSOLETE,
 460         .hooks = swp_hooks,
 461         .set_hw_mode = NULL,
 462 };
 463
 464 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
 465 {
 466         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 467
 468         switch (aarch32_check_condition(instr, regs->pstate)) {
 469         case ARM_OPCODE_CONDTEST_PASS:
 470                 break;
 471         case ARM_OPCODE_CONDTEST_FAIL:
 472                 /* Condition failed - return to next instruction */
 473                 goto ret;
 474         case ARM_OPCODE_CONDTEST_UNCOND:
 475                 /* If unconditional encoding - not a barrier instruction */
 476                 return -EFAULT;
 477         default:
 478                 return -EINVAL;
 479         }
 480
 481         switch (aarch32_insn_mcr_extract_crm(instr)) {
 482         case 10:
 483                 /*
 484                  * dmb - mcr p15, 0, Rt, c7, c10, 5
 485                  * dsb - mcr p15, 0, Rt, c7, c10, 4
 486                  */
 487                 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
 488                         dmb(sy);
 489                         trace_instruction_emulation(
 490                                 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
 491                 } else {
 492                         dsb(sy);
 493                         trace_instruction_emulation(
 494                                 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
 495                 }
 496                 break;
 497         case 5:
 498                 /*
 499                  * isb - mcr p15, 0, Rt, c7, c5, 4
 500                  *
 501                  * Taking an exception or returning from one acts as an
 502                  * instruction barrier. So no explicit barrier needed here.
 503                  */
 504                 trace_instruction_emulation(
 505                         "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
 506                 break;
 507         }
 508
 509 ret:
 510         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
 511                         current->comm, (unsigned long)current->pid, regs->pc);
 512
 513         arm64_skip_faulting_instruction(regs, 4);
 514         return 0;
 515 }
 516
 517 static int cp15_barrier_set_hw_mode(bool enable)
 518 {
 519         if (enable)
 520                 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_CP15BEN);
 521         else
 522                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_CP15BEN, 0);
 523         return 0;
 524 }
 525
 526 static struct undef_hook cp15_barrier_hooks[] = {
 527         {
 528                 .instr_mask     = 0x0fff0fdf,
 529                 .instr_val      = 0x0e070f9a,
 530                 .pstate_mask    = PSR_AA32_MODE_MASK,
 531                 .pstate_val     = PSR_AA32_MODE_USR,
 532                 .fn             = cp15barrier_handler,
 533         },
 534         {
 535                 .instr_mask     = 0x0fff0fff,
 536                 .instr_val      = 0x0e070f95,
 537                 .pstate_mask    = PSR_AA32_MODE_MASK,
 538                 .pstate_val     = PSR_AA32_MODE_USR,
 539                 .fn             = cp15barrier_handler,
 540         },
 541         { }
 542 };
 543
 544 static struct insn_emulation_ops cp15_barrier_ops = {
 545         .name = "cp15_barrier",
 546         .status = INSN_DEPRECATED,
 547         .hooks = cp15_barrier_hooks,
 548         .set_hw_mode = cp15_barrier_set_hw_mode,
 549 };
 550
 551 static int setend_set_hw_mode(bool enable)
 552 {
 553         if (!cpu_supports_mixed_endian_el0())
 554                 return -EINVAL;
 555
 556         if (enable)
 557                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SED, 0);
 558         else
 559                 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_SED);
 560         return 0;
 561 }
 562
 563 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
 564 {
 565         char *insn;
 566
 567         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 568
 569         if (big_endian) {
 570                 insn = "setend be";
 571                 regs->pstate |= PSR_AA32_E_BIT;
 572         } else {
 573                 insn = "setend le";
 574                 regs->pstate &= ~PSR_AA32_E_BIT;
 575         }
 576
 577         trace_instruction_emulation(insn, regs->pc);
 578         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
 579                         current->comm, (unsigned long)current->pid, regs->pc);
 580
 581         return 0;
 582 }
 583
 584 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
 585 {
 586         int rc = compat_setend_handler(regs, (instr >> 9) & 1);
 587         arm64_skip_faulting_instruction(regs, 4);
 588         return rc;
 589 }
 590
 591 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
 592 {
 593         int rc = compat_setend_handler(regs, (instr >> 3) & 1);
 594         arm64_skip_faulting_instruction(regs, 2);
 595         return rc;
 596 }
 597
 598 static struct undef_hook setend_hooks[] = {
 599         {
 600                 .instr_mask     = 0xfffffdff,
 601                 .instr_val      = 0xf1010000,
 602                 .pstate_mask    = PSR_AA32_MODE_MASK,
 603                 .pstate_val     = PSR_AA32_MODE_USR,
 604                 .fn             = a32_setend_handler,
 605         },
 606         {
 607                 /* Thumb mode */
 608                 .instr_mask     = 0xfffffff7,
 609                 .instr_val      = 0x0000b650,
 610                 .pstate_mask    = (PSR_AA32_T_BIT | PSR_AA32_MODE_MASK),
 611                 .pstate_val     = (PSR_AA32_T_BIT | PSR_AA32_MODE_USR),
 612                 .fn             = t16_setend_handler,
 613         },
 614         {}
 615 };
 616
 617 static struct insn_emulation_ops setend_ops = {
 618         .name = "setend",
 619         .status = INSN_DEPRECATED,
 620         .hooks = setend_hooks,
 621         .set_hw_mode = setend_set_hw_mode,
 622 };
 623
 624 /*
 625  * Invoked as late_initcall, since not needed before init spawned.
 626  */
 627 static int __init armv8_deprecated_init(void)
 628 {
 629         if (IS_ENABLED(CONFIG_SWP_EMULATION))
 630                 register_insn_emulation(&swp_ops);
 631
 632         if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
 633                 register_insn_emulation(&cp15_barrier_ops);
 634
 635         if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
 636                 if(system_supports_mixed_endian_el0())
 637                         register_insn_emulation(&setend_ops);
 638                 else
 639                         pr_info("setend instruction emulation is not supported on this system\n");
 640         }
 641
 642         cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
 643                                   "arm64/isndep:starting",
 644                                   run_all_insn_set_hw_mode, NULL);
 645         register_insn_emulation_sysctl();
 646
 647         return 0;
 648 }
 649
 650 core_initcall(armv8_deprecated_init);