arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/sort.h>
  24 #include <linux/stop_machine.h>
  25 #include <linux/types.h>
  26 #include <asm/cpu.h>
  27 #include <asm/cpufeature.h>
  28 #include <asm/cpu_ops.h>
  29 #include <asm/processor.h>
  30 #include <asm/sysreg.h>
  31
  32 unsigned long elf_hwcap __read_mostly;
  33 EXPORT_SYMBOL_GPL(elf_hwcap);
  34
  35 #ifdef CONFIG_COMPAT
  36 #define COMPAT_ELF_HWCAP_DEFAULT        \
  37                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  38                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  39                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  40                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  41                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  42                                  COMPAT_HWCAP_LPAE)
  43 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  44 unsigned int compat_elf_hwcap2 __read_mostly;
  45 #endif
  46
  47 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  48
  49 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  50         {                                               \
  51                 .sign = SIGNED,                         \
  52                 .strict = STRICT,                       \
  53                 .type = TYPE,                           \
  54                 .shift = SHIFT,                         \
  55                 .width = WIDTH,                         \
  56                 .safe_val = SAFE_VAL,                   \
  57         }
  58
  59 /* Define a feature with signed values */
  60 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  61         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  62
  63 /* Define a feature with unsigned value */
  64 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  65         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  66
  67 #define ARM64_FTR_END                                   \
  68         {                                               \
  69                 .width = 0,                             \
  70         }
  71
  72 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  73         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  74         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  75         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  76         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  77         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  78         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  79         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  81         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  82         ARM64_FTR_END,
  83 };
  84
  85 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  86         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  87         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  88         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  89         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  90         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  91         /* Linux doesn't care about the EL3 */
  92         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  94         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
  95         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
  96         ARM64_FTR_END,
  97 };
  98
  99 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 100         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 101         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 102         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 103         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 104         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 105         /* Linux shouldn't care about secure memory */
 106         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 107         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 108         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 109         /*
 110          * Differing PARange is fine as long as all peripherals and memory are mapped
 111          * within the minimum PARange of all CPUs
 112          */
 113         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 114         ARM64_FTR_END,
 115 };
 116
 117 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 118         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 119         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 120         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 121         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 122         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 125         ARM64_FTR_END,
 126 };
 127
 128 static struct arm64_ftr_bits ftr_ctr[] = {
 129         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),      /* RES1 */
 130         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0),
 131         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */
 132         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */
 133         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0),        /* CWG */
 134         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0),        /* ERG */
 135         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
 136         /*
 137          * Linux can handle differing I-cache policies. Userspace JITs will
 138          * make use of *minLine
 139          */
 140         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),   /* L1Ip */
 141         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 142         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),  /* IminLine */
 143         ARM64_FTR_END,
 144 };
 145
 146 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 147         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),        /* InnerShr */
 148         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 149         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 150         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 151         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 152         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
 153         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 154         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 155         ARM64_FTR_END,
 156 };
 157
 158 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 159         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 160         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 161         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 162         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 163         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 164         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 165         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 166         ARM64_FTR_END,
 167 };
 168
 169 static struct arm64_ftr_bits ftr_mvfr2[] = {
 170         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 171         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 172         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 173         ARM64_FTR_END,
 174 };
 175
 176 static struct arm64_ftr_bits ftr_dczid[] = {
 177         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 178         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 179         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 180         ARM64_FTR_END,
 181 };
 182
 183
 184 static struct arm64_ftr_bits ftr_id_isar5[] = {
 185         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 186         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 187         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 188         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 190         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 192         ARM64_FTR_END,
 193 };
 194
 195 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 196         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 197         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 198         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 199         ARM64_FTR_END,
 200 };
 201
 202 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 203         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 204         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 205         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 206         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 207         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 208         ARM64_FTR_END,
 209 };
 210
 211 /*
 212  * Common ftr bits for a 32bit register with all hidden, strict
 213  * attributes, with 4bit feature fields and a default safe value of
 214  * 0. Covers the following 32bit registers:
 215  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 216  */
 217 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 218         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 219         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 220         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 221         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 222         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 223         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 224         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 225         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 226         ARM64_FTR_END,
 227 };
 228
 229 static struct arm64_ftr_bits ftr_generic[] = {
 230         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 231         ARM64_FTR_END,
 232 };
 233
 234 static struct arm64_ftr_bits ftr_generic32[] = {
 235         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 236         ARM64_FTR_END,
 237 };
 238
 239 static struct arm64_ftr_bits ftr_aa64raz[] = {
 240         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 241         ARM64_FTR_END,
 242 };
 243
 244 #define ARM64_FTR_REG(id, table)                \
 245         {                                       \
 246                 .sys_id = id,                   \
 247                 .name = #id,                    \
 248                 .ftr_bits = &((table)[0]),      \
 249         }
 250
 251 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 252
 253         /* Op1 = 0, CRn = 0, CRm = 1 */
 254         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 255         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 256         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
 257         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 258         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 259         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 260         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 261
 262         /* Op1 = 0, CRn = 0, CRm = 2 */
 263         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 264         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 265         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 266         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 267         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 268         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 269         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 270
 271         /* Op1 = 0, CRn = 0, CRm = 3 */
 272         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 273         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 274         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 275
 276         /* Op1 = 0, CRn = 0, CRm = 4 */
 277         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 278         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 279
 280         /* Op1 = 0, CRn = 0, CRm = 5 */
 281         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 282         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 283
 284         /* Op1 = 0, CRn = 0, CRm = 6 */
 285         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 286         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 287
 288         /* Op1 = 0, CRn = 0, CRm = 7 */
 289         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 290         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 291
 292         /* Op1 = 3, CRn = 0, CRm = 0 */
 293         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 294         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 295
 296         /* Op1 = 3, CRn = 14, CRm = 0 */
 297         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 298 };
 299
 300 static int search_cmp_ftr_reg(const void *id, const void *regp)
 301 {
 302         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 303 }
 304
 305 /*
 306  * get_arm64_ftr_reg - Lookup a feature register entry using its
 307  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 308  * ascending order of sys_id , we use binary search to find a matching
 309  * entry.
 310  *
 311  * returns - Upon success,  matching ftr_reg entry for id.
 312  *         - NULL on failure. It is upto the caller to decide
 313  *           the impact of a failure.
 314  */
 315 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 316 {
 317         return bsearch((const void *)(unsigned long)sys_id,
 318                         arm64_ftr_regs,
 319                         ARRAY_SIZE(arm64_ftr_regs),
 320                         sizeof(arm64_ftr_regs[0]),
 321                         search_cmp_ftr_reg);
 322 }
 323
 324 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 325 {
 326         u64 mask = arm64_ftr_mask(ftrp);
 327
 328         reg &= ~mask;
 329         reg |= (ftr_val << ftrp->shift) & mask;
 330         return reg;
 331 }
 332
 333 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 334 {
 335         s64 ret = 0;
 336
 337         switch (ftrp->type) {
 338         case FTR_EXACT:
 339                 ret = ftrp->safe_val;
 340                 break;
 341         case FTR_LOWER_SAFE:
 342                 ret = new < cur ? new : cur;
 343                 break;
 344         case FTR_HIGHER_OR_ZERO_SAFE:
 345                 if (!cur || !new)
 346                         break;
 347                 /* Fallthrough */
 348         case FTR_HIGHER_SAFE:
 349                 ret = new > cur ? new : cur;
 350                 break;
 351         default:
 352                 BUG();
 353         }
 354
 355         return ret;
 356 }
 357
 358 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 359 {
 360         return ((const struct arm64_ftr_reg *)a)->sys_id -
 361                  ((const struct arm64_ftr_reg *)b)->sys_id;
 362 }
 363
 364 static void __init swap_ftr_regs(void *a, void *b, int size)
 365 {
 366         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 367         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 368         *(struct arm64_ftr_reg *)b = tmp;
 369 }
 370
 371 static void __init sort_ftr_regs(void)
 372 {
 373         /* Keep the array sorted so that we can do the binary search */
 374         sort(arm64_ftr_regs,
 375                 ARRAY_SIZE(arm64_ftr_regs),
 376                 sizeof(arm64_ftr_regs[0]),
 377                 sort_cmp_ftr_regs,
 378                 swap_ftr_regs);
 379 }
 380
 381 /*
 382  * Initialise the CPU feature register from Boot CPU values.
 383  * Also initiliases the strict_mask for the register.
 384  */
 385 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 386 {
 387         u64 val = 0;
 388         u64 strict_mask = ~0x0ULL;
 389         struct arm64_ftr_bits *ftrp;
 390         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 391
 392         BUG_ON(!reg);
 393
 394         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 395                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 396
 397                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 398                 if (!ftrp->strict)
 399                         strict_mask &= ~arm64_ftr_mask(ftrp);
 400         }
 401         reg->sys_val = val;
 402         reg->strict_mask = strict_mask;
 403 }
 404
 405 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 406 {
 407         /* Before we start using the tables, make sure it is sorted */
 408         sort_ftr_regs();
 409
 410         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 411         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 412         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 413         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 414         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 415         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 416         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 417         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 418         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 419         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 420         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 421         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 422         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 423         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 424         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 425         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 426         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 427         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 428         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 429         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 430         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 431         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 432         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 433         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 434         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 435         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 436         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 437 }
 438
 439 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 440 {
 441         struct arm64_ftr_bits *ftrp;
 442
 443         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 444                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 445                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 446
 447                 if (ftr_cur == ftr_new)
 448                         continue;
 449                 /* Find a safe value */
 450                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 451                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 452         }
 453
 454 }
 455
 456 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 457 {
 458         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 459
 460         BUG_ON(!regp);
 461         update_cpu_ftr_reg(regp, val);
 462         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 463                 return 0;
 464         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 465                         regp->name, boot, cpu, val);
 466         return 1;
 467 }
 468
 469 /*
 470  * Update system wide CPU feature registers with the values from a
 471  * non-boot CPU. Also performs SANITY checks to make sure that there
 472  * aren't any insane variations from that of the boot CPU.
 473  */
 474 void update_cpu_features(int cpu,
 475                          struct cpuinfo_arm64 *info,
 476                          struct cpuinfo_arm64 *boot)
 477 {
 478         int taint = 0;
 479
 480         /*
 481          * The kernel can handle differing I-cache policies, but otherwise
 482          * caches should look identical. Userspace JITs will make use of
 483          * *minLine.
 484          */
 485         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 486                                       info->reg_ctr, boot->reg_ctr);
 487
 488         /*
 489          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 490          * could result in too much or too little memory being zeroed if a
 491          * process is preempted and migrated between CPUs.
 492          */
 493         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 494                                       info->reg_dczid, boot->reg_dczid);
 495
 496         /* If different, timekeeping will be broken (especially with KVM) */
 497         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 498                                       info->reg_cntfrq, boot->reg_cntfrq);
 499
 500         /*
 501          * The kernel uses self-hosted debug features and expects CPUs to
 502          * support identical debug features. We presently need CTX_CMPs, WRPs,
 503          * and BRPs to be identical.
 504          * ID_AA64DFR1 is currently RES0.
 505          */
 506         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 507                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 508         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 509                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 510         /*
 511          * Even in big.LITTLE, processors should be identical instruction-set
 512          * wise.
 513          */
 514         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 515                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 516         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 517                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 518
 519         /*
 520          * Differing PARange support is fine as long as all peripherals and
 521          * memory are mapped within the minimum PARange of all CPUs.
 522          * Linux should not care about secure memory.
 523          */
 524         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 525                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 526         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 527                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 528
 529         /*
 530          * EL3 is not our concern.
 531          * ID_AA64PFR1 is currently RES0.
 532          */
 533         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 534                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 535         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 536                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 537
 538         /*
 539          * If we have AArch32, we care about 32-bit features for compat. These
 540          * registers should be RES0 otherwise.
 541          */
 542         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 543                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 544         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 545                                         info->reg_id_isar0, boot->reg_id_isar0);
 546         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 547                                         info->reg_id_isar1, boot->reg_id_isar1);
 548         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 549                                         info->reg_id_isar2, boot->reg_id_isar2);
 550         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 551                                         info->reg_id_isar3, boot->reg_id_isar3);
 552         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 553                                         info->reg_id_isar4, boot->reg_id_isar4);
 554         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 555                                         info->reg_id_isar5, boot->reg_id_isar5);
 556
 557         /*
 558          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 559          * ACTLR formats could differ across CPUs and therefore would have to
 560          * be trapped for virtualization anyway.
 561          */
 562         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 563                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 564         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 565                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 566         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 567                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 568         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 569                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 570         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 571                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 572         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 573                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 574         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 575                                         info->reg_mvfr0, boot->reg_mvfr0);
 576         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 577                                         info->reg_mvfr1, boot->reg_mvfr1);
 578         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 579                                         info->reg_mvfr2, boot->reg_mvfr2);
 580
 581         /*
 582          * Mismatched CPU features are a recipe for disaster. Don't even
 583          * pretend to support them.
 584          */
 585         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 586                         "Unsupported CPU feature variation.\n");
 587 }
 588
 589 u64 read_system_reg(u32 id)
 590 {
 591         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 592
 593         /* We shouldn't get a request for an unsupported register */
 594         BUG_ON(!regp);
 595         return regp->sys_val;
 596 }
 597
 598 #include <linux/irqchip/arm-gic-v3.h>
 599
 600 static bool
 601 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 602 {
 603         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 604
 605         return val >= entry->min_field_value;
 606 }
 607
 608 static bool
 609 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
 610 {
 611         u64 val;
 612
 613         val = read_system_reg(entry->sys_reg);
 614         return feature_matches(val, entry);
 615 }
 616
 617 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
 618 {
 619         bool has_sre;
 620
 621         if (!has_cpuid_feature(entry))
 622                 return false;
 623
 624         has_sre = gic_enable_sre();
 625         if (!has_sre)
 626                 pr_warn_once("%s present but disabled by higher exception level\n",
 627                              entry->desc);
 628
 629         return has_sre;
 630 }
 631
 632 static const struct arm64_cpu_capabilities arm64_features[] = {
 633         {
 634                 .desc = "GIC system register CPU interface",
 635                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 636                 .matches = has_useable_gicv3_cpuif,
 637                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 638                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 639                 .sign = FTR_UNSIGNED,
 640                 .min_field_value = 1,
 641         },
 642 #ifdef CONFIG_ARM64_PAN
 643         {
 644                 .desc = "Privileged Access Never",
 645                 .capability = ARM64_HAS_PAN,
 646                 .matches = has_cpuid_feature,
 647                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 648                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 649                 .sign = FTR_UNSIGNED,
 650                 .min_field_value = 1,
 651                 .enable = cpu_enable_pan,
 652         },
 653 #endif /* CONFIG_ARM64_PAN */
 654 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 655         {
 656                 .desc = "LSE atomic instructions",
 657                 .capability = ARM64_HAS_LSE_ATOMICS,
 658                 .matches = has_cpuid_feature,
 659                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 660                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 661                 .sign = FTR_UNSIGNED,
 662                 .min_field_value = 2,
 663         },
 664 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 665         {
 666                 .desc = "32-bit EL0 Support",
 667                 .capability = ARM64_HAS_32BIT_EL0,
 668                 .matches = has_cpuid_feature,
 669                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 670                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
 671                 .sign = FTR_UNSIGNED,
 672                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
 673         },
 674         {},
 675 };
 676
 677 #define HWCAP_CAP(reg, field, s, min_value, type, cap)  \
 678         {                                                       \
 679                 .desc = #cap,                                   \
 680                 .matches = has_cpuid_feature,                   \
 681                 .sys_reg = reg,                                 \
 682                 .field_pos = field,                             \
 683                 .sign = s,                                      \
 684                 .min_field_value = min_value,                   \
 685                 .hwcap_type = type,                             \
 686                 .hwcap = cap,                                   \
 687         }
 688
 689 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
 690         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
 691         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
 692         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
 693         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
 694         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
 695         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
 696         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
 697         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
 698 #ifdef CONFIG_COMPAT
 699         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 700         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 701         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 702         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 703         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 704 #endif
 705         {},
 706 };
 707
 708 static void cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
 709 {
 710         switch (cap->hwcap_type) {
 711         case CAP_HWCAP:
 712                 elf_hwcap |= cap->hwcap;
 713                 break;
 714 #ifdef CONFIG_COMPAT
 715         case CAP_COMPAT_HWCAP:
 716                 compat_elf_hwcap |= (u32)cap->hwcap;
 717                 break;
 718         case CAP_COMPAT_HWCAP2:
 719                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 720                 break;
 721 #endif
 722         default:
 723                 WARN_ON(1);
 724                 break;
 725         }
 726 }
 727
 728 /* Check if we have a particular HWCAP enabled */
 729 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
 730 {
 731         bool rc;
 732
 733         switch (cap->hwcap_type) {
 734         case CAP_HWCAP:
 735                 rc = (elf_hwcap & cap->hwcap) != 0;
 736                 break;
 737 #ifdef CONFIG_COMPAT
 738         case CAP_COMPAT_HWCAP:
 739                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 740                 break;
 741         case CAP_COMPAT_HWCAP2:
 742                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 743                 break;
 744 #endif
 745         default:
 746                 WARN_ON(1);
 747                 rc = false;
 748         }
 749
 750         return rc;
 751 }
 752
 753 static void setup_cpu_hwcaps(void)
 754 {
 755         int i;
 756         const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
 757
 758         for (i = 0; hwcaps[i].desc; i++)
 759                 if (hwcaps[i].matches(&hwcaps[i]))
 760                         cap_set_hwcap(&hwcaps[i]);
 761 }
 762
 763 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 764                             const char *info)
 765 {
 766         int i;
 767
 768         for (i = 0; caps[i].desc; i++) {
 769                 if (!caps[i].matches(&caps[i]))
 770                         continue;
 771
 772                 if (!cpus_have_cap(caps[i].capability))
 773                         pr_info("%s %s\n", info, caps[i].desc);
 774                 cpus_set_cap(caps[i].capability);
 775         }
 776 }
 777
 778 /*
 779  * Run through the enabled capabilities and enable() it on all active
 780  * CPUs
 781  */
 782 static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 783 {
 784         int i;
 785
 786         for (i = 0; caps[i].desc; i++)
 787                 if (caps[i].enable && cpus_have_cap(caps[i].capability))
 788                         /*
 789                          * Use stop_machine() as it schedules the work allowing
 790                          * us to modify PSTATE, instead of on_each_cpu() which
 791                          * uses an IPI, giving us a PSTATE that disappears when
 792                          * we return.
 793                          */
 794                         stop_machine(caps[i].enable, NULL, cpu_online_mask);
 795 }
 796
 797 #ifdef CONFIG_HOTPLUG_CPU
 798
 799 /*
 800  * Flag to indicate if we have computed the system wide
 801  * capabilities based on the boot time active CPUs. This
 802  * will be used to determine if a new booting CPU should
 803  * go through the verification process to make sure that it
 804  * supports the system capabilities, without using a hotplug
 805  * notifier.
 806  */
 807 static bool sys_caps_initialised;
 808
 809 static inline void set_sys_caps_initialised(void)
 810 {
 811         sys_caps_initialised = true;
 812 }
 813
 814 /*
 815  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 816  */
 817 static u64 __raw_read_system_reg(u32 sys_id)
 818 {
 819         switch (sys_id) {
 820         case SYS_ID_PFR0_EL1:           return (u64)read_cpuid(ID_PFR0_EL1);
 821         case SYS_ID_PFR1_EL1:           return (u64)read_cpuid(ID_PFR1_EL1);
 822         case SYS_ID_DFR0_EL1:           return (u64)read_cpuid(ID_DFR0_EL1);
 823         case SYS_ID_MMFR0_EL1:          return (u64)read_cpuid(ID_MMFR0_EL1);
 824         case SYS_ID_MMFR1_EL1:          return (u64)read_cpuid(ID_MMFR1_EL1);
 825         case SYS_ID_MMFR2_EL1:          return (u64)read_cpuid(ID_MMFR2_EL1);
 826         case SYS_ID_MMFR3_EL1:          return (u64)read_cpuid(ID_MMFR3_EL1);
 827         case SYS_ID_ISAR0_EL1:          return (u64)read_cpuid(ID_ISAR0_EL1);
 828         case SYS_ID_ISAR1_EL1:          return (u64)read_cpuid(ID_ISAR1_EL1);
 829         case SYS_ID_ISAR2_EL1:          return (u64)read_cpuid(ID_ISAR2_EL1);
 830         case SYS_ID_ISAR3_EL1:          return (u64)read_cpuid(ID_ISAR3_EL1);
 831         case SYS_ID_ISAR4_EL1:          return (u64)read_cpuid(ID_ISAR4_EL1);
 832         case SYS_ID_ISAR5_EL1:          return (u64)read_cpuid(ID_ISAR4_EL1);
 833         case SYS_MVFR0_EL1:             return (u64)read_cpuid(MVFR0_EL1);
 834         case SYS_MVFR1_EL1:             return (u64)read_cpuid(MVFR1_EL1);
 835         case SYS_MVFR2_EL1:             return (u64)read_cpuid(MVFR2_EL1);
 836
 837         case SYS_ID_AA64PFR0_EL1:       return (u64)read_cpuid(ID_AA64PFR0_EL1);
 838         case SYS_ID_AA64PFR1_EL1:       return (u64)read_cpuid(ID_AA64PFR0_EL1);
 839         case SYS_ID_AA64DFR0_EL1:       return (u64)read_cpuid(ID_AA64DFR0_EL1);
 840         case SYS_ID_AA64DFR1_EL1:       return (u64)read_cpuid(ID_AA64DFR0_EL1);
 841         case SYS_ID_AA64MMFR0_EL1:      return (u64)read_cpuid(ID_AA64MMFR0_EL1);
 842         case SYS_ID_AA64MMFR1_EL1:      return (u64)read_cpuid(ID_AA64MMFR1_EL1);
 843         case SYS_ID_AA64ISAR0_EL1:      return (u64)read_cpuid(ID_AA64ISAR0_EL1);
 844         case SYS_ID_AA64ISAR1_EL1:      return (u64)read_cpuid(ID_AA64ISAR1_EL1);
 845
 846         case SYS_CNTFRQ_EL0:            return (u64)read_cpuid(CNTFRQ_EL0);
 847         case SYS_CTR_EL0:               return (u64)read_cpuid(CTR_EL0);
 848         case SYS_DCZID_EL0:             return (u64)read_cpuid(DCZID_EL0);
 849         default:
 850                 BUG();
 851                 return 0;
 852         }
 853 }
 854
 855 /*
 856  * Park the CPU which doesn't have the capability as advertised
 857  * by the system.
 858  */
 859 static void fail_incapable_cpu(char *cap_type,
 860                                  const struct arm64_cpu_capabilities *cap)
 861 {
 862         int cpu = smp_processor_id();
 863
 864         pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
 865         /* Mark this CPU absent */
 866         set_cpu_present(cpu, 0);
 867
 868         /* Check if we can park ourselves */
 869         if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
 870                 cpu_ops[cpu]->cpu_die(cpu);
 871         asm(
 872         "1:     wfe\n"
 873         "       wfi\n"
 874         "       b       1b");
 875 }
 876
 877 /*
 878  * Run through the enabled system capabilities and enable() it on this CPU.
 879  * The capabilities were decided based on the available CPUs at the boot time.
 880  * Any new CPU should match the system wide status of the capability. If the
 881  * new CPU doesn't have a capability which the system now has enabled, we
 882  * cannot do anything to fix it up and could cause unexpected failures. So
 883  * we park the CPU.
 884  */
 885 void verify_local_cpu_capabilities(void)
 886 {
 887         int i;
 888         const struct arm64_cpu_capabilities *caps;
 889
 890         /*
 891          * If we haven't computed the system capabilities, there is nothing
 892          * to verify.
 893          */
 894         if (!sys_caps_initialised)
 895                 return;
 896
 897         caps = arm64_features;
 898         for (i = 0; caps[i].desc; i++) {
 899                 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
 900                         continue;
 901                 /*
 902                  * If the new CPU misses an advertised feature, we cannot proceed
 903                  * further, park the cpu.
 904                  */
 905                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 906                         fail_incapable_cpu("arm64_features", &caps[i]);
 907                 if (caps[i].enable)
 908                         caps[i].enable(NULL);
 909         }
 910
 911         for (i = 0, caps = arm64_hwcaps; caps[i].desc; i++) {
 912                 if (!cpus_have_hwcap(&caps[i]))
 913                         continue;
 914                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 915                         fail_incapable_cpu("arm64_hwcaps", &caps[i]);
 916         }
 917 }
 918
 919 #else   /* !CONFIG_HOTPLUG_CPU */
 920
 921 static inline void set_sys_caps_initialised(void)
 922 {
 923 }
 924
 925 #endif  /* CONFIG_HOTPLUG_CPU */
 926
 927 static void setup_feature_capabilities(void)
 928 {
 929         update_cpu_capabilities(arm64_features, "detected feature:");
 930         enable_cpu_capabilities(arm64_features);
 931 }
 932
 933 void __init setup_cpu_features(void)
 934 {
 935         u32 cwg;
 936         int cls;
 937
 938         /* Set the CPU feature capabilies */
 939         setup_feature_capabilities();
 940         setup_cpu_hwcaps();
 941
 942         /* Advertise that we have computed the system capabilities */
 943         set_sys_caps_initialised();
 944
 945         /*
 946          * Check for sane CTR_EL0.CWG value.
 947          */
 948         cwg = cache_type_cwg();
 949         cls = cache_line_size();
 950         if (!cwg)
 951                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
 952                         cls);
 953         if (L1_CACHE_BYTES < cls)
 954                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
 955                         L1_CACHE_BYTES, cls);
 956 }