arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/percpu.h>
  24 #include <linux/sort.h>
  25 #include <linux/stop_machine.h>
  26 #include <linux/types.h>
  27 #include <linux/mm.h>
  28 #include <linux/cpu.h>
  29
  30 #include <asm/cpu.h>
  31 #include <asm/cpufeature.h>
  32 #include <asm/cpu_ops.h>
  33 #include <asm/fpsimd.h>
  34 #include <asm/hwcap.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/processor.h>
  37 #include <asm/sysreg.h>
  38 #include <asm/traps.h>
  39 #include <asm/vectors.h>
  40 #include <asm/virt.h>
  41
  42 unsigned long elf_hwcap __read_mostly;
  43 EXPORT_SYMBOL_GPL(elf_hwcap);
  44
  45 #ifdef CONFIG_COMPAT
  46 #define COMPAT_ELF_HWCAP_DEFAULT        \
  47                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  48                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  49                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  50                                  COMPAT_HWCAP_LPAE)
  51 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  52 unsigned int compat_elf_hwcap2 __read_mostly;
  53 #endif
  54
  55 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  56 EXPORT_SYMBOL(cpu_hwcaps);
  57
  58 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
  59
  60 /*
  61  * Flag to indicate if we have computed the system wide
  62  * capabilities based on the boot time active CPUs. This
  63  * will be used to determine if a new booting CPU should
  64  * go through the verification process to make sure that it
  65  * supports the system capabilities, without using a hotplug
  66  * notifier.
  67  */
  68 static bool sys_caps_initialised;
  69
  70 static inline void set_sys_caps_initialised(void)
  71 {
  72         sys_caps_initialised = true;
  73 }
  74
  75 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  76 {
  77         /* file-wide pr_fmt adds "CPU features: " prefix */
  78         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  79         return 0;
  80 }
  81
  82 static struct notifier_block cpu_hwcaps_notifier = {
  83         .notifier_call = dump_cpu_hwcaps
  84 };
  85
  86 static int __init register_cpu_hwcaps_dumper(void)
  87 {
  88         atomic_notifier_chain_register(&panic_notifier_list,
  89                                        &cpu_hwcaps_notifier);
  90         return 0;
  91 }
  92 __initcall(register_cpu_hwcaps_dumper);
  93
  94 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  95 EXPORT_SYMBOL(cpu_hwcap_keys);
  96
  97 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  98         {                                               \
  99                 .sign = SIGNED,                         \
 100                 .visible = VISIBLE,                     \
 101                 .strict = STRICT,                       \
 102                 .type = TYPE,                           \
 103                 .shift = SHIFT,                         \
 104                 .width = WIDTH,                         \
 105                 .safe_val = SAFE_VAL,                   \
 106         }
 107
 108 /* Define a feature with unsigned values */
 109 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 110         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 111
 112 /* Define a feature with a signed value */
 113 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 114         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 115
 116 #define ARM64_FTR_END                                   \
 117         {                                               \
 118                 .width = 0,                             \
 119         }
 120
 121 /* meta feature for alternatives */
 122 static bool __maybe_unused
 123 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 124
 125
 126 /*
 127  * NOTE: Any changes to the visibility of features should be kept in
 128  * sync with the documentation of the CPU feature register ABI.
 129  */
 130 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 137         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 143         ARM64_FTR_END,
 144 };
 145
 146 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 147         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 150         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 151         ARM64_FTR_END,
 152 };
 153
 154 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
 155         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
 156         ARM64_FTR_END,
 157 };
 158
 159 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 162         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 163         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 164                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 167         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 168         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 172         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 173         ARM64_FTR_END,
 174 };
 175
 176 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 177         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 178         ARM64_FTR_END,
 179 };
 180
 181 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 182         /*
 183          * We already refuse to boot CPUs that don't support our configured
 184          * page size, so we can only detect mismatches for a page size other
 185          * than the one we're currently using. Unfortunately, SoCs like this
 186          * exist in the wild so, even though we don't like it, we'll have to go
 187          * along with it and treat them as non-strict.
 188          */
 189         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 190         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 191         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 192
 193         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 194         /* Linux shouldn't care about secure memory */
 195         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 198         /*
 199          * Differing PARange is fine as long as all peripherals and memory are mapped
 200          * within the minimum PARange of all CPUs
 201          */
 202         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 203         ARM64_FTR_END,
 204 };
 205
 206 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 207         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 208         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 210         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 211         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 212         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 213         ARM64_FTR_END,
 214 };
 215
 216 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 217         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 222         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 224         ARM64_FTR_END,
 225 };
 226
 227 static const struct arm64_ftr_bits ftr_ctr[] = {
 228         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 229         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 230         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 231         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 233         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 234         /*
 235          * Linux can handle differing I-cache policies. Userspace JITs will
 236          * make use of *minLine.
 237          * If we have differing I-cache policies, report it as the weakest - VIPT.
 238          */
 239         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 240         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 241         ARM64_FTR_END,
 242 };
 243
 244 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 245         .name           = "SYS_CTR_EL0",
 246         .ftr_bits       = ftr_ctr
 247 };
 248
 249 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 250         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 251         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 252         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 253         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 254         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 255         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 256         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 257         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 258         ARM64_FTR_END,
 259 };
 260
 261 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 266         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 267         /*
 268          * We can instantiate multiple PMU instances with different levels
 269          * of support.
 270          */
 271         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 272         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 273         ARM64_FTR_END,
 274 };
 275
 276 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 277         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 278         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 279         ARM64_FTR_END,
 280 };
 281
 282 static const struct arm64_ftr_bits ftr_dczid[] = {
 283         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 284         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 285         ARM64_FTR_END,
 286 };
 287
 288
 289 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 295         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 296         ARM64_FTR_END,
 297 };
 298
 299 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 301         ARM64_FTR_END,
 302 };
 303
 304 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 308         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 309         ARM64_FTR_END,
 310 };
 311
 312 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 313         /* [31:28] TraceFilt */
 314         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 315         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 320         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 321         ARM64_FTR_END,
 322 };
 323
 324 static const struct arm64_ftr_bits ftr_zcr[] = {
 325         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 326                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 327         ARM64_FTR_END,
 328 };
 329
 330 /*
 331  * Common ftr bits for a 32bit register with all hidden, strict
 332  * attributes, with 4bit feature fields and a default safe value of
 333  * 0. Covers the following 32bit registers:
 334  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 335  */
 336 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 339         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 342         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 343         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 344         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 345         ARM64_FTR_END,
 346 };
 347
 348 /* Table for a single 32bit feature value */
 349 static const struct arm64_ftr_bits ftr_single32[] = {
 350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 351         ARM64_FTR_END,
 352 };
 353
 354 static const struct arm64_ftr_bits ftr_raz[] = {
 355         ARM64_FTR_END,
 356 };
 357
 358 #define ARM64_FTR_REG(id, table) {              \
 359         .sys_id = id,                           \
 360         .reg =  &(struct arm64_ftr_reg){        \
 361                 .name = #id,                    \
 362                 .ftr_bits = &((table)[0]),      \
 363         }}
 364
 365 static const struct __ftr_reg_entry {
 366         u32                     sys_id;
 367         struct arm64_ftr_reg    *reg;
 368 } arm64_ftr_regs[] = {
 369
 370         /* Op1 = 0, CRn = 0, CRm = 1 */
 371         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 372         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 373         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 374         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 375         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 376         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 377         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 378
 379         /* Op1 = 0, CRn = 0, CRm = 2 */
 380         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 381         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 382         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 383         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 384         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 385         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 386         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 387
 388         /* Op1 = 0, CRn = 0, CRm = 3 */
 389         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 390         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 391         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 392
 393         /* Op1 = 0, CRn = 0, CRm = 4 */
 394         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 395         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 396         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
 397
 398         /* Op1 = 0, CRn = 0, CRm = 5 */
 399         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 400         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 401
 402         /* Op1 = 0, CRn = 0, CRm = 6 */
 403         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 404         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 405         ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
 406
 407         /* Op1 = 0, CRn = 0, CRm = 7 */
 408         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 409         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 410         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 411
 412         /* Op1 = 0, CRn = 1, CRm = 2 */
 413         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 414
 415         /* Op1 = 3, CRn = 0, CRm = 0 */
 416         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 417         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 418
 419         /* Op1 = 3, CRn = 14, CRm = 0 */
 420         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 421 };
 422
 423 static int search_cmp_ftr_reg(const void *id, const void *regp)
 424 {
 425         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 426 }
 427
 428 /*
 429  * get_arm64_ftr_reg - Lookup a feature register entry using its
 430  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 431  * ascending order of sys_id , we use binary search to find a matching
 432  * entry.
 433  *
 434  * returns - Upon success,  matching ftr_reg entry for id.
 435  *         - NULL on failure. It is upto the caller to decide
 436  *           the impact of a failure.
 437  */
 438 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 439 {
 440         const struct __ftr_reg_entry *ret;
 441
 442         ret = bsearch((const void *)(unsigned long)sys_id,
 443                         arm64_ftr_regs,
 444                         ARRAY_SIZE(arm64_ftr_regs),
 445                         sizeof(arm64_ftr_regs[0]),
 446                         search_cmp_ftr_reg);
 447         if (ret)
 448                 return ret->reg;
 449         return NULL;
 450 }
 451
 452 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 453                                s64 ftr_val)
 454 {
 455         u64 mask = arm64_ftr_mask(ftrp);
 456
 457         reg &= ~mask;
 458         reg |= (ftr_val << ftrp->shift) & mask;
 459         return reg;
 460 }
 461
 462 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 463                                 s64 cur)
 464 {
 465         s64 ret = 0;
 466
 467         switch (ftrp->type) {
 468         case FTR_EXACT:
 469                 ret = ftrp->safe_val;
 470                 break;
 471         case FTR_LOWER_SAFE:
 472                 ret = new < cur ? new : cur;
 473                 break;
 474         case FTR_HIGHER_OR_ZERO_SAFE:
 475                 if (!cur || !new)
 476                         break;
 477                 /* Fallthrough */
 478         case FTR_HIGHER_SAFE:
 479                 ret = new > cur ? new : cur;
 480                 break;
 481         default:
 482                 BUG();
 483         }
 484
 485         return ret;
 486 }
 487
 488 static void __init sort_ftr_regs(void)
 489 {
 490         int i;
 491
 492         /* Check that the array is sorted so that we can do the binary search */
 493         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 494                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 495 }
 496
 497 /*
 498  * Initialise the CPU feature register from Boot CPU values.
 499  * Also initiliases the strict_mask for the register.
 500  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 501  * RES0 for the system-wide value, and must strictly match.
 502  */
 503 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 504 {
 505         u64 val = 0;
 506         u64 strict_mask = ~0x0ULL;
 507         u64 user_mask = 0;
 508         u64 valid_mask = 0;
 509
 510         const struct arm64_ftr_bits *ftrp;
 511         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 512
 513         BUG_ON(!reg);
 514
 515         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 516                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 517                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 518
 519                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 520
 521                 valid_mask |= ftr_mask;
 522                 if (!ftrp->strict)
 523                         strict_mask &= ~ftr_mask;
 524                 if (ftrp->visible)
 525                         user_mask |= ftr_mask;
 526                 else
 527                         reg->user_val = arm64_ftr_set_value(ftrp,
 528                                                             reg->user_val,
 529                                                             ftrp->safe_val);
 530         }
 531
 532         val &= valid_mask;
 533
 534         reg->sys_val = val;
 535         reg->strict_mask = strict_mask;
 536         reg->user_mask = user_mask;
 537 }
 538
 539 extern const struct arm64_cpu_capabilities arm64_errata[];
 540 static void __init setup_boot_cpu_capabilities(void);
 541
 542 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 543 {
 544         /* Before we start using the tables, make sure it is sorted */
 545         sort_ftr_regs();
 546
 547         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 548         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 549         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 550         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 551         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 552         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 553         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 554         init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
 555         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 556         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 557         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 558         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 559         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 560         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 561
 562         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 563                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 564                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 565                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 566                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 567                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 568                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 569                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 570                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 571                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 572                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 573                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 574                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 575                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 576                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 577                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 578                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 579         }
 580
 581         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 582                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 583                 sve_init_vq_map();
 584         }
 585
 586         /*
 587          * Detect and enable early CPU capabilities based on the boot CPU,
 588          * after we have initialised the CPU feature infrastructure.
 589          */
 590         setup_boot_cpu_capabilities();
 591 }
 592
 593 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 594 {
 595         const struct arm64_ftr_bits *ftrp;
 596
 597         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 598                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 599                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 600
 601                 if (ftr_cur == ftr_new)
 602                         continue;
 603                 /* Find a safe value */
 604                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 605                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 606         }
 607
 608 }
 609
 610 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 611 {
 612         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 613
 614         BUG_ON(!regp);
 615         update_cpu_ftr_reg(regp, val);
 616         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 617                 return 0;
 618         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 619                         regp->name, boot, cpu, val);
 620         return 1;
 621 }
 622
 623 /*
 624  * Update system wide CPU feature registers with the values from a
 625  * non-boot CPU. Also performs SANITY checks to make sure that there
 626  * aren't any insane variations from that of the boot CPU.
 627  */
 628 void update_cpu_features(int cpu,
 629                          struct cpuinfo_arm64 *info,
 630                          struct cpuinfo_arm64 *boot)
 631 {
 632         int taint = 0;
 633
 634         /*
 635          * The kernel can handle differing I-cache policies, but otherwise
 636          * caches should look identical. Userspace JITs will make use of
 637          * *minLine.
 638          */
 639         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 640                                       info->reg_ctr, boot->reg_ctr);
 641
 642         /*
 643          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 644          * could result in too much or too little memory being zeroed if a
 645          * process is preempted and migrated between CPUs.
 646          */
 647         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 648                                       info->reg_dczid, boot->reg_dczid);
 649
 650         /* If different, timekeeping will be broken (especially with KVM) */
 651         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 652                                       info->reg_cntfrq, boot->reg_cntfrq);
 653
 654         /*
 655          * The kernel uses self-hosted debug features and expects CPUs to
 656          * support identical debug features. We presently need CTX_CMPs, WRPs,
 657          * and BRPs to be identical.
 658          * ID_AA64DFR1 is currently RES0.
 659          */
 660         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 661                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 662         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 663                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 664         /*
 665          * Even in big.LITTLE, processors should be identical instruction-set
 666          * wise.
 667          */
 668         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 669                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 670         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 671                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 672         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
 673                                       info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
 674
 675         /*
 676          * Differing PARange support is fine as long as all peripherals and
 677          * memory are mapped within the minimum PARange of all CPUs.
 678          * Linux should not care about secure memory.
 679          */
 680         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 681                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 682         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 683                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 684         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 685                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 686
 687         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 688                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 689         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 690                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 691
 692         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 693                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 694
 695         /*
 696          * If we have AArch32, we care about 32-bit features for compat.
 697          * If the system doesn't support AArch32, don't update them.
 698          */
 699         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 700                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 701
 702                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 703                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 704                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 705                                         info->reg_id_isar0, boot->reg_id_isar0);
 706                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 707                                         info->reg_id_isar1, boot->reg_id_isar1);
 708                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 709                                         info->reg_id_isar2, boot->reg_id_isar2);
 710                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 711                                         info->reg_id_isar3, boot->reg_id_isar3);
 712                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 713                                         info->reg_id_isar4, boot->reg_id_isar4);
 714                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 715                                         info->reg_id_isar5, boot->reg_id_isar5);
 716
 717                 /*
 718                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 719                  * ACTLR formats could differ across CPUs and therefore would have to
 720                  * be trapped for virtualization anyway.
 721                  */
 722                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 723                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 724                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 725                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 726                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 727                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 728                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 729                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 730                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 731                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 732                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 733                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 734                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 735                                         info->reg_mvfr0, boot->reg_mvfr0);
 736                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 737                                         info->reg_mvfr1, boot->reg_mvfr1);
 738                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 739                                         info->reg_mvfr2, boot->reg_mvfr2);
 740         }
 741
 742         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 743                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 744                                         info->reg_zcr, boot->reg_zcr);
 745
 746                 /* Probe vector lengths, unless we already gave up on SVE */
 747                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 748                     !sys_caps_initialised)
 749                         sve_update_vq_map();
 750         }
 751
 752         /*
 753          * Mismatched CPU features are a recipe for disaster. Don't even
 754          * pretend to support them.
 755          */
 756         if (taint) {
 757                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 758                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 759         }
 760 }
 761
 762 u64 read_sanitised_ftr_reg(u32 id)
 763 {
 764         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 765
 766         /* We shouldn't get a request for an unsupported register */
 767         BUG_ON(!regp);
 768         return regp->sys_val;
 769 }
 770
 771 #define read_sysreg_case(r)     \
 772         case r:         return read_sysreg_s(r)
 773
 774 /*
 775  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 776  * Read the system register on the current CPU
 777  */
 778 static u64 __read_sysreg_by_encoding(u32 sys_id)
 779 {
 780         switch (sys_id) {
 781         read_sysreg_case(SYS_ID_PFR0_EL1);
 782         read_sysreg_case(SYS_ID_PFR1_EL1);
 783         read_sysreg_case(SYS_ID_DFR0_EL1);
 784         read_sysreg_case(SYS_ID_MMFR0_EL1);
 785         read_sysreg_case(SYS_ID_MMFR1_EL1);
 786         read_sysreg_case(SYS_ID_MMFR2_EL1);
 787         read_sysreg_case(SYS_ID_MMFR3_EL1);
 788         read_sysreg_case(SYS_ID_ISAR0_EL1);
 789         read_sysreg_case(SYS_ID_ISAR1_EL1);
 790         read_sysreg_case(SYS_ID_ISAR2_EL1);
 791         read_sysreg_case(SYS_ID_ISAR3_EL1);
 792         read_sysreg_case(SYS_ID_ISAR4_EL1);
 793         read_sysreg_case(SYS_ID_ISAR5_EL1);
 794         read_sysreg_case(SYS_MVFR0_EL1);
 795         read_sysreg_case(SYS_MVFR1_EL1);
 796         read_sysreg_case(SYS_MVFR2_EL1);
 797
 798         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 799         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 800         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 801         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 802         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 803         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 804         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 805         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 806         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 807         read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
 808
 809         read_sysreg_case(SYS_CNTFRQ_EL0);
 810         read_sysreg_case(SYS_CTR_EL0);
 811         read_sysreg_case(SYS_DCZID_EL0);
 812
 813         default:
 814                 BUG();
 815                 return 0;
 816         }
 817 }
 818
 819 #include <linux/irqchip/arm-gic-v3.h>
 820
 821 static bool
 822 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 823 {
 824         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 825
 826         return val >= entry->min_field_value;
 827 }
 828
 829 static bool
 830 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 831 {
 832         u64 val;
 833
 834         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 835         if (scope == SCOPE_SYSTEM)
 836                 val = read_sanitised_ftr_reg(entry->sys_reg);
 837         else
 838                 val = __read_sysreg_by_encoding(entry->sys_reg);
 839
 840         return feature_matches(val, entry);
 841 }
 842
 843 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 844 {
 845         bool has_sre;
 846
 847         if (!has_cpuid_feature(entry, scope))
 848                 return false;
 849
 850         has_sre = gic_enable_sre();
 851         if (!has_sre)
 852                 pr_warn_once("%s present but disabled by higher exception level\n",
 853                              entry->desc);
 854
 855         return has_sre;
 856 }
 857
 858 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 859 {
 860         u32 midr = read_cpuid_id();
 861
 862         /* Cavium ThunderX pass 1.x and 2.x */
 863         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 864                 MIDR_CPU_VAR_REV(0, 0),
 865                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 866 }
 867
 868 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 869 {
 870         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 871
 872         return cpuid_feature_extract_signed_field(pfr0,
 873                                         ID_AA64PFR0_FP_SHIFT) < 0;
 874 }
 875
 876 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 877                           int scope)
 878 {
 879         u64 ctr;
 880
 881         if (scope == SCOPE_SYSTEM)
 882                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 883         else
 884                 ctr = read_cpuid_cachetype();
 885
 886         return ctr & BIT(CTR_IDC_SHIFT);
 887 }
 888
 889 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 890                           int scope)
 891 {
 892         u64 ctr;
 893
 894         if (scope == SCOPE_SYSTEM)
 895                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 896         else
 897                 ctr = read_cpuid_cachetype();
 898
 899         return ctr & BIT(CTR_DIC_SHIFT);
 900 }
 901
 902 static bool __meltdown_safe = true;
 903 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 904
 905 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 906                                 int scope)
 907 {
 908         /* List of CPUs that are not vulnerable and don't need KPTI */
 909         static const struct midr_range kpti_safe_list[] = {
 910                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 911                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 912                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 913                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 914                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 915                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 916                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 917                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 918                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 919                 { /* sentinel */ }
 920         };
 921         char const *str = "kpti command line option";
 922         bool meltdown_safe;
 923
 924         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 925
 926         /* Defer to CPU feature registers */
 927         if (has_cpuid_feature(entry, scope))
 928                 meltdown_safe = true;
 929
 930         if (!meltdown_safe)
 931                 __meltdown_safe = false;
 932
 933         /*
 934          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 935          * ThunderX leads to apparent I-cache corruption of kernel text, which
 936          * ends as well as you might imagine. Don't even try.
 937          */
 938         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
 939                 str = "ARM64_WORKAROUND_CAVIUM_27456";
 940                 __kpti_forced = -1;
 941         }
 942
 943         /* Useful for KASLR robustness */
 944         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
 945                 if (!__kpti_forced) {
 946                         str = "KASLR";
 947                         __kpti_forced = 1;
 948                 }
 949         }
 950
 951         if (cpu_mitigations_off() && !__kpti_forced) {
 952                 str = "mitigations=off";
 953                 __kpti_forced = -1;
 954         }
 955
 956         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
 957                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
 958                 return false;
 959         }
 960
 961         /* Forced? */
 962         if (__kpti_forced) {
 963                 pr_info_once("kernel page table isolation forced %s by %s\n",
 964                              __kpti_forced > 0 ? "ON" : "OFF", str);
 965                 return __kpti_forced > 0;
 966         }
 967
 968         return !meltdown_safe;
 969 }
 970
 971 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 972 static void
 973 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
 974 {
 975         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
 976         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
 977         kpti_remap_fn *remap_fn;
 978
 979         static bool kpti_applied = false;
 980         int cpu = smp_processor_id();
 981
 982         if (__this_cpu_read(this_cpu_vector) == vectors) {
 983                 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
 984
 985                 __this_cpu_write(this_cpu_vector, v);
 986         }
 987
 988         if (kpti_applied)
 989                 return;
 990
 991         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
 992
 993         cpu_install_idmap();
 994         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
 995         cpu_uninstall_idmap();
 996
 997         if (!cpu)
 998                 kpti_applied = true;
 999
1000         return;
1001 }
1002 #else
1003 static void
1004 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1005 {
1006 }
1007 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1008
1009 static int __init parse_kpti(char *str)
1010 {
1011         bool enabled;
1012         int ret = strtobool(str, &enabled);
1013
1014         if (ret)
1015                 return ret;
1016
1017         __kpti_forced = enabled ? 1 : -1;
1018         return 0;
1019 }
1020 early_param("kpti", parse_kpti);
1021
1022 #ifdef CONFIG_ARM64_HW_AFDBM
1023 static inline void __cpu_enable_hw_dbm(void)
1024 {
1025         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1026
1027         write_sysreg(tcr, tcr_el1);
1028         isb();
1029 }
1030
1031 static bool cpu_has_broken_dbm(void)
1032 {
1033         /* List of CPUs which have broken DBM support. */
1034         static const struct midr_range cpus[] = {
1035 #ifdef CONFIG_ARM64_ERRATUM_1024718
1036                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1037 #endif
1038                 {},
1039         };
1040
1041         return is_midr_in_range_list(read_cpuid_id(), cpus);
1042 }
1043
1044 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1045 {
1046         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1047                !cpu_has_broken_dbm();
1048 }
1049
1050 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1051 {
1052         if (cpu_can_use_dbm(cap))
1053                 __cpu_enable_hw_dbm();
1054 }
1055
1056 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1057                        int __unused)
1058 {
1059         static bool detected = false;
1060         /*
1061          * DBM is a non-conflicting feature. i.e, the kernel can safely
1062          * run a mix of CPUs with and without the feature. So, we
1063          * unconditionally enable the capability to allow any late CPU
1064          * to use the feature. We only enable the control bits on the
1065          * CPU, if it actually supports.
1066          *
1067          * We have to make sure we print the "feature" detection only
1068          * when at least one CPU actually uses it. So check if this CPU
1069          * can actually use it and print the message exactly once.
1070          *
1071          * This is safe as all CPUs (including secondary CPUs - due to the
1072          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1073          * goes through the "matches" check exactly once. Also if a CPU
1074          * matches the criteria, it is guaranteed that the CPU will turn
1075          * the DBM on, as the capability is unconditionally enabled.
1076          */
1077         if (!detected && cpu_can_use_dbm(cap)) {
1078                 detected = true;
1079                 pr_info("detected: Hardware dirty bit management\n");
1080         }
1081
1082         return true;
1083 }
1084
1085 #endif
1086
1087 #ifdef CONFIG_ARM64_VHE
1088 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1089 {
1090         return is_kernel_in_hyp_mode();
1091 }
1092
1093 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1094 {
1095         /*
1096          * Copy register values that aren't redirected by hardware.
1097          *
1098          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1099          * this value to tpidr_el2 before we patch the code. Once we've done
1100          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1101          * do anything here.
1102          */
1103         if (!alternatives_applied)
1104                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1105 }
1106 #endif
1107
1108 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1109 {
1110         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1111
1112         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1113         WARN_ON(val & (7 << 27 | 7 << 21));
1114 }
1115
1116 #ifdef CONFIG_ARM64_SSBD
1117 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1118 {
1119         if (user_mode(regs))
1120                 return 1;
1121
1122         if (instr & BIT(CRm_shift))
1123                 regs->pstate |= PSR_SSBS_BIT;
1124         else
1125                 regs->pstate &= ~PSR_SSBS_BIT;
1126
1127         arm64_skip_faulting_instruction(regs, 4);
1128         return 0;
1129 }
1130
1131 static struct undef_hook ssbs_emulation_hook = {
1132         .instr_mask     = ~(1U << CRm_shift),
1133         .instr_val      = 0xd500001f | REG_PSTATE_SSBS_IMM,
1134         .fn             = ssbs_emulation_handler,
1135 };
1136
1137 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1138 {
1139         static bool undef_hook_registered = false;
1140         static DEFINE_SPINLOCK(hook_lock);
1141
1142         spin_lock(&hook_lock);
1143         if (!undef_hook_registered) {
1144                 register_undef_hook(&ssbs_emulation_hook);
1145                 undef_hook_registered = true;
1146         }
1147         spin_unlock(&hook_lock);
1148
1149         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1150                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1151                 arm64_set_ssbd_mitigation(false);
1152         } else {
1153                 arm64_set_ssbd_mitigation(true);
1154         }
1155 }
1156 #endif /* CONFIG_ARM64_SSBD */
1157
1158 static void elf_hwcap_fixup(void)
1159 {
1160 #ifdef CONFIG_ARM64_ERRATUM_1742098
1161         if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
1162                 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
1163 #endif /* ARM64_ERRATUM_1742098 */
1164 }
1165
1166 static const struct arm64_cpu_capabilities arm64_features[] = {
1167         {
1168                 .desc = "GIC system register CPU interface",
1169                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1170                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1171                 .matches = has_useable_gicv3_cpuif,
1172                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1173                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1174                 .sign = FTR_UNSIGNED,
1175                 .min_field_value = 1,
1176         },
1177 #ifdef CONFIG_ARM64_PAN
1178         {
1179                 .desc = "Privileged Access Never",
1180                 .capability = ARM64_HAS_PAN,
1181                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1182                 .matches = has_cpuid_feature,
1183                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1184                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1185                 .sign = FTR_UNSIGNED,
1186                 .min_field_value = 1,
1187                 .cpu_enable = cpu_enable_pan,
1188         },
1189 #endif /* CONFIG_ARM64_PAN */
1190 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1191         {
1192                 .desc = "LSE atomic instructions",
1193                 .capability = ARM64_HAS_LSE_ATOMICS,
1194                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1195                 .matches = has_cpuid_feature,
1196                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1197                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1198                 .sign = FTR_UNSIGNED,
1199                 .min_field_value = 2,
1200         },
1201 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1202         {
1203                 .desc = "Software prefetching using PRFM",
1204                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1205                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1206                 .matches = has_no_hw_prefetch,
1207         },
1208 #ifdef CONFIG_ARM64_UAO
1209         {
1210                 .desc = "User Access Override",
1211                 .capability = ARM64_HAS_UAO,
1212                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1213                 .matches = has_cpuid_feature,
1214                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1215                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1216                 .min_field_value = 1,
1217                 /*
1218                  * We rely on stop_machine() calling uao_thread_switch() to set
1219                  * UAO immediately after patching.
1220                  */
1221         },
1222 #endif /* CONFIG_ARM64_UAO */
1223 #ifdef CONFIG_ARM64_PAN
1224         {
1225                 .capability = ARM64_ALT_PAN_NOT_UAO,
1226                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1227                 .matches = cpufeature_pan_not_uao,
1228         },
1229 #endif /* CONFIG_ARM64_PAN */
1230 #ifdef CONFIG_ARM64_VHE
1231         {
1232                 .desc = "Virtualization Host Extensions",
1233                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1234                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1235                 .matches = runs_at_el2,
1236                 .cpu_enable = cpu_copy_el2regs,
1237         },
1238 #endif  /* CONFIG_ARM64_VHE */
1239         {
1240                 .desc = "32-bit EL0 Support",
1241                 .capability = ARM64_HAS_32BIT_EL0,
1242                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1243                 .matches = has_cpuid_feature,
1244                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1245                 .sign = FTR_UNSIGNED,
1246                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1247                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1248         },
1249         {
1250                 .desc = "Kernel page table isolation (KPTI)",
1251                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1252                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1253                 /*
1254                  * The ID feature fields below are used to indicate that
1255                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1256                  * more details.
1257                  */
1258                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1259                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1260                 .min_field_value = 1,
1261                 .matches = unmap_kernel_at_el0,
1262                 .cpu_enable = kpti_install_ng_mappings,
1263         },
1264         {
1265                 /* FP/SIMD is not implemented */
1266                 .capability = ARM64_HAS_NO_FPSIMD,
1267                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1268                 .min_field_value = 0,
1269                 .matches = has_no_fpsimd,
1270         },
1271 #ifdef CONFIG_ARM64_PMEM
1272         {
1273                 .desc = "Data cache clean to Point of Persistence",
1274                 .capability = ARM64_HAS_DCPOP,
1275                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1276                 .matches = has_cpuid_feature,
1277                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1278                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1279                 .min_field_value = 1,
1280         },
1281 #endif
1282 #ifdef CONFIG_ARM64_SVE
1283         {
1284                 .desc = "Scalable Vector Extension",
1285                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1286                 .capability = ARM64_SVE,
1287                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1288                 .sign = FTR_UNSIGNED,
1289                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1290                 .min_field_value = ID_AA64PFR0_SVE,
1291                 .matches = has_cpuid_feature,
1292                 .cpu_enable = sve_kernel_enable,
1293         },
1294 #endif /* CONFIG_ARM64_SVE */
1295 #ifdef CONFIG_ARM64_RAS_EXTN
1296         {
1297                 .desc = "RAS Extension Support",
1298                 .capability = ARM64_HAS_RAS_EXTN,
1299                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1300                 .matches = has_cpuid_feature,
1301                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1302                 .sign = FTR_UNSIGNED,
1303                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1304                 .min_field_value = ID_AA64PFR0_RAS_V1,
1305                 .cpu_enable = cpu_clear_disr,
1306         },
1307 #endif /* CONFIG_ARM64_RAS_EXTN */
1308         {
1309                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1310                 .capability = ARM64_HAS_CACHE_IDC,
1311                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1312                 .matches = has_cache_idc,
1313         },
1314         {
1315                 .desc = "Instruction cache invalidation not required for I/D coherence",
1316                 .capability = ARM64_HAS_CACHE_DIC,
1317                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1318                 .matches = has_cache_dic,
1319         },
1320         {
1321                 .desc = "Stage-2 Force Write-Back",
1322                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1323                 .capability = ARM64_HAS_STAGE2_FWB,
1324                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1325                 .sign = FTR_UNSIGNED,
1326                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1327                 .min_field_value = 1,
1328                 .matches = has_cpuid_feature,
1329                 .cpu_enable = cpu_has_fwb,
1330         },
1331 #ifdef CONFIG_ARM64_HW_AFDBM
1332         {
1333                 /*
1334                  * Since we turn this on always, we don't want the user to
1335                  * think that the feature is available when it may not be.
1336                  * So hide the description.
1337                  *
1338                  * .desc = "Hardware pagetable Dirty Bit Management",
1339                  *
1340                  */
1341                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1342                 .capability = ARM64_HW_DBM,
1343                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1344                 .sign = FTR_UNSIGNED,
1345                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1346                 .min_field_value = 2,
1347                 .matches = has_hw_dbm,
1348                 .cpu_enable = cpu_enable_hw_dbm,
1349         },
1350 #endif
1351 #ifdef CONFIG_ARM64_SSBD
1352         {
1353                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1354                 .capability = ARM64_SSBS,
1355                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1356                 .matches = has_cpuid_feature,
1357                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1358                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1359                 .sign = FTR_UNSIGNED,
1360                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1361                 .cpu_enable = cpu_enable_ssbs,
1362         },
1363 #endif
1364         {},
1365 };
1366
1367
1368 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)             \
1369                 .matches = has_cpuid_feature,                   \
1370                 .sys_reg = reg,                                 \
1371                 .field_pos = field,                             \
1372                 .sign = s,                                      \
1373                 .min_field_value = min_value,                   \
1374
1375 #define __HWCAP_CAP(name, cap_type, cap)                        \
1376                 .desc = name,                                   \
1377                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,            \
1378                 .hwcap_type = cap_type,                         \
1379                 .hwcap = cap,                                   \
1380
1381 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)      \
1382         {                                                       \
1383                 __HWCAP_CAP(#cap, cap_type, cap)                \
1384                 HWCAP_CPUID_MATCH(reg, field, s, min_value)     \
1385         }
1386
1387 #define HWCAP_CAP_MATCH(match, cap_type, cap)                   \
1388         {                                                       \
1389                 __HWCAP_CAP(#cap, cap_type, cap)                \
1390                 .matches = match,                               \
1391         }
1392
1393 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1394         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1395         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1396         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1397         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1398         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1399         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1400         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1401         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1402         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1403         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1404         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1405         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1406         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1407         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
1408         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1409         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1410         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1411         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1412         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
1413         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1414         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1415         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1416         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1417         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1418         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
1419 #ifdef CONFIG_ARM64_SVE
1420         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1421 #endif
1422         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
1423         {},
1424 };
1425
1426 #ifdef CONFIG_COMPAT
1427 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1428 {
1429         /*
1430          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1431          * in line with that of arm32 as in vfp_init(). We make sure that the
1432          * check is future proof, by making sure value is non-zero.
1433          */
1434         u32 mvfr1;
1435
1436         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1437         if (scope == SCOPE_SYSTEM)
1438                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1439         else
1440                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1441
1442         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1443                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1444                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1445 }
1446 #endif
1447
1448 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1449 #ifdef CONFIG_COMPAT
1450         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1451         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1452         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1453         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1454         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1455         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1456         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1457         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1458         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1459         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1460 #endif
1461         {},
1462 };
1463
1464 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1465 {
1466         switch (cap->hwcap_type) {
1467         case CAP_HWCAP:
1468                 elf_hwcap |= cap->hwcap;
1469                 break;
1470 #ifdef CONFIG_COMPAT
1471         case CAP_COMPAT_HWCAP:
1472                 compat_elf_hwcap |= (u32)cap->hwcap;
1473                 break;
1474         case CAP_COMPAT_HWCAP2:
1475                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1476                 break;
1477 #endif
1478         default:
1479                 WARN_ON(1);
1480                 break;
1481         }
1482 }
1483
1484 /* Check if we have a particular HWCAP enabled */
1485 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1486 {
1487         bool rc;
1488
1489         switch (cap->hwcap_type) {
1490         case CAP_HWCAP:
1491                 rc = (elf_hwcap & cap->hwcap) != 0;
1492                 break;
1493 #ifdef CONFIG_COMPAT
1494         case CAP_COMPAT_HWCAP:
1495                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1496                 break;
1497         case CAP_COMPAT_HWCAP2:
1498                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1499                 break;
1500 #endif
1501         default:
1502                 WARN_ON(1);
1503                 rc = false;
1504         }
1505
1506         return rc;
1507 }
1508
1509 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1510 {
1511         /* We support emulation of accesses to CPU ID feature registers */
1512         elf_hwcap |= HWCAP_CPUID;
1513         for (; hwcaps->matches; hwcaps++)
1514                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1515                         cap_set_elf_hwcap(hwcaps);
1516 }
1517
1518 /*
1519  * Check if the current CPU has a given feature capability.
1520  * Should be called from non-preemptible context.
1521  */
1522 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1523                                unsigned int cap)
1524 {
1525         const struct arm64_cpu_capabilities *caps;
1526
1527         if (WARN_ON(preemptible()))
1528                 return false;
1529
1530         for (caps = cap_array; caps->matches; caps++)
1531                 if (caps->capability == cap)
1532                         return caps->matches(caps, SCOPE_LOCAL_CPU);
1533
1534         return false;
1535 }
1536
1537 static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1538                                       u16 scope_mask, const char *info)
1539 {
1540         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1541         for (; caps->matches; caps++) {
1542                 if (!(caps->type & scope_mask) ||
1543                     !caps->matches(caps, cpucap_default_scope(caps)))
1544                         continue;
1545
1546                 if (!cpus_have_cap(caps->capability) && caps->desc)
1547                         pr_info("%s %s\n", info, caps->desc);
1548                 cpus_set_cap(caps->capability);
1549         }
1550 }
1551
1552 static void update_cpu_capabilities(u16 scope_mask)
1553 {
1554         __update_cpu_capabilities(arm64_errata, scope_mask,
1555                                   "enabling workaround for");
1556         __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
1557 }
1558
1559 static int __enable_cpu_capability(void *arg)
1560 {
1561         const struct arm64_cpu_capabilities *cap = arg;
1562
1563         cap->cpu_enable(cap);
1564         return 0;
1565 }
1566
1567 /*
1568  * Run through the enabled capabilities and enable() it on all active
1569  * CPUs
1570  */
1571 static void __init
1572 __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1573                           u16 scope_mask)
1574 {
1575         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1576         for (; caps->matches; caps++) {
1577                 unsigned int num = caps->capability;
1578
1579                 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
1580                         continue;
1581
1582                 /* Ensure cpus_have_const_cap(num) works */
1583                 static_branch_enable(&cpu_hwcap_keys[num]);
1584
1585                 if (caps->cpu_enable) {
1586                         /*
1587                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1588                          * before any secondary CPU boots. Thus, each secondary
1589                          * will enable the capability as appropriate via
1590                          * check_local_cpu_capabilities(). The only exception is
1591                          * the boot CPU, for which the capability must be
1592                          * enabled here. This approach avoids costly
1593                          * stop_machine() calls for this case.
1594                          *
1595                          * Otherwise, use stop_machine() as it schedules the
1596                          * work allowing us to modify PSTATE, instead of
1597                          * on_each_cpu() which uses an IPI, giving us a PSTATE
1598                          * that disappears when we return.
1599                          */
1600                         if (scope_mask & SCOPE_BOOT_CPU)
1601                                 caps->cpu_enable(caps);
1602                         else
1603                                 stop_machine(__enable_cpu_capability,
1604                                              (void *)caps, cpu_online_mask);
1605                 }
1606         }
1607 }
1608
1609 static void __init enable_cpu_capabilities(u16 scope_mask)
1610 {
1611         __enable_cpu_capabilities(arm64_errata, scope_mask);
1612         __enable_cpu_capabilities(arm64_features, scope_mask);
1613 }
1614
1615 /*
1616  * Run through the list of capabilities to check for conflicts.
1617  * If the system has already detected a capability, take necessary
1618  * action on this CPU.
1619  *
1620  * Returns "false" on conflicts.
1621  */
1622 static bool
1623 __verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps,
1624                         u16 scope_mask)
1625 {
1626         bool cpu_has_cap, system_has_cap;
1627
1628         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1629
1630         for (; caps->matches; caps++) {
1631                 if (!(caps->type & scope_mask))
1632                         continue;
1633
1634                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1635                 system_has_cap = cpus_have_cap(caps->capability);
1636
1637                 if (system_has_cap) {
1638                         /*
1639                          * Check if the new CPU misses an advertised feature,
1640                          * which is not safe to miss.
1641                          */
1642                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1643                                 break;
1644                         /*
1645                          * We have to issue cpu_enable() irrespective of
1646                          * whether the CPU has it or not, as it is enabeld
1647                          * system wide. It is upto the call back to take
1648                          * appropriate action on this CPU.
1649                          */
1650                         if (caps->cpu_enable)
1651                                 caps->cpu_enable(caps);
1652                 } else {
1653                         /*
1654                          * Check if the CPU has this capability if it isn't
1655                          * safe to have when the system doesn't.
1656                          */
1657                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1658                                 break;
1659                 }
1660         }
1661
1662         if (caps->matches) {
1663                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1664                         smp_processor_id(), caps->capability,
1665                         caps->desc, system_has_cap, cpu_has_cap);
1666                 return false;
1667         }
1668
1669         return true;
1670 }
1671
1672 static bool verify_local_cpu_caps(u16 scope_mask)
1673 {
1674         return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
1675                __verify_local_cpu_caps(arm64_features, scope_mask);
1676 }
1677
1678 /*
1679  * Check for CPU features that are used in early boot
1680  * based on the Boot CPU value.
1681  */
1682 static void check_early_cpu_features(void)
1683 {
1684         verify_cpu_asid_bits();
1685         /*
1686          * Early features are used by the kernel already. If there
1687          * is a conflict, we cannot proceed further.
1688          */
1689         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1690                 cpu_panic_kernel();
1691 }
1692
1693 static void
1694 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1695 {
1696
1697         for (; caps->matches; caps++)
1698                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1699                         pr_crit("CPU%d: missing HWCAP: %s\n",
1700                                         smp_processor_id(), caps->desc);
1701                         cpu_die_early();
1702                 }
1703 }
1704
1705 static void verify_sve_features(void)
1706 {
1707         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1708         u64 zcr = read_zcr_features();
1709
1710         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1711         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1712
1713         if (len < safe_len || sve_verify_vq_map()) {
1714                 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1715                         smp_processor_id());
1716                 cpu_die_early();
1717         }
1718
1719         /* Add checks on other ZCR bits here if necessary */
1720 }
1721
1722
1723 /*
1724  * Run through the enabled system capabilities and enable() it on this CPU.
1725  * The capabilities were decided based on the available CPUs at the boot time.
1726  * Any new CPU should match the system wide status of the capability. If the
1727  * new CPU doesn't have a capability which the system now has enabled, we
1728  * cannot do anything to fix it up and could cause unexpected failures. So
1729  * we park the CPU.
1730  */
1731 static void verify_local_cpu_capabilities(void)
1732 {
1733         /*
1734          * The capabilities with SCOPE_BOOT_CPU are checked from
1735          * check_early_cpu_features(), as they need to be verified
1736          * on all secondary CPUs.
1737          */
1738         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1739                 cpu_die_early();
1740
1741         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1742
1743         if (system_supports_32bit_el0())
1744                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1745
1746         if (system_supports_sve())
1747                 verify_sve_features();
1748 }
1749
1750 void check_local_cpu_capabilities(void)
1751 {
1752         /*
1753          * All secondary CPUs should conform to the early CPU features
1754          * in use by the kernel based on boot CPU.
1755          */
1756         check_early_cpu_features();
1757
1758         /*
1759          * If we haven't finalised the system capabilities, this CPU gets
1760          * a chance to update the errata work arounds and local features.
1761          * Otherwise, this CPU should verify that it has all the system
1762          * advertised capabilities.
1763          */
1764         if (!sys_caps_initialised)
1765                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1766         else
1767                 verify_local_cpu_capabilities();
1768 }
1769
1770 static void __init setup_boot_cpu_capabilities(void)
1771 {
1772         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1773         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1774         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1775         enable_cpu_capabilities(SCOPE_BOOT_CPU);
1776 }
1777
1778 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1779 EXPORT_SYMBOL(arm64_const_caps_ready);
1780
1781 static void __init mark_const_caps_ready(void)
1782 {
1783         static_branch_enable(&arm64_const_caps_ready);
1784 }
1785
1786 extern const struct arm64_cpu_capabilities arm64_errata[];
1787
1788 bool this_cpu_has_cap(unsigned int cap)
1789 {
1790         return (__this_cpu_has_cap(arm64_features, cap) ||
1791                 __this_cpu_has_cap(arm64_errata, cap));
1792 }
1793
1794 static void __init setup_system_capabilities(void)
1795 {
1796         /*
1797          * We have finalised the system-wide safe feature
1798          * registers, finalise the capabilities that depend
1799          * on it. Also enable all the available capabilities,
1800          * that are not enabled already.
1801          */
1802         update_cpu_capabilities(SCOPE_SYSTEM);
1803         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
1804 }
1805
1806 void __init setup_cpu_features(void)
1807 {
1808         u32 cwg;
1809
1810         setup_system_capabilities();
1811         mark_const_caps_ready();
1812         setup_elf_hwcaps(arm64_elf_hwcaps);
1813
1814         if (system_supports_32bit_el0()) {
1815                 setup_elf_hwcaps(compat_elf_hwcaps);
1816                 elf_hwcap_fixup();
1817         }
1818
1819         if (system_uses_ttbr0_pan())
1820                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1821
1822         sve_setup();
1823         minsigstksz_setup();
1824
1825         /* Advertise that we have computed the system capabilities */
1826         set_sys_caps_initialised();
1827
1828         /*
1829          * Check for sane CTR_EL0.CWG value.
1830          */
1831         cwg = cache_type_cwg();
1832         if (!cwg)
1833                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1834                         ARCH_DMA_MINALIGN);
1835 }
1836
1837 static bool __maybe_unused
1838 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1839 {
1840         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1841 }
1842
1843 /*
1844  * We emulate only the following system register space.
1845  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1846  * See Table C5-6 System instruction encodings for System register accesses,
1847  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1848  */
1849 static inline bool __attribute_const__ is_emulated(u32 id)
1850 {
1851         return (sys_reg_Op0(id) == 0x3 &&
1852                 sys_reg_CRn(id) == 0x0 &&
1853                 sys_reg_Op1(id) == 0x0 &&
1854                 (sys_reg_CRm(id) == 0 ||
1855                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1856 }
1857
1858 /*
1859  * With CRm == 0, reg should be one of :
1860  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1861  */
1862 static inline int emulate_id_reg(u32 id, u64 *valp)
1863 {
1864         switch (id) {
1865         case SYS_MIDR_EL1:
1866                 *valp = read_cpuid_id();
1867                 break;
1868         case SYS_MPIDR_EL1:
1869                 *valp = SYS_MPIDR_SAFE_VAL;
1870                 break;
1871         case SYS_REVIDR_EL1:
1872                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1873                 *valp = 0;
1874                 break;
1875         default:
1876                 return -EINVAL;
1877         }
1878
1879         return 0;
1880 }
1881
1882 static int emulate_sys_reg(u32 id, u64 *valp)
1883 {
1884         struct arm64_ftr_reg *regp;
1885
1886         if (!is_emulated(id))
1887                 return -EINVAL;
1888
1889         if (sys_reg_CRm(id) == 0)
1890                 return emulate_id_reg(id, valp);
1891
1892         regp = get_arm64_ftr_reg(id);
1893         if (regp)
1894                 *valp = arm64_ftr_reg_user_value(regp);
1895         else
1896                 /*
1897                  * The untracked registers are either IMPLEMENTATION DEFINED
1898                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
1899                  */
1900                 *valp = 0;
1901         return 0;
1902 }
1903
1904 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1905 {
1906         int rc;
1907         u32 sys_reg, dst;
1908         u64 val;
1909
1910         /*
1911          * sys_reg values are defined as used in mrs/msr instruction.
1912          * shift the imm value to get the encoding.
1913          */
1914         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1915         rc = emulate_sys_reg(sys_reg, &val);
1916         if (!rc) {
1917                 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1918                 pt_regs_write_reg(regs, dst, val);
1919                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1920         }
1921
1922         return rc;
1923 }
1924
1925 static struct undef_hook mrs_hook = {
1926         .instr_mask = 0xfff00000,
1927         .instr_val  = 0xd5300000,
1928         .pstate_mask = PSR_AA32_MODE_MASK,
1929         .pstate_val = PSR_MODE_EL0t,
1930         .fn = emulate_mrs,
1931 };
1932
1933 static int __init enable_mrs_emulation(void)
1934 {
1935         register_undef_hook(&mrs_hook);
1936         return 0;
1937 }
1938
1939 core_initcall(enable_mrs_emulation);
1940
1941 void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1942 {
1943         /* Firmware may have left a deferred SError in this register. */
1944         write_sysreg_s(0, SYS_DISR_EL1);
1945 }
1946
1947 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
1948                           char *buf)
1949 {
1950         if (__meltdown_safe)
1951                 return sprintf(buf, "Not affected\n");
1952
1953         if (arm64_kernel_unmapped_at_el0())
1954                 return sprintf(buf, "Mitigation: PTI\n");
1955
1956         return sprintf(buf, "Vulnerable\n");
1957 }