1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_sap_in_defs_asm_h
3 #define __iop_sap_in_defs_asm_h
6 * This file is autogenerated from
9 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
10 * Any changes here will be lost.
12 * -*- buffer-read-only: t -*-
16 #define REG_FIELD( scope, reg, field, value ) \
17 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
18 #define REG_FIELD_X_( value, shift ) ((value) << shift)
22 #define REG_STATE( scope, reg, field, symbolic_value ) \
23 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE_X_( k, shift ) (k << shift)
28 #define REG_MASK( scope, reg, field ) \
29 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
34 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
38 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
42 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
43 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
47 #define REG_ADDR_VECT( scope, inst, reg, index ) \
48 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
49 STRIDE_##scope##_##reg )
50 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
51 ((inst) + offs + (index) * stride)
54 #define STRIDE_iop_sap_in_rw_bus_byte 4
55 /* Register rw_bus_byte, scope iop_sap_in, type rw */
56 #define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
57 #define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
58 #define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
59 #define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
60 #define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
61 #define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
62 #define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
63 #define reg_iop_sap_in_rw_bus_byte___delay___width 2
64 #define reg_iop_sap_in_rw_bus_byte_offset 0
66 #define STRIDE_iop_sap_in_rw_gio 4
67 /* Register rw_gio, scope iop_sap_in, type rw */
68 #define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
69 #define reg_iop_sap_in_rw_gio___sync_sel___width 2
70 #define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
71 #define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
72 #define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
73 #define reg_iop_sap_in_rw_gio___sync_edge___width 2
74 #define reg_iop_sap_in_rw_gio___delay___lsb 7
75 #define reg_iop_sap_in_rw_gio___delay___width 2
76 #define reg_iop_sap_in_rw_gio___logic___lsb 9
77 #define reg_iop_sap_in_rw_gio___logic___width 2
78 #define reg_iop_sap_in_rw_gio_offset 16
82 #define regk_iop_sap_in_and 0x00000002
83 #define regk_iop_sap_in_ext_clk200 0x00000003
84 #define regk_iop_sap_in_gio0 0x00000000
85 #define regk_iop_sap_in_gio12 0x00000003
86 #define regk_iop_sap_in_gio16 0x00000004
87 #define regk_iop_sap_in_gio20 0x00000005
88 #define regk_iop_sap_in_gio24 0x00000006
89 #define regk_iop_sap_in_gio28 0x00000007
90 #define regk_iop_sap_in_gio4 0x00000001
91 #define regk_iop_sap_in_gio8 0x00000002
92 #define regk_iop_sap_in_inv 0x00000001
93 #define regk_iop_sap_in_neg 0x00000002
94 #define regk_iop_sap_in_no 0x00000000
95 #define regk_iop_sap_in_no_del_ext_clk200 0x00000002
96 #define regk_iop_sap_in_none 0x00000000
97 #define regk_iop_sap_in_one 0x00000001
98 #define regk_iop_sap_in_or 0x00000003
99 #define regk_iop_sap_in_pos 0x00000001
100 #define regk_iop_sap_in_pos_neg 0x00000003
101 #define regk_iop_sap_in_rw_bus_byte_default 0x00000000
102 #define regk_iop_sap_in_rw_bus_byte_size 0x00000004
103 #define regk_iop_sap_in_rw_gio_default 0x00000000
104 #define regk_iop_sap_in_rw_gio_size 0x00000020
105 #define regk_iop_sap_in_timer_grp0_tmr3 0x00000000
106 #define regk_iop_sap_in_timer_grp1_tmr3 0x00000001
107 #define regk_iop_sap_in_tmr_clk200 0x00000001
108 #define regk_iop_sap_in_two 0x00000002
109 #define regk_iop_sap_in_two_clk200 0x00000000
110 #endif /* __iop_sap_in_defs_asm_h */