arch/ia64/sn/kernel/sn2/sn2_smp.c

   1 /*
   2  * SN2 Platform specific SMP Support
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/threads.h>
  15 #include <linux/sched.h>
  16 #include <linux/smp.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/irq.h>
  19 #include <linux/mmzone.h>
  20 #include <linux/module.h>
  21 #include <linux/bitops.h>
  22 #include <linux/nodemask.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/seq_file.h>
  25
  26 #include <asm/processor.h>
  27 #include <asm/irq.h>
  28 #include <asm/sal.h>
  29 #include <asm/delay.h>
  30 #include <asm/io.h>
  31 #include <asm/smp.h>
  32 #include <asm/tlb.h>
  33 #include <asm/numa.h>
  34 #include <asm/hw_irq.h>
  35 #include <asm/current.h>
  36 #include <asm/sn/sn_cpuid.h>
  37 #include <asm/sn/sn_sal.h>
  38 #include <asm/sn/addrs.h>
  39 #include <asm/sn/shub_mmr.h>
  40 #include <asm/sn/nodepda.h>
  41 #include <asm/sn/rw_mmr.h>
  42 #include <asm/sn/sn_feature_sets.h>
  43
  44 DEFINE_PER_CPU(struct ptc_stats, ptcstats);
  45 DECLARE_PER_CPU(struct ptc_stats, ptcstats);
  46
  47 static  __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
  48
  49 /* 0 = old algorithm (no IPI flushes), 1 = ipi deadlock flush, 2 = ipi instead of SHUB ptc, >2 = always ipi */
  50 static int sn2_flush_opt = 0;
  51
  52 extern unsigned long
  53 sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
  54                                volatile unsigned long *, unsigned long,
  55                                volatile unsigned long *, unsigned long);
  56 void
  57 sn2_ptc_deadlock_recovery(nodemask_t, short, short, int,
  58                           volatile unsigned long *, unsigned long,
  59                           volatile unsigned long *, unsigned long);
  60
  61 /*
  62  * Note: some is the following is captured here to make degugging easier
  63  * (the macros make more sense if you see the debug patch - not posted)
  64  */
  65 #define sn2_ptctest     0
  66 #define local_node_uses_ptc_ga(sh1)     ((sh1) ? 1 : 0)
  67 #define max_active_pio(sh1)             ((sh1) ? 32 : 7)
  68 #define reset_max_active_on_deadlock()  1
  69 #define PTC_LOCK(sh1)                   ((sh1) ? &sn2_global_ptc_lock : &sn_nodepda->ptc_lock)
  70
  71 struct ptc_stats {
  72         unsigned long ptc_l;
  73         unsigned long change_rid;
  74         unsigned long shub_ptc_flushes;
  75         unsigned long nodes_flushed;
  76         unsigned long deadlocks;
  77         unsigned long deadlocks2;
  78         unsigned long lock_itc_clocks;
  79         unsigned long shub_itc_clocks;
  80         unsigned long shub_itc_clocks_max;
  81         unsigned long shub_ptc_flushes_not_my_mm;
  82         unsigned long shub_ipi_flushes;
  83         unsigned long shub_ipi_flushes_itc_clocks;
  84 };
  85
  86 #define sn2_ptctest     0
  87
  88 static inline unsigned long wait_piowc(void)
  89 {
  90         volatile unsigned long *piows;
  91         unsigned long zeroval, ws;
  92
  93         piows = pda->pio_write_status_addr;
  94         zeroval = pda->pio_write_status_val;
  95         do {
  96                 cpu_relax();
  97         } while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
  98         return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
  99 }
 100
 101 /**
 102  * sn_migrate - SN-specific task migration actions
 103  * @task: Task being migrated to new CPU
 104  *
 105  * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
 106  * Context switching user threads which have memory-mapped MMIO may cause
 107  * PIOs to issue from separate CPUs, thus the PIO writes must be drained
 108  * from the previous CPU's Shub before execution resumes on the new CPU.
 109  */
 110 void sn_migrate(struct task_struct *task)
 111 {
 112         pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
 113         volatile unsigned long *adr = last_pda->pio_write_status_addr;
 114         unsigned long val = last_pda->pio_write_status_val;
 115
 116         /* Drain PIO writes from old CPU's Shub */
 117         while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
 118                         != val))
 119                 cpu_relax();
 120 }
 121
 122 void sn_tlb_migrate_finish(struct mm_struct *mm)
 123 {
 124         /* flush_tlb_mm is inefficient if more than 1 users of mm */
 125         if (mm == current->mm && mm && atomic_read(&mm->mm_users) == 1)
 126                 flush_tlb_mm(mm);
 127 }
 128
 129 static void
 130 sn2_ipi_flush_all_tlb(struct mm_struct *mm)
 131 {
 132         unsigned long itc;
 133
 134         itc = ia64_get_itc();
 135         smp_flush_tlb_cpumask(*mm_cpumask(mm));
 136         itc = ia64_get_itc() - itc;
 137         __this_cpu_add(ptcstats.shub_ipi_flushes_itc_clocks, itc);
 138         __this_cpu_inc(ptcstats.shub_ipi_flushes);
 139 }
 140
 141 /**
 142  * sn2_global_tlb_purge - globally purge translation cache of virtual address range
 143  * @mm: mm_struct containing virtual address range
 144  * @start: start of virtual address range
 145  * @end: end of virtual address range
 146  * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
 147  *
 148  * Purges the translation caches of all processors of the given virtual address
 149  * range.
 150  *
 151  * Note:
 152  *      - cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
 153  *      - cpu_vm_mask is converted into a nodemask of the nodes containing the
 154  *        cpus in cpu_vm_mask.
 155  *      - if only one bit is set in cpu_vm_mask & it is the current cpu & the
 156  *        process is purging its own virtual address range, then only the
 157  *        local TLB needs to be flushed. This flushing can be done using
 158  *        ptc.l. This is the common case & avoids the global spinlock.
 159  *      - if multiple cpus have loaded the context, then flushing has to be
 160  *        done with ptc.g/MMRs under protection of the global ptc_lock.
 161  */
 162
 163 void
 164 sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
 165                      unsigned long end, unsigned long nbits)
 166 {
 167         int i, ibegin, shub1, cnode, mynasid, cpu, lcpu = 0, nasid;
 168         int mymm = (mm == current->active_mm && mm == current->mm);
 169         int use_cpu_ptcga;
 170         volatile unsigned long *ptc0, *ptc1;
 171         unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value, old_rr = 0;
 172         short nix;
 173         nodemask_t nodes_flushed;
 174         int active, max_active, deadlock, flush_opt = sn2_flush_opt;
 175
 176         if (flush_opt > 2) {
 177                 sn2_ipi_flush_all_tlb(mm);
 178                 return;
 179         }
 180
 181         nodes_clear(nodes_flushed);
 182         i = 0;
 183
 184         for_each_cpu(cpu, mm_cpumask(mm)) {
 185                 cnode = cpu_to_node(cpu);
 186                 node_set(cnode, nodes_flushed);
 187                 lcpu = cpu;
 188                 i++;
 189         }
 190
 191         if (i == 0)
 192                 return;
 193
 194         preempt_disable();
 195
 196         if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
 197                 do {
 198                         ia64_ptcl(start, nbits << 2);
 199                         start += (1UL << nbits);
 200                 } while (start < end);
 201                 ia64_srlz_i();
 202                 __this_cpu_inc(ptcstats.ptc_l);
 203                 preempt_enable();
 204                 return;
 205         }
 206
 207         if (atomic_read(&mm->mm_users) == 1 && mymm) {
 208                 flush_tlb_mm(mm);
 209                 __this_cpu_inc(ptcstats.change_rid);
 210                 preempt_enable();
 211                 return;
 212         }
 213
 214         if (flush_opt == 2) {
 215                 sn2_ipi_flush_all_tlb(mm);
 216                 preempt_enable();
 217                 return;
 218         }
 219
 220         itc = ia64_get_itc();
 221         nix = nodes_weight(nodes_flushed);
 222
 223         rr_value = (mm->context << 3) | REGION_NUMBER(start);
 224
 225         shub1 = is_shub1();
 226         if (shub1) {
 227                 data0 = (1UL << SH1_PTC_0_A_SHFT) |
 228                         (nbits << SH1_PTC_0_PS_SHFT) |
 229                         (rr_value << SH1_PTC_0_RID_SHFT) |
 230                         (1UL << SH1_PTC_0_START_SHFT);
 231                 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
 232                 ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
 233         } else {
 234                 data0 = (1UL << SH2_PTC_A_SHFT) |
 235                         (nbits << SH2_PTC_PS_SHFT) |
 236                         (1UL << SH2_PTC_START_SHFT);
 237                 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC +
 238                         (rr_value << SH2_PTC_RID_SHFT));
 239                 ptc1 = NULL;
 240         }
 241
 242
 243         mynasid = get_nasid();
 244         use_cpu_ptcga = local_node_uses_ptc_ga(shub1);
 245         max_active = max_active_pio(shub1);
 246
 247         itc = ia64_get_itc();
 248         spin_lock_irqsave(PTC_LOCK(shub1), flags);
 249         itc2 = ia64_get_itc();
 250
 251         __this_cpu_add(ptcstats.lock_itc_clocks, itc2 - itc);
 252         __this_cpu_inc(ptcstats.shub_ptc_flushes);
 253         __this_cpu_add(ptcstats.nodes_flushed, nix);
 254         if (!mymm)
 255                  __this_cpu_inc(ptcstats.shub_ptc_flushes_not_my_mm);
 256
 257         if (use_cpu_ptcga && !mymm) {
 258                 old_rr = ia64_get_rr(start);
 259                 ia64_set_rr(start, (old_rr & 0xff) | (rr_value << 8));
 260                 ia64_srlz_d();
 261         }
 262
 263         wait_piowc();
 264         do {
 265                 if (shub1)
 266                         data1 = start | (1UL << SH1_PTC_1_START_SHFT);
 267                 else
 268                         data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
 269                 deadlock = 0;
 270                 active = 0;
 271                 ibegin = 0;
 272                 i = 0;
 273                 for_each_node_mask(cnode, nodes_flushed) {
 274                         nasid = cnodeid_to_nasid(cnode);
 275                         if (use_cpu_ptcga && unlikely(nasid == mynasid)) {
 276                                 ia64_ptcga(start, nbits << 2);
 277                                 ia64_srlz_i();
 278                         } else {
 279                                 ptc0 = CHANGE_NASID(nasid, ptc0);
 280                                 if (ptc1)
 281                                         ptc1 = CHANGE_NASID(nasid, ptc1);
 282                                 pio_atomic_phys_write_mmrs(ptc0, data0, ptc1, data1);
 283                                 active++;
 284                         }
 285                         if (active >= max_active || i == (nix - 1)) {
 286                                 if ((deadlock = wait_piowc())) {
 287                                         if (flush_opt == 1)
 288                                                 goto done;
 289                                         sn2_ptc_deadlock_recovery(nodes_flushed, ibegin, i, mynasid, ptc0, data0, ptc1, data1);
 290                                         if (reset_max_active_on_deadlock())
 291                                                 max_active = 1;
 292                                 }
 293                                 active = 0;
 294                                 ibegin = i + 1;
 295                         }
 296                         i++;
 297                 }
 298                 start += (1UL << nbits);
 299         } while (start < end);
 300
 301 done:
 302         itc2 = ia64_get_itc() - itc2;
 303         __this_cpu_add(ptcstats.shub_itc_clocks, itc2);
 304         if (itc2 > __this_cpu_read(ptcstats.shub_itc_clocks_max))
 305                 __this_cpu_write(ptcstats.shub_itc_clocks_max, itc2);
 306
 307         if (old_rr) {
 308                 ia64_set_rr(start, old_rr);
 309                 ia64_srlz_d();
 310         }
 311
 312         spin_unlock_irqrestore(PTC_LOCK(shub1), flags);
 313
 314         if (flush_opt == 1 && deadlock) {
 315                 __this_cpu_inc(ptcstats.deadlocks);
 316                 sn2_ipi_flush_all_tlb(mm);
 317         }
 318
 319         preempt_enable();
 320 }
 321
 322 /*
 323  * sn2_ptc_deadlock_recovery
 324  *
 325  * Recover from PTC deadlocks conditions. Recovery requires stepping thru each
 326  * TLB flush transaction.  The recovery sequence is somewhat tricky & is
 327  * coded in assembly language.
 328  */
 329
 330 void
 331 sn2_ptc_deadlock_recovery(nodemask_t nodes, short ib, short ie, int mynasid,
 332                           volatile unsigned long *ptc0, unsigned long data0,
 333                           volatile unsigned long *ptc1, unsigned long data1)
 334 {
 335         short nasid, i;
 336         int cnode;
 337         unsigned long *piows, zeroval, n;
 338
 339         __this_cpu_inc(ptcstats.deadlocks);
 340
 341         piows = (unsigned long *) pda->pio_write_status_addr;
 342         zeroval = pda->pio_write_status_val;
 343
 344         i = 0;
 345         for_each_node_mask(cnode, nodes) {
 346                 if (i < ib)
 347                         goto next;
 348
 349                 if (i > ie)
 350                         break;
 351
 352                 nasid = cnodeid_to_nasid(cnode);
 353                 if (local_node_uses_ptc_ga(is_shub1()) && nasid == mynasid)
 354                         goto next;
 355
 356                 ptc0 = CHANGE_NASID(nasid, ptc0);
 357                 if (ptc1)
 358                         ptc1 = CHANGE_NASID(nasid, ptc1);
 359
 360                 n = sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
 361                 __this_cpu_add(ptcstats.deadlocks2, n);
 362 next:
 363                 i++;
 364         }
 365
 366 }
 367
 368 /**
 369  * sn_send_IPI_phys - send an IPI to a Nasid and slice
 370  * @nasid: nasid to receive the interrupt (may be outside partition)
 371  * @physid: physical cpuid to receive the interrupt.
 372  * @vector: command to send
 373  * @delivery_mode: delivery mechanism
 374  *
 375  * Sends an IPI (interprocessor interrupt) to the processor specified by
 376  * @physid
 377  *
 378  * @delivery_mode can be one of the following
 379  *
 380  * %IA64_IPI_DM_INT - pend an interrupt
 381  * %IA64_IPI_DM_PMI - pend a PMI
 382  * %IA64_IPI_DM_NMI - pend an NMI
 383  * %IA64_IPI_DM_INIT - pend an INIT interrupt
 384  */
 385 void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
 386 {
 387         long val;
 388         unsigned long flags = 0;
 389         volatile long *p;
 390
 391         p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
 392         val = (1UL << SH_IPI_INT_SEND_SHFT) |
 393             (physid << SH_IPI_INT_PID_SHFT) |
 394             ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
 395             ((long)vector << SH_IPI_INT_IDX_SHFT) |
 396             (0x000feeUL << SH_IPI_INT_BASE_SHFT);
 397
 398         mb();
 399         if (enable_shub_wars_1_1()) {
 400                 spin_lock_irqsave(&sn2_global_ptc_lock, flags);
 401         }
 402         pio_phys_write_mmr(p, val);
 403         if (enable_shub_wars_1_1()) {
 404                 wait_piowc();
 405                 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
 406         }
 407
 408 }
 409
 410 EXPORT_SYMBOL(sn_send_IPI_phys);
 411
 412 /**
 413  * sn2_send_IPI - send an IPI to a processor
 414  * @cpuid: target of the IPI
 415  * @vector: command to send
 416  * @delivery_mode: delivery mechanism
 417  * @redirect: redirect the IPI?
 418  *
 419  * Sends an IPI (InterProcessor Interrupt) to the processor specified by
 420  * @cpuid.  @vector specifies the command to send, while @delivery_mode can
 421  * be one of the following
 422  *
 423  * %IA64_IPI_DM_INT - pend an interrupt
 424  * %IA64_IPI_DM_PMI - pend a PMI
 425  * %IA64_IPI_DM_NMI - pend an NMI
 426  * %IA64_IPI_DM_INIT - pend an INIT interrupt
 427  */
 428 void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
 429 {
 430         long physid;
 431         int nasid;
 432
 433         physid = cpu_physical_id(cpuid);
 434         nasid = cpuid_to_nasid(cpuid);
 435
 436         /* the following is used only when starting cpus at boot time */
 437         if (unlikely(nasid == -1))
 438                 ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
 439
 440         sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
 441 }
 442
 443 #ifdef CONFIG_HOTPLUG_CPU
 444 /**
 445  * sn_cpu_disable_allowed - Determine if a CPU can be disabled.
 446  * @cpu - CPU that is requested to be disabled.
 447  *
 448  * CPU disable is only allowed on SHub2 systems running with a PROM
 449  * that supports CPU disable. It is not permitted to disable the boot processor.
 450  */
 451 bool sn_cpu_disable_allowed(int cpu)
 452 {
 453         if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT)) {
 454                 if (cpu != 0)
 455                         return true;
 456                 else
 457                         printk(KERN_WARNING
 458                               "Disabling the boot processor is not allowed.\n");
 459
 460         } else
 461                 printk(KERN_WARNING
 462                        "CPU disable is not supported on this system.\n");
 463
 464         return false;
 465 }
 466 #endif /* CONFIG_HOTPLUG_CPU */
 467
 468 #ifdef CONFIG_PROC_FS
 469
 470 #define PTC_BASENAME    "sgi_sn/ptc_statistics"
 471
 472 static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
 473 {
 474         if (*offset < nr_cpu_ids)
 475                 return offset;
 476         return NULL;
 477 }
 478
 479 static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
 480 {
 481         (*offset)++;
 482         if (*offset < nr_cpu_ids)
 483                 return offset;
 484         return NULL;
 485 }
 486
 487 static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
 488 {
 489 }
 490
 491 static int sn2_ptc_seq_show(struct seq_file *file, void *data)
 492 {
 493         struct ptc_stats *stat;
 494         int cpu;
 495
 496         cpu = *(loff_t *) data;
 497
 498         if (!cpu) {
 499                 seq_printf(file,
 500                            "# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2 ipi_fluches ipi_nsec\n");
 501                 seq_printf(file, "# ptctest %d, flushopt %d\n", sn2_ptctest, sn2_flush_opt);
 502         }
 503
 504         if (cpu < nr_cpu_ids && cpu_online(cpu)) {
 505                 stat = &per_cpu(ptcstats, cpu);
 506                 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
 507                                 stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
 508                                 stat->deadlocks,
 509                                 1000 * stat->lock_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
 510                                 1000 * stat->shub_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
 511                                 1000 * stat->shub_itc_clocks_max / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
 512                                 stat->shub_ptc_flushes_not_my_mm,
 513                                 stat->deadlocks2,
 514                                 stat->shub_ipi_flushes,
 515                                 1000 * stat->shub_ipi_flushes_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec);
 516         }
 517         return 0;
 518 }
 519
 520 static ssize_t sn2_ptc_proc_write(struct file *file, const char __user *user, size_t count, loff_t *data)
 521 {
 522         int cpu;
 523         char optstr[64];
 524
 525         if (count == 0 || count > sizeof(optstr))
 526                 return -EINVAL;
 527         if (copy_from_user(optstr, user, count))
 528                 return -EFAULT;
 529         optstr[count - 1] = '\0';
 530         sn2_flush_opt = simple_strtoul(optstr, NULL, 0);
 531
 532         for_each_online_cpu(cpu)
 533                 memset(&per_cpu(ptcstats, cpu), 0, sizeof(struct ptc_stats));
 534
 535         return count;
 536 }
 537
 538 static const struct seq_operations sn2_ptc_seq_ops = {
 539         .start = sn2_ptc_seq_start,
 540         .next = sn2_ptc_seq_next,
 541         .stop = sn2_ptc_seq_stop,
 542         .show = sn2_ptc_seq_show
 543 };
 544
 545 static int sn2_ptc_proc_open(struct inode *inode, struct file *file)
 546 {
 547         return seq_open(file, &sn2_ptc_seq_ops);
 548 }
 549
 550 static const struct file_operations proc_sn2_ptc_operations = {
 551         .open = sn2_ptc_proc_open,
 552         .read = seq_read,
 553         .write = sn2_ptc_proc_write,
 554         .llseek = seq_lseek,
 555         .release = seq_release,
 556 };
 557
 558 static struct proc_dir_entry *proc_sn2_ptc;
 559
 560 static int __init sn2_ptc_init(void)
 561 {
 562         if (!ia64_platform_is("sn2"))
 563                 return 0;
 564
 565         proc_sn2_ptc = proc_create(PTC_BASENAME, 0444,
 566                                    NULL, &proc_sn2_ptc_operations);
 567         if (!proc_sn2_ptc) {
 568                 printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
 569                 return -EINVAL;
 570         }
 571         spin_lock_init(&sn2_global_ptc_lock);
 572         return 0;
 573 }
 574
 575 static void __exit sn2_ptc_exit(void)
 576 {
 577         remove_proc_entry(PTC_BASENAME, NULL);
 578 }
 579
 580 module_init(sn2_ptc_init);
 581 module_exit(sn2_ptc_exit);
 582 #endif /* CONFIG_PROC_FS */
 583