1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ARCH_M68K_ATOMIC__
3 #define __ARCH_M68K_ATOMIC__
5 #include <linux/types.h>
6 #include <linux/irqflags.h>
7 #include <asm/cmpxchg.h>
8 #include <asm/barrier.h>
11 * Atomic operations that C can't guarantee us. Useful for
12 * resource counting etc..
16 * We do not have SMP m68k systems, so we don't have to deal with that.
19 #define ATOMIC_INIT(i) { (i) }
21 #define atomic_read(v) READ_ONCE((v)->counter)
22 #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
25 * The ColdFire parts cannot do some immediate to memory operations,
26 * so for them we do not specify the "i" asm constraint.
28 #ifdef CONFIG_COLDFIRE
34 #define ATOMIC_OP(op, c_op, asm_op) \
35 static inline void atomic_##op(int i, atomic_t *v) \
37 __asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
40 #ifdef CONFIG_RMW_INSNS
42 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
43 static inline int atomic_##op##_return(int i, atomic_t *v) \
47 __asm__ __volatile__( \
49 " " #asm_op "l %3,%1\n" \
52 : "+m" (*v), "=&d" (t), "=&d" (tmp) \
53 : "g" (i), "2" (atomic_read(v))); \
57 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
58 static inline int atomic_fetch_##op(int i, atomic_t *v) \
62 __asm__ __volatile__( \
64 " " #asm_op "l %3,%1\n" \
67 : "+m" (*v), "=&d" (t), "=&d" (tmp) \
68 : "g" (i), "2" (atomic_read(v))); \
74 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
75 static inline int atomic_##op##_return(int i, atomic_t * v) \
77 unsigned long flags; \
80 local_irq_save(flags); \
81 t = (v->counter c_op i); \
82 local_irq_restore(flags); \
87 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
88 static inline int atomic_fetch_##op(int i, atomic_t * v) \
90 unsigned long flags; \
93 local_irq_save(flags); \
96 local_irq_restore(flags); \
101 #endif /* CONFIG_RMW_INSNS */
103 #define ATOMIC_OPS(op, c_op, asm_op) \
104 ATOMIC_OP(op, c_op, asm_op) \
105 ATOMIC_OP_RETURN(op, c_op, asm_op) \
106 ATOMIC_FETCH_OP(op, c_op, asm_op)
108 ATOMIC_OPS(add, +=, add)
109 ATOMIC_OPS(sub, -=, sub)
112 #define ATOMIC_OPS(op, c_op, asm_op) \
113 ATOMIC_OP(op, c_op, asm_op) \
114 ATOMIC_FETCH_OP(op, c_op, asm_op)
116 ATOMIC_OPS(and, &=, and)
117 ATOMIC_OPS(or, |=, or)
118 ATOMIC_OPS(xor, ^=, eor)
121 #undef ATOMIC_FETCH_OP
122 #undef ATOMIC_OP_RETURN
125 static inline void atomic_inc(atomic_t *v)
127 __asm__ __volatile__("addql #1,%0" : "+m" (*v));
129 #define atomic_inc atomic_inc
131 static inline void atomic_dec(atomic_t *v)
133 __asm__ __volatile__("subql #1,%0" : "+m" (*v));
135 #define atomic_dec atomic_dec
137 static inline int atomic_dec_and_test(atomic_t *v)
140 __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
143 #define atomic_dec_and_test atomic_dec_and_test
145 static inline int atomic_dec_and_test_lt(atomic_t *v)
148 __asm__ __volatile__(
149 "subql #1,%1; slt %0"
150 : "=d" (c), "=m" (*v)
155 static inline int atomic_inc_and_test(atomic_t *v)
158 __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
161 #define atomic_inc_and_test atomic_inc_and_test
163 #ifdef CONFIG_RMW_INSNS
165 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
166 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
168 #else /* !CONFIG_RMW_INSNS */
170 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
175 local_irq_save(flags);
176 prev = atomic_read(v);
179 local_irq_restore(flags);
183 static inline int atomic_xchg(atomic_t *v, int new)
188 local_irq_save(flags);
189 prev = atomic_read(v);
191 local_irq_restore(flags);
195 #endif /* !CONFIG_RMW_INSNS */
197 static inline int atomic_sub_and_test(int i, atomic_t *v)
200 __asm__ __volatile__("subl %2,%1; seq %0"
201 : "=d" (c), "+m" (*v)
205 #define atomic_sub_and_test atomic_sub_and_test
207 static inline int atomic_add_negative(int i, atomic_t *v)
210 __asm__ __volatile__("addl %2,%1; smi %0"
211 : "=d" (c), "+m" (*v)
215 #define atomic_add_negative atomic_add_negative
217 #endif /* __ARCH_M68K_ATOMIC __ */