arch/mips/boot/dts/brcm/bcm7360.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 / {
   3         #address-cells = <1>;
   4         #size-cells = <1>;
   5         compatible = "brcm,bcm7360";
   6
   7         cpus {
   8                 #address-cells = <1>;
   9                 #size-cells = <0>;
  10
  11                 mips-hpt-frequency = <375000000>;
  12
  13                 cpu@0 {
  14                         compatible = "brcm,bmips3300";
  15                         device_type = "cpu";
  16                         reg = <0>;
  17                 };
  18         };
  19
  20         aliases {
  21                 uart0 = &uart0;
  22         };
  23
  24         cpu_intc: interrupt-controller {
  25                 #address-cells = <0>;
  26                 compatible = "mti,cpu-interrupt-controller";
  27
  28                 interrupt-controller;
  29                 #interrupt-cells = <1>;
  30         };
  31
  32         clocks {
  33                 uart_clk: uart_clk {
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                         clock-frequency = <81000000>;
  37                 };
  38
  39                 upg_clk: upg_clk {
  40                         compatible = "fixed-clock";
  41                         #clock-cells = <0>;
  42                         clock-frequency = <27000000>;
  43                 };
  44         };
  45
  46         rdb {
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49
  50                 compatible = "simple-bus";
  51                 ranges = <0 0x10000000 0x01000000>;
  52
  53                 periph_intc: interrupt-controller@411400 {
  54                         compatible = "brcm,bcm7038-l1-intc";
  55                         reg = <0x411400 0x30>;
  56
  57                         interrupt-controller;
  58                         #interrupt-cells = <1>;
  59
  60                         interrupt-parent = <&cpu_intc>;
  61                         interrupts = <2>;
  62                 };
  63
  64                 sun_l2_intc: interrupt-controller@403000 {
  65                         compatible = "brcm,l2-intc";
  66                         reg = <0x403000 0x30>;
  67                         interrupt-controller;
  68                         #interrupt-cells = <1>;
  69                         interrupt-parent = <&periph_intc>;
  70                         interrupts = <48>;
  71                 };
  72
  73                 gisb-arb@400000 {
  74                         compatible = "brcm,bcm7400-gisb-arb";
  75                         reg = <0x400000 0xdc>;
  76                         native-endian;
  77                         interrupt-parent = <&sun_l2_intc>;
  78                         interrupts = <0>, <2>;
  79                         brcm,gisb-arb-master-mask = <0x2f3>;
  80                         brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
  81                                                      "rdc_0", "raaga_0",
  82                                                      "avd_0", "jtag_0";
  83                 };
  84
  85                 upg_irq0_intc: interrupt-controller@406600 {
  86                         compatible = "brcm,bcm7120-l2-intc";
  87                         reg = <0x406600 0x8>;
  88
  89                         brcm,int-map-mask = <0x44>, <0x7000000>;
  90                         brcm,int-fwd-mask = <0x70000>;
  91
  92                         interrupt-controller;
  93                         #interrupt-cells = <1>;
  94
  95                         interrupt-parent = <&periph_intc>;
  96                         interrupts = <56>, <54>;
  97                         interrupt-names = "upg_main", "upg_bsc";
  98                 };
  99
 100                 upg_aon_irq0_intc: interrupt-controller@408b80 {
 101                         compatible = "brcm,bcm7120-l2-intc";
 102                         reg = <0x408b80 0x8>;
 103
 104                         brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
 105                         brcm,int-fwd-mask = <0>;
 106                         brcm,irq-can-wake;
 107
 108                         interrupt-controller;
 109                         #interrupt-cells = <1>;
 110
 111                         interrupt-parent = <&periph_intc>;
 112                         interrupts = <57>, <55>, <59>;
 113                         interrupt-names = "upg_main_aon", "upg_bsc_aon",
 114                                           "upg_spi";
 115                 };
 116
 117                 sun_top_ctrl: syscon@404000 {
 118                         compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
 119                         reg = <0x404000 0x51c>;
 120                         native-endian;
 121                 };
 122
 123                 reboot {
 124                         compatible = "brcm,brcmstb-reboot";
 125                         syscon = <&sun_top_ctrl 0x304 0x308>;
 126                 };
 127
 128                 uart0: serial@406800 {
 129                         compatible = "ns16550a";
 130                         reg = <0x406800 0x20>;
 131                         reg-io-width = <0x4>;
 132                         reg-shift = <0x2>;
 133                         native-endian;
 134                         interrupt-parent = <&periph_intc>;
 135                         interrupts = <61>;
 136                         clocks = <&uart_clk>;
 137                         status = "disabled";
 138                 };
 139
 140                 uart1: serial@406840 {
 141                         compatible = "ns16550a";
 142                         reg = <0x406840 0x20>;
 143                         reg-io-width = <0x4>;
 144                         reg-shift = <0x2>;
 145                         native-endian;
 146                         interrupt-parent = <&periph_intc>;
 147                         interrupts = <62>;
 148                         clocks = <&uart_clk>;
 149                         status = "disabled";
 150                 };
 151
 152                 uart2: serial@406880 {
 153                         compatible = "ns16550a";
 154                         reg = <0x406880 0x20>;
 155                         reg-io-width = <0x4>;
 156                         reg-shift = <0x2>;
 157                         native-endian;
 158                         interrupt-parent = <&periph_intc>;
 159                         interrupts = <63>;
 160                         clocks = <&uart_clk>;
 161                         status = "disabled";
 162                 };
 163
 164                 bsca: i2c@406200 {
 165                       clock-frequency = <390000>;
 166                       compatible = "brcm,brcmstb-i2c";
 167                       interrupt-parent = <&upg_irq0_intc>;
 168                       reg = <0x406200 0x58>;
 169                       interrupts = <24>;
 170                       interrupt-names = "upg_bsca";
 171                       status = "disabled";
 172                 };
 173
 174                 bscb: i2c@406280 {
 175                       clock-frequency = <390000>;
 176                       compatible = "brcm,brcmstb-i2c";
 177                       interrupt-parent = <&upg_irq0_intc>;
 178                       reg = <0x406280 0x58>;
 179                       interrupts = <25>;
 180                       interrupt-names = "upg_bscb";
 181                       status = "disabled";
 182                 };
 183
 184                 bscc: i2c@406300 {
 185                       clock-frequency = <390000>;
 186                       compatible = "brcm,brcmstb-i2c";
 187                       interrupt-parent = <&upg_irq0_intc>;
 188                       reg = <0x406300 0x58>;
 189                       interrupts = <26>;
 190                       interrupt-names = "upg_bscc";
 191                       status = "disabled";
 192                 };
 193
 194                 bscd: i2c@408980 {
 195                       clock-frequency = <390000>;
 196                       compatible = "brcm,brcmstb-i2c";
 197                       interrupt-parent = <&upg_aon_irq0_intc>;
 198                       reg = <0x408980 0x58>;
 199                       interrupts = <27>;
 200                       interrupt-names = "upg_bscd";
 201                       status = "disabled";
 202                 };
 203
 204                 pwma: pwm@406400 {
 205                         compatible = "brcm,bcm7038-pwm";
 206                         reg = <0x406400 0x28>;
 207                         #pwm-cells = <2>;
 208                         clocks = <&upg_clk>;
 209                         status = "disabled";
 210                 };
 211
 212                 watchdog: watchdog@4066a8 {
 213                         clocks = <&upg_clk>;
 214                         compatible = "brcm,bcm7038-wdt";
 215                         reg = <0x4066a8 0x14>;
 216                         status = "disabled";
 217                 };
 218
 219                 aon_pm_l2_intc: interrupt-controller@408440 {
 220                         compatible = "brcm,l2-intc";
 221                         reg = <0x408440 0x30>;
 222                         interrupt-controller;
 223                         #interrupt-cells = <1>;
 224                         interrupt-parent = <&periph_intc>;
 225                         interrupts = <50>;
 226                         brcm,irq-can-wake;
 227                 };
 228
 229                 aon_ctrl: syscon@408000 {
 230                         compatible = "brcm,brcmstb-aon-ctrl";
 231                         reg = <0x408000 0x100>, <0x408200 0x200>;
 232                         reg-names = "aon-ctrl", "aon-sram";
 233                 };
 234
 235                 timers: timer@406680 {
 236                         compatible = "brcm,brcmstb-timers";
 237                         reg = <0x406680 0x40>;
 238                 };
 239
 240                 upg_gio: gpio@406500 {
 241                         compatible = "brcm,brcmstb-gpio";
 242                         reg = <0x406500 0xa0>;
 243                         #gpio-cells = <2>;
 244                         #interrupt-cells = <2>;
 245                         gpio-controller;
 246                         interrupt-controller;
 247                         interrupt-parent = <&upg_irq0_intc>;
 248                         interrupts = <6>;
 249                         brcm,gpio-bank-widths = <32 32 32 29 4>;
 250                 };
 251
 252                 upg_gio_aon: gpio@408c00 {
 253                         compatible = "brcm,brcmstb-gpio";
 254                         reg = <0x408c00 0x60>;
 255                         #gpio-cells = <2>;
 256                         #interrupt-cells = <2>;
 257                         gpio-controller;
 258                         interrupt-controller;
 259                         interrupt-parent = <&upg_aon_irq0_intc>;
 260                         interrupts = <6>;
 261                         interrupts-extended = <&upg_aon_irq0_intc 6>,
 262                                               <&aon_pm_l2_intc 5>;
 263                         wakeup-source;
 264                         brcm,gpio-bank-widths = <21 32 2>;
 265                 };
 266
 267                 enet0: ethernet@430000 {
 268                         phy-mode = "internal";
 269                         phy-handle = <&phy1>;
 270                         mac-address = [ 00 10 18 36 23 1a ];
 271                         compatible = "brcm,genet-v2";
 272                         #address-cells = <0x1>;
 273                         #size-cells = <0x1>;
 274                         reg = <0x430000 0x4c8c>;
 275                         interrupts = <24>, <25>;
 276                         interrupt-parent = <&periph_intc>;
 277                         status = "disabled";
 278
 279                         mdio@e14 {
 280                                 compatible = "brcm,genet-mdio-v2";
 281                                 #address-cells = <0x1>;
 282                                 #size-cells = <0x0>;
 283                                 reg = <0xe14 0x8>;
 284
 285                                 phy1: ethernet-phy@1 {
 286                                         max-speed = <100>;
 287                                         reg = <0x1>;
 288                                         compatible = "brcm,40nm-ephy",
 289                                                 "ethernet-phy-ieee802.3-c22";
 290                                 };
 291                         };
 292                 };
 293
 294                 ehci0: usb@480300 {
 295                         compatible = "brcm,bcm7360-ehci", "generic-ehci";
 296                         reg = <0x480300 0x100>;
 297                         native-endian;
 298                         interrupt-parent = <&periph_intc>;
 299                         interrupts = <65>;
 300                         status = "disabled";
 301                 };
 302
 303                 ohci0: usb@480400 {
 304                         compatible = "brcm,bcm7360-ohci", "generic-ohci";
 305                         reg = <0x480400 0x100>;
 306                         native-endian;
 307                         no-big-frame-no;
 308                         interrupt-parent = <&periph_intc>;
 309                         interrupts = <66>;
 310                         status = "disabled";
 311                 };
 312
 313                 hif_l2_intc: interrupt-controller@411000 {
 314                         compatible = "brcm,l2-intc";
 315                         reg = <0x411000 0x30>;
 316                         interrupt-controller;
 317                         #interrupt-cells = <1>;
 318                         interrupt-parent = <&periph_intc>;
 319                         interrupts = <30>;
 320                 };
 321
 322                 nand: nand@412800 {
 323                         compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                         reg-names = "nand";
 327                         reg = <0x412800 0x400>;
 328                         interrupt-parent = <&hif_l2_intc>;
 329                         interrupts = <24>;
 330                         status = "disabled";
 331                 };
 332
 333                 sata: sata@181000 {
 334                         compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
 335                         reg-names = "ahci", "top-ctrl";
 336                         reg = <0x181000 0xa9c>, <0x180020 0x1c>;
 337                         interrupt-parent = <&periph_intc>;
 338                         interrupts = <86>;
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         status = "disabled";
 342
 343                         sata0: sata-port@0 {
 344                                 reg = <0>;
 345                                 phys = <&sata_phy0>;
 346                         };
 347
 348                         sata1: sata-port@1 {
 349                                 reg = <1>;
 350                                 phys = <&sata_phy1>;
 351                         };
 352                 };
 353
 354                 sata_phy: sata-phy@180100 {
 355                         compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
 356                         reg = <0x180100 0x0eff>;
 357                         reg-names = "phy";
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         status = "disabled";
 361
 362                         sata_phy0: sata-phy@0 {
 363                                 reg = <0>;
 364                                 #phy-cells = <0>;
 365                         };
 366
 367                         sata_phy1: sata-phy@1 {
 368                                 reg = <1>;
 369                                 #phy-cells = <0>;
 370                         };
 371                 };
 372
 373                 sdhci0: sdhci@410000 {
 374                         compatible = "brcm,bcm7425-sdhci";
 375                         reg = <0x410000 0x100>;
 376                         interrupt-parent = <&periph_intc>;
 377                         interrupts = <82>;
 378                         status = "disabled";
 379                 };
 380
 381                 spi_l2_intc: interrupt-controller@411d00 {
 382                         compatible = "brcm,l2-intc";
 383                         reg = <0x411d00 0x30>;
 384                         interrupt-controller;
 385                         #interrupt-cells = <1>;
 386                         interrupt-parent = <&periph_intc>;
 387                         interrupts = <31>;
 388                 };
 389
 390                 qspi: spi@413000 {
 391                         #address-cells = <0x1>;
 392                         #size-cells = <0x0>;
 393                         compatible = "brcm,spi-bcm-qspi",
 394                                      "brcm,spi-brcmstb-qspi";
 395                         clocks = <&upg_clk>;
 396                         reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
 397                         reg-names = "cs_reg", "hif_mspi", "bspi";
 398                         interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
 399                         interrupt-parent = <&spi_l2_intc>;
 400                         interrupt-names = "spi_lr_fullness_reached",
 401                                           "spi_lr_session_aborted",
 402                                           "spi_lr_impatient",
 403                                           "spi_lr_session_done",
 404                                           "spi_lr_overread",
 405                                           "mspi_done",
 406                                           "mspi_halted";
 407                         status = "disabled";
 408                 };
 409
 410                 mspi: spi@408a00 {
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         compatible = "brcm,spi-bcm-qspi",
 414                                      "brcm,spi-brcmstb-mspi";
 415                         clocks = <&upg_clk>;
 416                         reg = <0x408a00 0x180>;
 417                         reg-names = "mspi";
 418                         interrupts = <0x14>;
 419                         interrupt-parent = <&upg_aon_irq0_intc>;
 420                         interrupt-names = "mspi_done";
 421                         status = "disabled";
 422                 };
 423
 424                 waketimer: waketimer@408e80 {
 425                         compatible = "brcm,brcmstb-waketimer";
 426                         reg = <0x408e80 0x14>;
 427                         interrupts = <0x3>;
 428                         interrupt-parent = <&aon_pm_l2_intc>;
 429                         interrupt-names = "timer";
 430                         clocks = <&upg_clk>;
 431                         status = "disabled";
 432                 };
 433         };
 434
 435         memory_controllers {
 436                 compatible = "simple-bus";
 437                 ranges = <0x0 0x103b0000 0xa000>;
 438                 #address-cells = <1>;
 439                 #size-cells = <1>;
 440
 441                 memory-controller@0 {
 442                         compatible = "brcm,brcmstb-memc", "simple-bus";
 443                         ranges = <0x0 0x0 0xa000>;
 444                         #address-cells = <1>;
 445                         #size-cells = <1>;
 446
 447                         memc-arb@1000 {
 448                                 compatible = "brcm,brcmstb-memc-arb";
 449                                 reg = <0x1000 0x248>;
 450                         };
 451
 452                         memc-ddr@2000 {
 453                                 compatible = "brcm,brcmstb-memc-ddr";
 454                                 reg = <0x2000 0x300>;
 455                         };
 456
 457                         ddr-phy@6000 {
 458                                 compatible = "brcm,brcmstb-ddr-phy";
 459                                 reg = <0x6000 0xc8>;
 460                         };
 461
 462                         shimphy@8000 {
 463                                 compatible = "brcm,brcmstb-ddr-shimphy";
 464                                 reg = <0x8000 0x13c>;
 465                         };
 466                 };
 467         };
 468 };