arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3 /*
   4  * OCTEON 68XX device tree skeleton.
   5  *
   6  * This device tree is pruned and patched by early boot code before
   7  * use.  Because of this, it contains a super-set of the available
   8  * devices and properties.
   9  */
  10 / {
  11         compatible = "cavium,octeon-6880";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14         interrupt-parent = <&ciu2>;
  15
  16         soc@0 {
  17                 compatible = "simple-bus";
  18                 #address-cells = <2>;
  19                 #size-cells = <2>;
  20                 ranges; /* Direct mapping */
  21
  22                 ciu2: interrupt-controller@1070100000000 {
  23                         compatible = "cavium,octeon-6880-ciu2";
  24                         interrupt-controller;
  25                         /* Interrupts are specified by two parts:
  26                          * 1) Controller register (0 or 7)
  27                          * 2) Bit within the register (0..63)
  28                          */
  29                         #address-cells = <0>;
  30                         #interrupt-cells = <2>;
  31                         reg = <0x10701 0x00000000 0x0 0x4000000>;
  32                 };
  33
  34                 gpio: gpio-controller@1070000000800 {
  35                         #gpio-cells = <2>;
  36                         compatible = "cavium,octeon-3860-gpio";
  37                         reg = <0x10700 0x00000800 0x0 0x100>;
  38                         gpio-controller;
  39                         /* Interrupts are specified by two parts:
  40                          * 1) GPIO pin number (0..15)
  41                          * 2) Triggering (1 - edge rising
  42                          *                2 - edge falling
  43                          *                4 - level active high
  44                          *                8 - level active low)
  45                          */
  46                         interrupt-controller;
  47                         #interrupt-cells = <2>;
  48                         /* The GPIO pins connect to 16 consecutive CUI bits */
  49                         interrupts = <7 0>,  <7 1>,  <7 2>,  <7 3>,
  50                                      <7 4>,  <7 5>,  <7 6>,  <7 7>,
  51                                      <7 8>,  <7 9>,  <7 10>, <7 11>,
  52                                      <7 12>, <7 13>, <7 14>, <7 15>;
  53                 };
  54
  55                 smi0: mdio@1180000003800 {
  56                         compatible = "cavium,octeon-3860-mdio";
  57                         #address-cells = <1>;
  58                         #size-cells = <0>;
  59                         reg = <0x11800 0x00003800 0x0 0x40>;
  60
  61                         phy0: ethernet-phy@6 {
  62                                 compatible = "marvell,88e1118";
  63                                 marvell,reg-init =
  64                                         /* Fix rx and tx clock transition timing */
  65                                         <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
  66                                         /* Adjust LED drive. */
  67                                         <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
  68                                         /* irq, blink-activity, blink-link */
  69                                         <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
  70                                 reg = <6>;
  71                         };
  72
  73                         phy1: ethernet-phy@1 {
  74                                 cavium,qlm-trim = "4,sgmii";
  75                                 reg = <1>;
  76                                 compatible = "marvell,88e1149r";
  77                                 marvell,reg-init = <3 0x10 0 0x5777>,
  78                                         <3 0x11 0 0x00aa>,
  79                                         <3 0x12 0 0x4105>,
  80                                         <3 0x13 0 0x0a60>;
  81                         };
  82                         phy2: ethernet-phy@2 {
  83                                 cavium,qlm-trim = "4,sgmii";
  84                                 reg = <2>;
  85                                 compatible = "marvell,88e1149r";
  86                                 marvell,reg-init = <3 0x10 0 0x5777>,
  87                                         <3 0x11 0 0x00aa>,
  88                                         <3 0x12 0 0x4105>,
  89                                         <3 0x13 0 0x0a60>;
  90                         };
  91                         phy3: ethernet-phy@3 {
  92                                 cavium,qlm-trim = "4,sgmii";
  93                                 reg = <3>;
  94                                 compatible = "marvell,88e1149r";
  95                                 marvell,reg-init = <3 0x10 0 0x5777>,
  96                                         <3 0x11 0 0x00aa>,
  97                                         <3 0x12 0 0x4105>,
  98                                         <3 0x13 0 0x0a60>;
  99                         };
 100                         phy4: ethernet-phy@4 {
 101                                 cavium,qlm-trim = "4,sgmii";
 102                                 reg = <4>;
 103                                 compatible = "marvell,88e1149r";
 104                                 marvell,reg-init = <3 0x10 0 0x5777>,
 105                                         <3 0x11 0 0x00aa>,
 106                                         <3 0x12 0 0x4105>,
 107                                         <3 0x13 0 0x0a60>;
 108                         };
 109                 };
 110
 111                 smi1: mdio@1180000003880 {
 112                         compatible = "cavium,octeon-3860-mdio";
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                         reg = <0x11800 0x00003880 0x0 0x40>;
 116
 117                         phy41: ethernet-phy@1 {
 118                                 cavium,qlm-trim = "0,sgmii";
 119                                 reg = <1>;
 120                                 compatible = "marvell,88e1149r";
 121                                 marvell,reg-init = <3 0x10 0 0x5777>,
 122                                         <3 0x11 0 0x00aa>,
 123                                         <3 0x12 0 0x4105>,
 124                                         <3 0x13 0 0x0a60>;
 125                         };
 126                         phy42: ethernet-phy@2 {
 127                                 cavium,qlm-trim = "0,sgmii";
 128                                 reg = <2>;
 129                                 compatible = "marvell,88e1149r";
 130                                 marvell,reg-init = <3 0x10 0 0x5777>,
 131                                         <3 0x11 0 0x00aa>,
 132                                         <3 0x12 0 0x4105>,
 133                                         <3 0x13 0 0x0a60>;
 134                         };
 135                         phy43: ethernet-phy@3 {
 136                                 cavium,qlm-trim = "0,sgmii";
 137                                 reg = <3>;
 138                                 compatible = "marvell,88e1149r";
 139                                 marvell,reg-init = <3 0x10 0 0x5777>,
 140                                         <3 0x11 0 0x00aa>,
 141                                         <3 0x12 0 0x4105>,
 142                                         <3 0x13 0 0x0a60>;
 143                         };
 144                         phy44: ethernet-phy@4 {
 145                                 cavium,qlm-trim = "0,sgmii";
 146                                 reg = <4>;
 147                                 compatible = "marvell,88e1149r";
 148                                 marvell,reg-init = <3 0x10 0 0x5777>,
 149                                         <3 0x11 0 0x00aa>,
 150                                         <3 0x12 0 0x4105>,
 151                                         <3 0x13 0 0x0a60>;
 152                         };
 153                 };
 154
 155                 smi2: mdio@1180000003900 {
 156                         compatible = "cavium,octeon-3860-mdio";
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         reg = <0x11800 0x00003900 0x0 0x40>;
 160
 161                         phy21: ethernet-phy@1 {
 162                                 cavium,qlm-trim = "2,sgmii";
 163                                 reg = <1>;
 164                                 compatible = "marvell,88e1149r";
 165                                 marvell,reg-init = <3 0x10 0 0x5777>,
 166                                         <3 0x11 0 0x00aa>,
 167                                         <3 0x12 0 0x4105>,
 168                                         <3 0x13 0 0x0a60>;
 169                         };
 170                         phy22: ethernet-phy@2 {
 171                                 cavium,qlm-trim = "2,sgmii";
 172                                 reg = <2>;
 173                                 compatible = "marvell,88e1149r";
 174                                 marvell,reg-init = <3 0x10 0 0x5777>,
 175                                         <3 0x11 0 0x00aa>,
 176                                         <3 0x12 0 0x4105>,
 177                                         <3 0x13 0 0x0a60>;
 178                         };
 179                         phy23: ethernet-phy@3 {
 180                                 cavium,qlm-trim = "2,sgmii";
 181                                 reg = <3>;
 182                                 compatible = "marvell,88e1149r";
 183                                 marvell,reg-init = <3 0x10 0 0x5777>,
 184                                         <3 0x11 0 0x00aa>,
 185                                         <3 0x12 0 0x4105>,
 186                                         <3 0x13 0 0x0a60>;
 187                         };
 188                         phy24: ethernet-phy@4 {
 189                                 cavium,qlm-trim = "2,sgmii";
 190                                 reg = <4>;
 191                                 compatible = "marvell,88e1149r";
 192                                 marvell,reg-init = <3 0x10 0 0x5777>,
 193                                         <3 0x11 0 0x00aa>,
 194                                         <3 0x12 0 0x4105>,
 195                                         <3 0x13 0 0x0a60>;
 196                         };
 197                 };
 198
 199                 smi3: mdio@1180000003980 {
 200                         compatible = "cavium,octeon-3860-mdio";
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         reg = <0x11800 0x00003980 0x0 0x40>;
 204
 205                         phy11: ethernet-phy@1 {
 206                                 cavium,qlm-trim = "3,sgmii";
 207                                 reg = <1>;
 208                                 compatible = "marvell,88e1149r";
 209                                 marvell,reg-init = <3 0x10 0 0x5777>,
 210                                         <3 0x11 0 0x00aa>,
 211                                         <3 0x12 0 0x4105>,
 212                                         <3 0x13 0 0x0a60>;
 213                         };
 214                         phy12: ethernet-phy@2 {
 215                                 cavium,qlm-trim = "3,sgmii";
 216                                 reg = <2>;
 217                                 compatible = "marvell,88e1149r";
 218                                 marvell,reg-init = <3 0x10 0 0x5777>,
 219                                         <3 0x11 0 0x00aa>,
 220                                         <3 0x12 0 0x4105>,
 221                                         <3 0x13 0 0x0a60>;
 222                         };
 223                         phy13: ethernet-phy@3 {
 224                                 cavium,qlm-trim = "3,sgmii";
 225                                 reg = <3>;
 226                                 compatible = "marvell,88e1149r";
 227                                 marvell,reg-init = <3 0x10 0 0x5777>,
 228                                         <3 0x11 0 0x00aa>,
 229                                         <3 0x12 0 0x4105>,
 230                                         <3 0x13 0 0x0a60>;
 231                         };
 232                         phy14: ethernet-phy@4 {
 233                                 cavium,qlm-trim = "3,sgmii";
 234                                 reg = <4>;
 235                                 compatible = "marvell,88e1149r";
 236                                 marvell,reg-init = <3 0x10 0 0x5777>,
 237                                         <3 0x11 0 0x00aa>,
 238                                         <3 0x12 0 0x4105>,
 239                                         <3 0x13 0 0x0a60>;
 240                         };
 241                 };
 242
 243                 mix0: ethernet@1070000100000 {
 244                         compatible = "cavium,octeon-5750-mix";
 245                         reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
 246                               <0x11800 0xE0000000 0x0 0x300>, /* AGL */
 247                               <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
 248                               <0x11800 0xE0002000 0x0 0x8>;   /* AGL_PRT_CTL */
 249                         cell-index = <0>;
 250                         interrupts = <6 40>, <6 32>;
 251                         local-mac-address = [ 00 00 00 00 00 00 ];
 252                         phy-handle = <&phy0>;
 253                 };
 254
 255                 pip: pip@11800a0000000 {
 256                         compatible = "cavium,octeon-3860-pip";
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         reg = <0x11800 0xa0000000 0x0 0x2000>;
 260
 261                         interface@4 {
 262                                 compatible = "cavium,octeon-3860-pip-interface";
 263                                 #address-cells = <1>;
 264                                 #size-cells = <0>;
 265                                 reg = <0x4>; /* interface */
 266
 267                                 ethernet@0 {
 268                                         compatible = "cavium,octeon-3860-pip-port";
 269                                         reg = <0x0>; /* Port */
 270                                         local-mac-address = [ 00 00 00 00 00 00 ];
 271                                         phy-handle = <&phy1>;
 272                                 };
 273                                 ethernet@1 {
 274                                         compatible = "cavium,octeon-3860-pip-port";
 275                                         reg = <0x1>; /* Port */
 276                                         local-mac-address = [ 00 00 00 00 00 00 ];
 277                                         phy-handle = <&phy2>;
 278                                 };
 279                                 ethernet@2 {
 280                                         compatible = "cavium,octeon-3860-pip-port";
 281                                         reg = <0x2>; /* Port */
 282                                         local-mac-address = [ 00 00 00 00 00 00 ];
 283                                         phy-handle = <&phy3>;
 284                                 };
 285                                 ethernet@3 {
 286                                         compatible = "cavium,octeon-3860-pip-port";
 287                                         reg = <0x3>; /* Port */
 288                                         local-mac-address = [ 00 00 00 00 00 00 ];
 289                                         phy-handle = <&phy4>;
 290                                 };
 291                         };
 292
 293                         interface@3 {
 294                                 compatible = "cavium,octeon-3860-pip-interface";
 295                                 #address-cells = <1>;
 296                                 #size-cells = <0>;
 297                                 reg = <0x3>; /* interface */
 298
 299                                 ethernet@0 {
 300                                         compatible = "cavium,octeon-3860-pip-port";
 301                                         reg = <0x0>; /* Port */
 302                                         local-mac-address = [ 00 00 00 00 00 00 ];
 303                                         phy-handle = <&phy11>;
 304                                 };
 305                                 ethernet@1 {
 306                                         compatible = "cavium,octeon-3860-pip-port";
 307                                         reg = <0x1>; /* Port */
 308                                         local-mac-address = [ 00 00 00 00 00 00 ];
 309                                         phy-handle = <&phy12>;
 310                                 };
 311                                 ethernet@2 {
 312                                         compatible = "cavium,octeon-3860-pip-port";
 313                                         reg = <0x2>; /* Port */
 314                                         local-mac-address = [ 00 00 00 00 00 00 ];
 315                                         phy-handle = <&phy13>;
 316                                 };
 317                                 ethernet@3 {
 318                                         compatible = "cavium,octeon-3860-pip-port";
 319                                         reg = <0x3>; /* Port */
 320                                         local-mac-address = [ 00 00 00 00 00 00 ];
 321                                         phy-handle = <&phy14>;
 322                                 };
 323                         };
 324
 325                         interface@2 {
 326                                 compatible = "cavium,octeon-3860-pip-interface";
 327                                 #address-cells = <1>;
 328                                 #size-cells = <0>;
 329                                 reg = <0x2>; /* interface */
 330
 331                                 ethernet@0 {
 332                                         compatible = "cavium,octeon-3860-pip-port";
 333                                         reg = <0x0>; /* Port */
 334                                         local-mac-address = [ 00 00 00 00 00 00 ];
 335                                         phy-handle = <&phy21>;
 336                                 };
 337                                 ethernet@1 {
 338                                         compatible = "cavium,octeon-3860-pip-port";
 339                                         reg = <0x1>; /* Port */
 340                                         local-mac-address = [ 00 00 00 00 00 00 ];
 341                                         phy-handle = <&phy22>;
 342                                 };
 343                                 ethernet@2 {
 344                                         compatible = "cavium,octeon-3860-pip-port";
 345                                         reg = <0x2>; /* Port */
 346                                         local-mac-address = [ 00 00 00 00 00 00 ];
 347                                         phy-handle = <&phy23>;
 348                                 };
 349                                 ethernet@3 {
 350                                         compatible = "cavium,octeon-3860-pip-port";
 351                                         reg = <0x3>; /* Port */
 352                                         local-mac-address = [ 00 00 00 00 00 00 ];
 353                                         phy-handle = <&phy24>;
 354                                 };
 355                         };
 356
 357                         interface@1 {
 358                                 compatible = "cavium,octeon-3860-pip-interface";
 359                                 #address-cells = <1>;
 360                                 #size-cells = <0>;
 361                                 reg = <0x1>; /* interface */
 362
 363                                 ethernet@0 {
 364                                         compatible = "cavium,octeon-3860-pip-port";
 365                                         reg = <0x0>; /* Port */
 366                                         local-mac-address = [ 00 00 00 00 00 00 ];
 367                                 };
 368                         };
 369
 370                         interface@0 {
 371                                 compatible = "cavium,octeon-3860-pip-interface";
 372                                 #address-cells = <1>;
 373                                 #size-cells = <0>;
 374                                 reg = <0x0>; /* interface */
 375
 376                                 ethernet@0 {
 377                                         compatible = "cavium,octeon-3860-pip-port";
 378                                         reg = <0x0>; /* Port */
 379                                         local-mac-address = [ 00 00 00 00 00 00 ];
 380                                         phy-handle = <&phy41>;
 381                                 };
 382                                 ethernet@1 {
 383                                         compatible = "cavium,octeon-3860-pip-port";
 384                                         reg = <0x1>; /* Port */
 385                                         local-mac-address = [ 00 00 00 00 00 00 ];
 386                                         phy-handle = <&phy42>;
 387                                 };
 388                                 ethernet@2 {
 389                                         compatible = "cavium,octeon-3860-pip-port";
 390                                         reg = <0x2>; /* Port */
 391                                         local-mac-address = [ 00 00 00 00 00 00 ];
 392                                         phy-handle = <&phy43>;
 393                                 };
 394                                 ethernet@3 {
 395                                         compatible = "cavium,octeon-3860-pip-port";
 396                                         reg = <0x3>; /* Port */
 397                                         local-mac-address = [ 00 00 00 00 00 00 ];
 398                                         phy-handle = <&phy44>;
 399                                 };
 400                         };
 401                 };
 402
 403                 twsi0: i2c@1180000001000 {
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         compatible = "cavium,octeon-3860-twsi";
 407                         reg = <0x11800 0x00001000 0x0 0x200>;
 408                         interrupts = <3 32>;
 409                         clock-frequency = <100000>;
 410
 411                         rtc@68 {
 412                                 compatible = "dallas,ds1337";
 413                                 reg = <0x68>;
 414                         };
 415                         tmp@4c {
 416                                 compatible = "ti,tmp421";
 417                                 reg = <0x4c>;
 418                         };
 419                 };
 420
 421                 twsi1: i2c@1180000001200 {
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         compatible = "cavium,octeon-3860-twsi";
 425                         reg = <0x11800 0x00001200 0x0 0x200>;
 426                         interrupts = <3 33>;
 427                         clock-frequency = <100000>;
 428                 };
 429
 430                 uart0: serial@1180000000800 {
 431                         compatible = "cavium,octeon-3860-uart","ns16550";
 432                         reg = <0x11800 0x00000800 0x0 0x400>;
 433                         clock-frequency = <0>;
 434                         current-speed = <115200>;
 435                         reg-shift = <3>;
 436                         interrupts = <3 36>;
 437                 };
 438
 439                 uart1: serial@1180000000c00 {
 440                         compatible = "cavium,octeon-3860-uart","ns16550";
 441                         reg = <0x11800 0x00000c00 0x0 0x400>;
 442                         clock-frequency = <0>;
 443                         current-speed = <115200>;
 444                         reg-shift = <3>;
 445                         interrupts = <3 37>;
 446                 };
 447
 448                 bootbus: bootbus@1180000000000 {
 449                         compatible = "cavium,octeon-3860-bootbus";
 450                         reg = <0x11800 0x00000000 0x0 0x200>;
 451                         /* The chip select number and offset */
 452                         #address-cells = <2>;
 453                         /* The size of the chip select region */
 454                         #size-cells = <1>;
 455                         ranges = <0 0  0       0x1f400000  0xc00000>,
 456                                  <1 0  0x10000 0x30000000  0>,
 457                                  <2 0  0x10000 0x40000000  0>,
 458                                  <3 0  0x10000 0x50000000  0>,
 459                                  <4 0  0       0x1d020000  0x10000>,
 460                                  <5 0  0       0x1d040000  0x10000>,
 461                                  <6 0  0       0x1d050000  0x10000>,
 462                                  <7 0  0x10000 0x90000000  0>;
 463
 464                         cavium,cs-config@0 {
 465                                 compatible = "cavium,octeon-3860-bootbus-config";
 466                                 cavium,cs-index = <0>;
 467                                 cavium,t-adr  = <10>;
 468                                 cavium,t-ce   = <50>;
 469                                 cavium,t-oe   = <50>;
 470                                 cavium,t-we   = <35>;
 471                                 cavium,t-rd-hld = <25>;
 472                                 cavium,t-wr-hld = <35>;
 473                                 cavium,t-pause  = <0>;
 474                                 cavium,t-wait   = <300>;
 475                                 cavium,t-page   = <25>;
 476                                 cavium,t-rd-dly = <0>;
 477
 478                                 cavium,pages     = <0>;
 479                                 cavium,bus-width = <8>;
 480                         };
 481                         cavium,cs-config@4 {
 482                                 compatible = "cavium,octeon-3860-bootbus-config";
 483                                 cavium,cs-index = <4>;
 484                                 cavium,t-adr  = <320>;
 485                                 cavium,t-ce   = <320>;
 486                                 cavium,t-oe   = <320>;
 487                                 cavium,t-we   = <320>;
 488                                 cavium,t-rd-hld = <320>;
 489                                 cavium,t-wr-hld = <320>;
 490                                 cavium,t-pause  = <320>;
 491                                 cavium,t-wait   = <320>;
 492                                 cavium,t-page   = <320>;
 493                                 cavium,t-rd-dly = <0>;
 494
 495                                 cavium,pages     = <0>;
 496                                 cavium,bus-width = <8>;
 497                         };
 498                         cavium,cs-config@5 {
 499                                 compatible = "cavium,octeon-3860-bootbus-config";
 500                                 cavium,cs-index = <5>;
 501                                 cavium,t-adr  = <0>;
 502                                 cavium,t-ce   = <300>;
 503                                 cavium,t-oe   = <125>;
 504                                 cavium,t-we   = <150>;
 505                                 cavium,t-rd-hld = <100>;
 506                                 cavium,t-wr-hld = <300>;
 507                                 cavium,t-pause  = <0>;
 508                                 cavium,t-wait   = <300>;
 509                                 cavium,t-page   = <310>;
 510                                 cavium,t-rd-dly = <0>;
 511
 512                                 cavium,pages     = <0>;
 513                                 cavium,bus-width = <16>;
 514                         };
 515                         cavium,cs-config@6 {
 516                                 compatible = "cavium,octeon-3860-bootbus-config";
 517                                 cavium,cs-index = <6>;
 518                                 cavium,t-adr  = <0>;
 519                                 cavium,t-ce   = <30>;
 520                                 cavium,t-oe   = <125>;
 521                                 cavium,t-we   = <150>;
 522                                 cavium,t-rd-hld = <100>;
 523                                 cavium,t-wr-hld = <30>;
 524                                 cavium,t-pause  = <0>;
 525                                 cavium,t-wait   = <30>;
 526                                 cavium,t-page   = <310>;
 527                                 cavium,t-rd-dly = <0>;
 528
 529                                 cavium,pages     = <0>;
 530                                 cavium,wait-mode;
 531                                 cavium,bus-width = <16>;
 532                         };
 533
 534                         flash0: nor@0,0 {
 535                                 compatible = "cfi-flash";
 536                                 reg = <0 0 0x800000>;
 537                                 #address-cells = <1>;
 538                                 #size-cells = <1>;
 539
 540                                 partition@0 {
 541                                         label = "bootloader";
 542                                         reg = <0 0x200000>;
 543                                         read-only;
 544                                 };
 545                                 partition@200000 {
 546                                         label = "kernel";
 547                                         reg = <0x200000 0x200000>;
 548                                 };
 549                                 partition@400000 {
 550                                         label = "cramfs";
 551                                         reg = <0x400000 0x3fe000>;
 552                                 };
 553                                 partition@7fe000 {
 554                                         label = "environment";
 555                                         reg = <0x7fe000 0x2000>;
 556                                         read-only;
 557                                 };
 558                         };
 559
 560                         led0: led-display@4,0 {
 561                                 compatible = "avago,hdsp-253x";
 562                                 reg = <4 0x20 0x20>, <4 0 0x20>;
 563                         };
 564
 565                         compact-flash@5,0 {
 566                                 compatible = "cavium,ebt3000-compact-flash";
 567                                 reg = <5 0 0x10000>, <6 0 0x10000>;
 568                                 cavium,bus-width = <16>;
 569                                 cavium,true-ide;
 570                                 cavium,dma-engine-handle = <&dma0>;
 571                         };
 572                 };
 573
 574                 dma0: dma-engine@1180000000100 {
 575                         compatible = "cavium,octeon-5750-bootbus-dma";
 576                         reg = <0x11800 0x00000100 0x0 0x8>;
 577                         interrupts = <0 63>;
 578                 };
 579                 dma1: dma-engine@1180000000108 {
 580                         compatible = "cavium,octeon-5750-bootbus-dma";
 581                         reg = <0x11800 0x00000108 0x0 0x8>;
 582                         interrupts = <0 63>;
 583                 };
 584
 585                 uctl: uctl@118006f000000 {
 586                         compatible = "cavium,octeon-6335-uctl";
 587                         reg = <0x11800 0x6f000000 0x0 0x100>;
 588                         ranges; /* Direct mapping */
 589                         #address-cells = <2>;
 590                         #size-cells = <2>;
 591                         /* 12MHz, 24MHz and 48MHz allowed */
 592                         refclk-frequency = <12000000>;
 593                         /* Either "crystal" or "external" */
 594                         refclk-type = "crystal";
 595
 596                         ehci@16f0000000000 {
 597                                 compatible = "cavium,octeon-6335-ehci","usb-ehci";
 598                                 reg = <0x16f00 0x00000000 0x0 0x100>;
 599                                 interrupts = <3 44>;
 600                                 big-endian-regs;
 601                         };
 602                         ohci@16f0000000400 {
 603                                 compatible = "cavium,octeon-6335-ohci","usb-ohci";
 604                                 reg = <0x16f00 0x00000400 0x0 0x100>;
 605                                 interrupts = <3 44>;
 606                                 big-endian-regs;
 607                         };
 608                 };
 609         };
 610
 611         aliases {
 612                 mix0 = &mix0;
 613                 pip = &pip;
 614                 smi0 = &smi0;
 615                 smi1 = &smi1;
 616                 smi2 = &smi2;
 617                 smi3 = &smi3;
 618                 twsi0 = &twsi0;
 619                 twsi1 = &twsi1;
 620                 uart0 = &uart0;
 621                 uart1 = &uart1;
 622                 uctl = &uctl;
 623                 led0 = &led0;
 624                 flash0 = &flash0;
 625         };
 626  };