arch/mips/boot/dts/img/boston.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/clock/boston-clock.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/interrupt-controller/mips-gic.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         compatible = "img,boston";
  13
  14         chosen {
  15                 stdout-path = "uart0:115200";
  16         };
  17
  18         aliases {
  19                 uart0 = &uart0;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "img,mips";
  29                         reg = <0>;
  30                         clocks = <&clk_boston BOSTON_CLK_CPU>;
  31                 };
  32         };
  33
  34         memory@0 {
  35                 device_type = "memory";
  36                 reg = <0x00000000 0x10000000>;
  37         };
  38
  39         pci0: pci@10000000 {
  40                 compatible = "xlnx,axi-pcie-host-1.00.a";
  41                 device_type = "pci";
  42                 reg = <0x10000000 0x2000000>;
  43
  44                 #address-cells = <3>;
  45                 #size-cells = <2>;
  46                 #interrupt-cells = <1>;
  47
  48                 interrupt-parent = <&gic>;
  49                 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
  50
  51                 ranges = <0x02000000 0 0x40000000
  52                           0x40000000 0 0x40000000>;
  53
  54                 bus-range = <0x00 0xff>;
  55
  56                 interrupt-map-mask = <0 0 0 7>;
  57                 interrupt-map = <0 0 0 1 &pci0_intc 1>,
  58                                 <0 0 0 2 &pci0_intc 2>,
  59                                 <0 0 0 3 &pci0_intc 3>,
  60                                 <0 0 0 4 &pci0_intc 4>;
  61
  62                 pci0_intc: interrupt-controller {
  63                         interrupt-controller;
  64                         #address-cells = <0>;
  65                         #interrupt-cells = <1>;
  66                 };
  67         };
  68
  69         pci1: pci@12000000 {
  70                 compatible = "xlnx,axi-pcie-host-1.00.a";
  71                 device_type = "pci";
  72                 reg = <0x12000000 0x2000000>;
  73
  74                 #address-cells = <3>;
  75                 #size-cells = <2>;
  76                 #interrupt-cells = <1>;
  77
  78                 interrupt-parent = <&gic>;
  79                 interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
  80
  81                 ranges = <0x02000000 0 0x20000000
  82                           0x20000000 0 0x20000000>;
  83
  84                 bus-range = <0x00 0xff>;
  85
  86                 interrupt-map-mask = <0 0 0 7>;
  87                 interrupt-map = <0 0 0 1 &pci1_intc 1>,
  88                                 <0 0 0 2 &pci1_intc 2>,
  89                                 <0 0 0 3 &pci1_intc 3>,
  90                                 <0 0 0 4 &pci1_intc 4>;
  91
  92                 pci1_intc: interrupt-controller {
  93                         interrupt-controller;
  94                         #address-cells = <0>;
  95                         #interrupt-cells = <1>;
  96                 };
  97         };
  98
  99         pci2: pci@14000000 {
 100                 compatible = "xlnx,axi-pcie-host-1.00.a";
 101                 device_type = "pci";
 102                 reg = <0x14000000 0x2000000>;
 103
 104                 #address-cells = <3>;
 105                 #size-cells = <2>;
 106                 #interrupt-cells = <1>;
 107
 108                 interrupt-parent = <&gic>;
 109                 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
 110
 111                 ranges = <0x02000000 0 0x16000000
 112                           0x16000000 0 0x100000>;
 113
 114                 bus-range = <0x00 0xff>;
 115
 116                 interrupt-map-mask = <0 0 0 7>;
 117                 interrupt-map = <0 0 0 1 &pci2_intc 1>,
 118                                 <0 0 0 2 &pci2_intc 2>,
 119                                 <0 0 0 3 &pci2_intc 3>,
 120                                 <0 0 0 4 &pci2_intc 4>;
 121
 122                 pci2_intc: interrupt-controller {
 123                         interrupt-controller;
 124                         #address-cells = <0>;
 125                         #interrupt-cells = <1>;
 126                 };
 127
 128                 pci2_root@0,0,0 {
 129                         compatible = "pci10ee,7021";
 130                         reg = <0x00000000 0 0 0 0>;
 131
 132                         #address-cells = <3>;
 133                         #size-cells = <2>;
 134                         #interrupt-cells = <1>;
 135
 136                         eg20t_bridge@1,0,0 {
 137                                 compatible = "pci8086,8800";
 138                                 reg = <0x00010000 0 0 0 0>;
 139
 140                                 #address-cells = <3>;
 141                                 #size-cells = <2>;
 142                                 #interrupt-cells = <1>;
 143
 144                                 eg20t_phub@2,0,0 {
 145                                         compatible = "pci8086,8801";
 146                                         reg = <0x00020000 0 0 0 0>;
 147                                         intel,eg20t-prefetch = <0>;
 148                                 };
 149
 150                                 eg20t_mac@2,0,1 {
 151                                         compatible = "pci8086,8802";
 152                                         reg = <0x00020100 0 0 0 0>;
 153                                         phy-reset-gpios = <&eg20t_gpio 6
 154                                                            GPIO_ACTIVE_LOW>;
 155                                 };
 156
 157                                 eg20t_gpio: eg20t_gpio@2,0,2 {
 158                                         compatible = "pci8086,8803";
 159                                         reg = <0x00020200 0 0 0 0>;
 160
 161                                         gpio-controller;
 162                                         #gpio-cells = <2>;
 163                                 };
 164
 165                                 eg20t_i2c@2,12,2 {
 166                                         compatible = "pci8086,8817";
 167                                         reg = <0x00026200 0 0 0 0>;
 168
 169                                         #address-cells = <1>;
 170                                         #size-cells = <0>;
 171
 172                                         rtc@0x68 {
 173                                                 compatible = "st,m41t81s";
 174                                                 reg = <0x68>;
 175                                         };
 176                                 };
 177                         };
 178                 };
 179         };
 180
 181         gic: interrupt-controller@16120000 {
 182                 compatible = "mti,gic";
 183                 reg = <0x16120000 0x20000>;
 184
 185                 interrupt-controller;
 186                 #interrupt-cells = <3>;
 187
 188                 timer {
 189                         compatible = "mti,gic-timer";
 190                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 191                         clocks = <&clk_boston BOSTON_CLK_CPU>;
 192                 };
 193         };
 194
 195         cdmm@16140000 {
 196                 compatible = "mti,mips-cdmm";
 197                 reg = <0x16140000 0x8000>;
 198         };
 199
 200         cpc@16200000 {
 201                 compatible = "mti,mips-cpc";
 202                 reg = <0x16200000 0x8000>;
 203         };
 204
 205         plat_regs: system-controller@17ffd000 {
 206                 compatible = "img,boston-platform-regs", "syscon";
 207                 reg = <0x17ffd000 0x1000>;
 208
 209                 clk_boston: clock {
 210                         compatible = "img,boston-clock";
 211                         #clock-cells = <1>;
 212                 };
 213         };
 214
 215         reboot: syscon-reboot {
 216                 compatible = "syscon-reboot";
 217                 regmap = <&plat_regs>;
 218                 offset = <0x10>;
 219                 mask = <0x10>;
 220         };
 221
 222         uart0: uart@17ffe000 {
 223                 compatible = "ns16550a";
 224                 reg = <0x17ffe000 0x1000>;
 225                 reg-shift = <2>;
 226
 227                 interrupt-parent = <&gic>;
 228                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 229
 230                 clocks = <&clk_boston BOSTON_CLK_SYS>;
 231         };
 232
 233         lcd: lcd@17fff000 {
 234                 compatible = "img,boston-lcd";
 235                 reg = <0x17fff000 0x8>;
 236         };
 237 };