1 // SPDX-License-Identifier: GPL-2.0
7 compatible = "gcw,zero", "ingenic,jz4770";
18 stdout-path = "serial2:57600n8";
22 compatible = "simple-bus";
28 compatible = "usb-nop-xceiv";
29 clocks = <&cgu JZ4770_CLK_OTG_PHY>;
30 clock-names = "main_clk";
36 clock-frequency = <12000000>;
44 /* Put high-speed peripherals under PLL1, such that we can change the
45 * PLL0 frequency on demand without having to suspend peripherals.
46 * We use a rate of 432 MHz, which is the least common multiple of
47 * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
50 <&cgu JZ4770_CLK_PLL1>,
51 <&cgu JZ4770_CLK_UHC>;
52 assigned-clock-parents =
54 <&cgu JZ4770_CLK_PLL1>;
55 assigned-clock-rates =
60 /* The WiFi module is connected to the UHC. */