arch/mips/cavium-octeon/octeon-platform.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004-2016 Cavium Networks
   7  * Copyright (C) 2008 Wind River Systems
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/delay.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/of_fdt.h>
  15 #include <linux/libfdt.h>
  16 #include <linux/usb/ehci_def.h>
  17 #include <linux/usb/ehci_pdriver.h>
  18 #include <linux/usb/ohci_pdriver.h>
  19
  20 #include <asm/octeon/octeon.h>
  21 #include <asm/octeon/cvmx-helper-board.h>
  22 #include <asm/octeon/cvmx-uctlx-defs.h>
  23
  24 #define CVMX_UAHCX_EHCI_USBCMD  (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
  25 #define CVMX_UAHCX_OHCI_USBCMD  (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
  26
  27 /* Octeon Random Number Generator.  */
  28 static int __init octeon_rng_device_init(void)
  29 {
  30         struct platform_device *pd;
  31         int ret = 0;
  32
  33         struct resource rng_resources[] = {
  34                 {
  35                         .flags  = IORESOURCE_MEM,
  36                         .start  = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
  37                         .end    = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
  38                 }, {
  39                         .flags  = IORESOURCE_MEM,
  40                         .start  = cvmx_build_io_address(8, 0),
  41                         .end    = cvmx_build_io_address(8, 0) + 0x7
  42                 }
  43         };
  44
  45         pd = platform_device_alloc("octeon_rng", -1);
  46         if (!pd) {
  47                 ret = -ENOMEM;
  48                 goto out;
  49         }
  50
  51         ret = platform_device_add_resources(pd, rng_resources,
  52                                             ARRAY_SIZE(rng_resources));
  53         if (ret)
  54                 goto fail;
  55
  56         ret = platform_device_add(pd);
  57         if (ret)
  58                 goto fail;
  59
  60         return ret;
  61 fail:
  62         platform_device_put(pd);
  63
  64 out:
  65         return ret;
  66 }
  67 device_initcall(octeon_rng_device_init);
  68
  69 #ifdef CONFIG_USB
  70
  71 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
  72
  73 static int octeon2_usb_clock_start_cnt;
  74
  75 static int __init octeon2_usb_reset(void)
  76 {
  77         union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
  78         u32 ucmd;
  79
  80         if (!OCTEON_IS_OCTEON2())
  81                 return 0;
  82
  83         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
  84         if (clk_rst_ctl.s.hrst) {
  85                 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
  86                 ucmd &= ~CMD_RUN;
  87                 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
  88                 mdelay(2);
  89                 ucmd |= CMD_RESET;
  90                 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
  91                 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
  92                 ucmd |= CMD_RUN;
  93                 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
  94         }
  95
  96         return 0;
  97 }
  98 arch_initcall(octeon2_usb_reset);
  99
 100 static void octeon2_usb_clocks_start(struct device *dev)
 101 {
 102         u64 div;
 103         union cvmx_uctlx_if_ena if_ena;
 104         union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
 105         union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
 106         int i;
 107         unsigned long io_clk_64_to_ns;
 108         u32 clock_rate = 12000000;
 109         bool is_crystal_clock = false;
 110
 111
 112         mutex_lock(&octeon2_usb_clocks_mutex);
 113
 114         octeon2_usb_clock_start_cnt++;
 115         if (octeon2_usb_clock_start_cnt != 1)
 116                 goto exit;
 117
 118         io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
 119
 120         if (dev->of_node) {
 121                 struct device_node *uctl_node;
 122                 const char *clock_type;
 123
 124                 uctl_node = of_get_parent(dev->of_node);
 125                 if (!uctl_node) {
 126                         dev_err(dev, "No UCTL device node\n");
 127                         goto exit;
 128                 }
 129                 i = of_property_read_u32(uctl_node,
 130                                          "refclk-frequency", &clock_rate);
 131                 if (i) {
 132                         dev_err(dev, "No UCTL \"refclk-frequency\"\n");
 133                         of_node_put(uctl_node);
 134                         goto exit;
 135                 }
 136                 i = of_property_read_string(uctl_node,
 137                                             "refclk-type", &clock_type);
 138                 of_node_put(uctl_node);
 139                 if (!i && strcmp("crystal", clock_type) == 0)
 140                         is_crystal_clock = true;
 141         }
 142
 143         /*
 144          * Step 1: Wait for voltages stable.  That surely happened
 145          * before starting the kernel.
 146          *
 147          * Step 2: Enable  SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
 148          */
 149         if_ena.u64 = 0;
 150         if_ena.s.en = 1;
 151         cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
 152
 153         for (i = 0; i <= 1; i++) {
 154                 port_ctl_status.u64 =
 155                         cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
 156                 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
 157                 port_ctl_status.s.txvreftune = 15;
 158                 port_ctl_status.s.txrisetune = 1;
 159                 port_ctl_status.s.txpreemphasistune = 1;
 160                 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
 161                                port_ctl_status.u64);
 162         }
 163
 164         /* Step 3: Configure the reference clock, PHY, and HCLK */
 165         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
 166
 167         /*
 168          * If the UCTL looks like it has already been started, skip
 169          * the initialization, otherwise bus errors are obtained.
 170          */
 171         if (clk_rst_ctl.s.hrst)
 172                 goto end_clock;
 173         /* 3a */
 174         clk_rst_ctl.s.p_por = 1;
 175         clk_rst_ctl.s.hrst = 0;
 176         clk_rst_ctl.s.p_prst = 0;
 177         clk_rst_ctl.s.h_clkdiv_rst = 0;
 178         clk_rst_ctl.s.o_clkdiv_rst = 0;
 179         clk_rst_ctl.s.h_clkdiv_en = 0;
 180         clk_rst_ctl.s.o_clkdiv_en = 0;
 181         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 182
 183         /* 3b */
 184         clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
 185         switch (clock_rate) {
 186         default:
 187                 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
 188                         clock_rate);
 189                 /* Fall through */
 190         case 12000000:
 191                 clk_rst_ctl.s.p_refclk_div = 0;
 192                 break;
 193         case 24000000:
 194                 clk_rst_ctl.s.p_refclk_div = 1;
 195                 break;
 196         case 48000000:
 197                 clk_rst_ctl.s.p_refclk_div = 2;
 198                 break;
 199         }
 200         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 201
 202         /* 3c */
 203         div = octeon_get_io_clock_rate() / 130000000ull;
 204
 205         switch (div) {
 206         case 0:
 207                 div = 1;
 208                 break;
 209         case 1:
 210         case 2:
 211         case 3:
 212         case 4:
 213                 break;
 214         case 5:
 215                 div = 4;
 216                 break;
 217         case 6:
 218         case 7:
 219                 div = 6;
 220                 break;
 221         case 8:
 222         case 9:
 223         case 10:
 224         case 11:
 225                 div = 8;
 226                 break;
 227         default:
 228                 div = 12;
 229                 break;
 230         }
 231         clk_rst_ctl.s.h_div = div;
 232         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 233         /* Read it back, */
 234         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
 235         clk_rst_ctl.s.h_clkdiv_en = 1;
 236         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 237         /* 3d */
 238         clk_rst_ctl.s.h_clkdiv_rst = 1;
 239         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 240
 241         /* 3e: delay 64 io clocks */
 242         ndelay(io_clk_64_to_ns);
 243
 244         /*
 245          * Step 4: Program the power-on reset field in the UCTL
 246          * clock-reset-control register.
 247          */
 248         clk_rst_ctl.s.p_por = 0;
 249         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 250
 251         /* Step 5:    Wait 3 ms for the PHY clock to start. */
 252         mdelay(3);
 253
 254         /* Steps 6..9 for ATE only, are skipped. */
 255
 256         /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
 257         /* 10a */
 258         clk_rst_ctl.s.o_clkdiv_rst = 1;
 259         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 260
 261         /* 10b */
 262         clk_rst_ctl.s.o_clkdiv_en = 1;
 263         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 264
 265         /* 10c */
 266         ndelay(io_clk_64_to_ns);
 267
 268         /*
 269          * Step 11: Program the PHY reset field:
 270          * UCTL0_CLK_RST_CTL[P_PRST] = 1
 271          */
 272         clk_rst_ctl.s.p_prst = 1;
 273         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 274
 275         /* Step 11b */
 276         udelay(1);
 277
 278         /* Step 11c */
 279         clk_rst_ctl.s.p_prst = 0;
 280         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 281
 282         /* Step 11d */
 283         mdelay(1);
 284
 285         /* Step 11e */
 286         clk_rst_ctl.s.p_prst = 1;
 287         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 288
 289         /* Step 12: Wait 1 uS. */
 290         udelay(1);
 291
 292         /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
 293         clk_rst_ctl.s.hrst = 1;
 294         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 295
 296 end_clock:
 297         /* Set uSOF cycle period to 60,000 bits. */
 298         cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
 299
 300 exit:
 301         mutex_unlock(&octeon2_usb_clocks_mutex);
 302 }
 303
 304 static void octeon2_usb_clocks_stop(void)
 305 {
 306         mutex_lock(&octeon2_usb_clocks_mutex);
 307         octeon2_usb_clock_start_cnt--;
 308         mutex_unlock(&octeon2_usb_clocks_mutex);
 309 }
 310
 311 static int octeon_ehci_power_on(struct platform_device *pdev)
 312 {
 313         octeon2_usb_clocks_start(&pdev->dev);
 314         return 0;
 315 }
 316
 317 static void octeon_ehci_power_off(struct platform_device *pdev)
 318 {
 319         octeon2_usb_clocks_stop();
 320 }
 321
 322 static struct usb_ehci_pdata octeon_ehci_pdata = {
 323         /* Octeon EHCI matches CPU endianness. */
 324 #ifdef __BIG_ENDIAN
 325         .big_endian_mmio        = 1,
 326 #endif
 327         /*
 328          * We can DMA from anywhere. But the descriptors must be in
 329          * the lower 4GB.
 330          */
 331         .dma_mask_64    = 0,
 332         .power_on       = octeon_ehci_power_on,
 333         .power_off      = octeon_ehci_power_off,
 334 };
 335
 336 static void __init octeon_ehci_hw_start(struct device *dev)
 337 {
 338         union cvmx_uctlx_ehci_ctl ehci_ctl;
 339
 340         octeon2_usb_clocks_start(dev);
 341
 342         ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
 343         /* Use 64-bit addressing. */
 344         ehci_ctl.s.ehci_64b_addr_en = 1;
 345         ehci_ctl.s.l2c_addr_msb = 0;
 346 #ifdef __BIG_ENDIAN
 347         ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
 348         ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
 349 #else
 350         ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
 351         ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
 352         ehci_ctl.s.inv_reg_a2 = 1;
 353 #endif
 354         cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
 355
 356         octeon2_usb_clocks_stop();
 357 }
 358
 359 static int __init octeon_ehci_device_init(void)
 360 {
 361         struct platform_device *pd;
 362         struct device_node *ehci_node;
 363         int ret = 0;
 364
 365         ehci_node = of_find_node_by_name(NULL, "ehci");
 366         if (!ehci_node)
 367                 return 0;
 368
 369         pd = of_find_device_by_node(ehci_node);
 370         of_node_put(ehci_node);
 371         if (!pd)
 372                 return 0;
 373
 374         pd->dev.platform_data = &octeon_ehci_pdata;
 375         octeon_ehci_hw_start(&pd->dev);
 376
 377         return ret;
 378 }
 379 device_initcall(octeon_ehci_device_init);
 380
 381 static int octeon_ohci_power_on(struct platform_device *pdev)
 382 {
 383         octeon2_usb_clocks_start(&pdev->dev);
 384         return 0;
 385 }
 386
 387 static void octeon_ohci_power_off(struct platform_device *pdev)
 388 {
 389         octeon2_usb_clocks_stop();
 390 }
 391
 392 static struct usb_ohci_pdata octeon_ohci_pdata = {
 393         /* Octeon OHCI matches CPU endianness. */
 394 #ifdef __BIG_ENDIAN
 395         .big_endian_mmio        = 1,
 396 #endif
 397         .power_on       = octeon_ohci_power_on,
 398         .power_off      = octeon_ohci_power_off,
 399 };
 400
 401 static void __init octeon_ohci_hw_start(struct device *dev)
 402 {
 403         union cvmx_uctlx_ohci_ctl ohci_ctl;
 404
 405         octeon2_usb_clocks_start(dev);
 406
 407         ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
 408         ohci_ctl.s.l2c_addr_msb = 0;
 409 #ifdef __BIG_ENDIAN
 410         ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
 411         ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
 412 #else
 413         ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
 414         ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
 415         ohci_ctl.s.inv_reg_a2 = 1;
 416 #endif
 417         cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
 418
 419         octeon2_usb_clocks_stop();
 420 }
 421
 422 static int __init octeon_ohci_device_init(void)
 423 {
 424         struct platform_device *pd;
 425         struct device_node *ohci_node;
 426         int ret = 0;
 427
 428         ohci_node = of_find_node_by_name(NULL, "ohci");
 429         if (!ohci_node)
 430                 return 0;
 431
 432         pd = of_find_device_by_node(ohci_node);
 433         of_node_put(ohci_node);
 434         if (!pd)
 435                 return 0;
 436
 437         pd->dev.platform_data = &octeon_ohci_pdata;
 438         octeon_ohci_hw_start(&pd->dev);
 439
 440         return ret;
 441 }
 442 device_initcall(octeon_ohci_device_init);
 443
 444 #endif /* CONFIG_USB */
 445
 446
 447 static struct of_device_id __initdata octeon_ids[] = {
 448         { .compatible = "simple-bus", },
 449         { .compatible = "cavium,octeon-6335-uctl", },
 450         { .compatible = "cavium,octeon-5750-usbn", },
 451         { .compatible = "cavium,octeon-3860-bootbus", },
 452         { .compatible = "cavium,mdio-mux", },
 453         { .compatible = "gpio-leds", },
 454         {},
 455 };
 456
 457 static bool __init octeon_has_88e1145(void)
 458 {
 459         return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
 460                !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
 461                !OCTEON_IS_MODEL(OCTEON_CN56XX);
 462 }
 463
 464 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
 465 {
 466         const __be32 *phy_handle;
 467         const __be32 *alt_phy_handle;
 468         const __be32 *reg;
 469         u32 phandle;
 470         int phy;
 471         int alt_phy;
 472         const char *p;
 473         int current_len;
 474         char new_name[20];
 475
 476         phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
 477         if (!phy_handle)
 478                 return;
 479
 480         phandle = be32_to_cpup(phy_handle);
 481         phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
 482
 483         alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
 484         if (alt_phy_handle) {
 485                 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
 486                 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
 487         } else {
 488                 alt_phy = -1;
 489         }
 490
 491         if (phy_addr < 0 || phy < 0) {
 492                 /* Delete the PHY things */
 493                 fdt_nop_property(initial_boot_params, eth, "phy-handle");
 494                 /* This one may fail */
 495                 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
 496                 if (phy >= 0)
 497                         fdt_nop_node(initial_boot_params, phy);
 498                 if (alt_phy >= 0)
 499                         fdt_nop_node(initial_boot_params, alt_phy);
 500                 return;
 501         }
 502
 503         if (phy_addr >= 256 && alt_phy > 0) {
 504                 const struct fdt_property *phy_prop;
 505                 struct fdt_property *alt_prop;
 506                 fdt32_t phy_handle_name;
 507
 508                 /* Use the alt phy node instead.*/
 509                 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
 510                 phy_handle_name = phy_prop->nameoff;
 511                 fdt_nop_node(initial_boot_params, phy);
 512                 fdt_nop_property(initial_boot_params, eth, "phy-handle");
 513                 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
 514                 alt_prop->nameoff = phy_handle_name;
 515                 phy = alt_phy;
 516         }
 517
 518         phy_addr &= 0xff;
 519
 520         if (octeon_has_88e1145()) {
 521                 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
 522                 memset(new_name, 0, sizeof(new_name));
 523                 strcpy(new_name, "marvell,88e1145");
 524                 p = fdt_getprop(initial_boot_params, phy, "compatible",
 525                                 &current_len);
 526                 if (p && current_len >= strlen(new_name))
 527                         fdt_setprop_inplace(initial_boot_params, phy,
 528                                         "compatible", new_name, current_len);
 529         }
 530
 531         reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
 532         if (phy_addr == be32_to_cpup(reg))
 533                 return;
 534
 535         fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
 536
 537         snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
 538
 539         p = fdt_get_name(initial_boot_params, phy, &current_len);
 540         if (p && current_len == strlen(new_name))
 541                 fdt_set_name(initial_boot_params, phy, new_name);
 542         else
 543                 pr_err("Error: could not rename ethernet phy: <%s>", p);
 544 }
 545
 546 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
 547 {
 548         const u8 *old_mac;
 549         int old_len;
 550         u8 new_mac[6];
 551         u64 mac = *pmac;
 552         int r;
 553
 554         old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
 555                               &old_len);
 556         if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
 557                 return;
 558
 559         new_mac[0] = (mac >> 40) & 0xff;
 560         new_mac[1] = (mac >> 32) & 0xff;
 561         new_mac[2] = (mac >> 24) & 0xff;
 562         new_mac[3] = (mac >> 16) & 0xff;
 563         new_mac[4] = (mac >> 8) & 0xff;
 564         new_mac[5] = mac & 0xff;
 565
 566         r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
 567                                 new_mac, sizeof(new_mac));
 568
 569         if (r) {
 570                 pr_err("Setting \"local-mac-address\" failed %d", r);
 571                 return;
 572         }
 573         *pmac = mac + 1;
 574 }
 575
 576 static void __init octeon_fdt_rm_ethernet(int node)
 577 {
 578         const __be32 *phy_handle;
 579
 580         phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
 581         if (phy_handle) {
 582                 u32 ph = be32_to_cpup(phy_handle);
 583                 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
 584                 if (p >= 0)
 585                         fdt_nop_node(initial_boot_params, p);
 586         }
 587         fdt_nop_node(initial_boot_params, node);
 588 }
 589
 590 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
 591 {
 592         char name_buffer[20];
 593         int eth;
 594         int phy_addr;
 595         int ipd_port;
 596
 597         snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
 598         eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
 599         if (eth < 0)
 600                 return;
 601         if (p > max) {
 602                 pr_debug("Deleting port %x:%x\n", i, p);
 603                 octeon_fdt_rm_ethernet(eth);
 604                 return;
 605         }
 606         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 607                 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
 608         else
 609                 ipd_port = 16 * i + p;
 610
 611         phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
 612         octeon_fdt_set_phy(eth, phy_addr);
 613 }
 614
 615 static void __init octeon_fdt_pip_iface(int pip, int idx)
 616 {
 617         char name_buffer[20];
 618         int iface;
 619         int p;
 620         int count = 0;
 621
 622         snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
 623         iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
 624         if (iface < 0)
 625                 return;
 626
 627         if (cvmx_helper_interface_enumerate(idx) == 0)
 628                 count = cvmx_helper_ports_on_interface(idx);
 629
 630         for (p = 0; p < 16; p++)
 631                 octeon_fdt_pip_port(iface, idx, p, count - 1);
 632 }
 633
 634 void __init octeon_fill_mac_addresses(void)
 635 {
 636         const char *alias_prop;
 637         char name_buffer[20];
 638         u64 mac_addr_base;
 639         int aliases;
 640         int pip;
 641         int i;
 642
 643         aliases = fdt_path_offset(initial_boot_params, "/aliases");
 644         if (aliases < 0)
 645                 return;
 646
 647         mac_addr_base =
 648                 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
 649                 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
 650                 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
 651                 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
 652                 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
 653                  (octeon_bootinfo->mac_addr_base[5] & 0xffull);
 654
 655         for (i = 0; i < 2; i++) {
 656                 int mgmt;
 657
 658                 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
 659                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 660                                          name_buffer, NULL);
 661                 if (!alias_prop)
 662                         continue;
 663                 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
 664                 if (mgmt < 0)
 665                         continue;
 666                 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
 667         }
 668
 669         alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
 670         if (!alias_prop)
 671                 return;
 672
 673         pip = fdt_path_offset(initial_boot_params, alias_prop);
 674         if (pip < 0)
 675                 return;
 676
 677         for (i = 0; i <= 4; i++) {
 678                 int iface;
 679                 int p;
 680
 681                 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
 682                 iface = fdt_subnode_offset(initial_boot_params, pip,
 683                                            name_buffer);
 684                 if (iface < 0)
 685                         continue;
 686                 for (p = 0; p < 16; p++) {
 687                         int eth;
 688
 689                         snprintf(name_buffer, sizeof(name_buffer),
 690                                  "ethernet@%x", p);
 691                         eth = fdt_subnode_offset(initial_boot_params, iface,
 692                                                  name_buffer);
 693                         if (eth < 0)
 694                                 continue;
 695                         octeon_fdt_set_mac_addr(eth, &mac_addr_base);
 696                 }
 697         }
 698 }
 699
 700 int __init octeon_prune_device_tree(void)
 701 {
 702         int i, max_port, uart_mask;
 703         const char *pip_path;
 704         const char *alias_prop;
 705         char name_buffer[20];
 706         int aliases;
 707
 708         if (fdt_check_header(initial_boot_params))
 709                 panic("Corrupt Device Tree.");
 710
 711         WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
 712              "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
 713              cvmx_board_type_to_string(octeon_bootinfo->board_type));
 714
 715         aliases = fdt_path_offset(initial_boot_params, "/aliases");
 716         if (aliases < 0) {
 717                 pr_err("Error: No /aliases node in device tree.");
 718                 return -EINVAL;
 719         }
 720
 721         if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
 722                 max_port = 2;
 723         else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
 724                 max_port = 1;
 725         else
 726                 max_port = 0;
 727
 728         if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
 729                 max_port = 0;
 730
 731         for (i = 0; i < 2; i++) {
 732                 int mgmt;
 733                 snprintf(name_buffer, sizeof(name_buffer),
 734                          "mix%d", i);
 735                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 736                                         name_buffer, NULL);
 737                 if (alias_prop) {
 738                         mgmt = fdt_path_offset(initial_boot_params, alias_prop);
 739                         if (mgmt < 0)
 740                                 continue;
 741                         if (i >= max_port) {
 742                                 pr_debug("Deleting mix%d\n", i);
 743                                 octeon_fdt_rm_ethernet(mgmt);
 744                                 fdt_nop_property(initial_boot_params, aliases,
 745                                                  name_buffer);
 746                         } else {
 747                                 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
 748                                 octeon_fdt_set_phy(mgmt, phy_addr);
 749                         }
 750                 }
 751         }
 752
 753         pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
 754         if (pip_path) {
 755                 int pip = fdt_path_offset(initial_boot_params, pip_path);
 756                 if (pip  >= 0)
 757                         for (i = 0; i <= 4; i++)
 758                                 octeon_fdt_pip_iface(pip, i);
 759         }
 760
 761         /* I2C */
 762         if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
 763             OCTEON_IS_MODEL(OCTEON_CN63XX) ||
 764             OCTEON_IS_MODEL(OCTEON_CN68XX) ||
 765             OCTEON_IS_MODEL(OCTEON_CN56XX))
 766                 max_port = 2;
 767         else
 768                 max_port = 1;
 769
 770         for (i = 0; i < 2; i++) {
 771                 int i2c;
 772                 snprintf(name_buffer, sizeof(name_buffer),
 773                          "twsi%d", i);
 774                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 775                                         name_buffer, NULL);
 776
 777                 if (alias_prop) {
 778                         i2c = fdt_path_offset(initial_boot_params, alias_prop);
 779                         if (i2c < 0)
 780                                 continue;
 781                         if (i >= max_port) {
 782                                 pr_debug("Deleting twsi%d\n", i);
 783                                 fdt_nop_node(initial_boot_params, i2c);
 784                                 fdt_nop_property(initial_boot_params, aliases,
 785                                                  name_buffer);
 786                         }
 787                 }
 788         }
 789
 790         /* SMI/MDIO */
 791         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 792                 max_port = 4;
 793         else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
 794                  OCTEON_IS_MODEL(OCTEON_CN63XX) ||
 795                  OCTEON_IS_MODEL(OCTEON_CN56XX))
 796                 max_port = 2;
 797         else
 798                 max_port = 1;
 799
 800         for (i = 0; i < 2; i++) {
 801                 int i2c;
 802                 snprintf(name_buffer, sizeof(name_buffer),
 803                          "smi%d", i);
 804                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 805                                         name_buffer, NULL);
 806
 807                 if (alias_prop) {
 808                         i2c = fdt_path_offset(initial_boot_params, alias_prop);
 809                         if (i2c < 0)
 810                                 continue;
 811                         if (i >= max_port) {
 812                                 pr_debug("Deleting smi%d\n", i);
 813                                 fdt_nop_node(initial_boot_params, i2c);
 814                                 fdt_nop_property(initial_boot_params, aliases,
 815                                                  name_buffer);
 816                         }
 817                 }
 818         }
 819
 820         /* Serial */
 821         uart_mask = 3;
 822
 823         /* Right now CN52XX is the only chip with a third uart */
 824         if (OCTEON_IS_MODEL(OCTEON_CN52XX))
 825                 uart_mask |= 4; /* uart2 */
 826
 827         for (i = 0; i < 3; i++) {
 828                 int uart;
 829                 snprintf(name_buffer, sizeof(name_buffer),
 830                          "uart%d", i);
 831                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 832                                         name_buffer, NULL);
 833
 834                 if (alias_prop) {
 835                         uart = fdt_path_offset(initial_boot_params, alias_prop);
 836                         if (uart_mask & (1 << i)) {
 837                                 __be32 f;
 838
 839                                 f = cpu_to_be32(octeon_get_io_clock_rate());
 840                                 fdt_setprop_inplace(initial_boot_params,
 841                                                     uart, "clock-frequency",
 842                                                     &f, sizeof(f));
 843                                 continue;
 844                         }
 845                         pr_debug("Deleting uart%d\n", i);
 846                         fdt_nop_node(initial_boot_params, uart);
 847                         fdt_nop_property(initial_boot_params, aliases,
 848                                          name_buffer);
 849                 }
 850         }
 851
 852         /* Compact Flash */
 853         alias_prop = fdt_getprop(initial_boot_params, aliases,
 854                                  "cf0", NULL);
 855         if (alias_prop) {
 856                 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
 857                 unsigned long base_ptr, region_base, region_size;
 858                 unsigned long region1_base = 0;
 859                 unsigned long region1_size = 0;
 860                 int cs, bootbus;
 861                 bool is_16bit = false;
 862                 bool is_true_ide = false;
 863                 __be32 new_reg[6];
 864                 __be32 *ranges;
 865                 int len;
 866
 867                 int cf = fdt_path_offset(initial_boot_params, alias_prop);
 868                 base_ptr = 0;
 869                 if (octeon_bootinfo->major_version == 1
 870                         && octeon_bootinfo->minor_version >= 1) {
 871                         if (octeon_bootinfo->compact_flash_common_base_addr)
 872                                 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
 873                 } else {
 874                         base_ptr = 0x1d000800;
 875                 }
 876
 877                 if (!base_ptr)
 878                         goto no_cf;
 879
 880                 /* Find CS0 region. */
 881                 for (cs = 0; cs < 8; cs++) {
 882                         mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
 883                         region_base = mio_boot_reg_cfg.s.base << 16;
 884                         region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 885                         if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
 886                                 && base_ptr < region_base + region_size) {
 887                                 is_16bit = mio_boot_reg_cfg.s.width;
 888                                 break;
 889                         }
 890                 }
 891                 if (cs >= 7) {
 892                         /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
 893                         goto no_cf;
 894                 }
 895
 896                 if (!(base_ptr & 0xfffful)) {
 897                         /*
 898                          * Boot loader signals availability of DMA (true_ide
 899                          * mode) by setting low order bits of base_ptr to
 900                          * zero.
 901                          */
 902
 903                         /* Asume that CS1 immediately follows. */
 904                         mio_boot_reg_cfg.u64 =
 905                                 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
 906                         region1_base = mio_boot_reg_cfg.s.base << 16;
 907                         region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 908                         if (!mio_boot_reg_cfg.s.en)
 909                                 goto no_cf;
 910                         is_true_ide = true;
 911
 912                 } else {
 913                         fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
 914                         fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
 915                         if (!is_16bit) {
 916                                 __be32 width = cpu_to_be32(8);
 917                                 fdt_setprop_inplace(initial_boot_params, cf,
 918                                                 "cavium,bus-width", &width, sizeof(width));
 919                         }
 920                 }
 921                 new_reg[0] = cpu_to_be32(cs);
 922                 new_reg[1] = cpu_to_be32(0);
 923                 new_reg[2] = cpu_to_be32(0x10000);
 924                 new_reg[3] = cpu_to_be32(cs + 1);
 925                 new_reg[4] = cpu_to_be32(0);
 926                 new_reg[5] = cpu_to_be32(0x10000);
 927                 fdt_setprop_inplace(initial_boot_params, cf,
 928                                     "reg",  new_reg, sizeof(new_reg));
 929
 930                 bootbus = fdt_parent_offset(initial_boot_params, cf);
 931                 if (bootbus < 0)
 932                         goto no_cf;
 933                 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
 934                 if (!ranges || len < (5 * 8 * sizeof(__be32)))
 935                         goto no_cf;
 936
 937                 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
 938                 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
 939                 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
 940                 if (is_true_ide) {
 941                         cs++;
 942                         ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
 943                         ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
 944                         ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
 945                 }
 946                 goto end_cf;
 947 no_cf:
 948                 fdt_nop_node(initial_boot_params, cf);
 949
 950 end_cf:
 951                 ;
 952         }
 953
 954         /* 8 char LED */
 955         alias_prop = fdt_getprop(initial_boot_params, aliases,
 956                                  "led0", NULL);
 957         if (alias_prop) {
 958                 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
 959                 unsigned long base_ptr, region_base, region_size;
 960                 int cs, bootbus;
 961                 __be32 new_reg[6];
 962                 __be32 *ranges;
 963                 int len;
 964                 int led = fdt_path_offset(initial_boot_params, alias_prop);
 965
 966                 base_ptr = octeon_bootinfo->led_display_base_addr;
 967                 if (base_ptr == 0)
 968                         goto no_led;
 969                 /* Find CS0 region. */
 970                 for (cs = 0; cs < 8; cs++) {
 971                         mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
 972                         region_base = mio_boot_reg_cfg.s.base << 16;
 973                         region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 974                         if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
 975                                 && base_ptr < region_base + region_size)
 976                                 break;
 977                 }
 978
 979                 if (cs > 7)
 980                         goto no_led;
 981
 982                 new_reg[0] = cpu_to_be32(cs);
 983                 new_reg[1] = cpu_to_be32(0x20);
 984                 new_reg[2] = cpu_to_be32(0x20);
 985                 new_reg[3] = cpu_to_be32(cs);
 986                 new_reg[4] = cpu_to_be32(0);
 987                 new_reg[5] = cpu_to_be32(0x20);
 988                 fdt_setprop_inplace(initial_boot_params, led,
 989                                     "reg",  new_reg, sizeof(new_reg));
 990
 991                 bootbus = fdt_parent_offset(initial_boot_params, led);
 992                 if (bootbus < 0)
 993                         goto no_led;
 994                 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
 995                 if (!ranges || len < (5 * 8 * sizeof(__be32)))
 996                         goto no_led;
 997
 998                 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
 999                 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1000                 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1001                 goto end_led;
1002
1003 no_led:
1004                 fdt_nop_node(initial_boot_params, led);
1005 end_led:
1006                 ;
1007         }
1008
1009         /* OHCI/UHCI USB */
1010         alias_prop = fdt_getprop(initial_boot_params, aliases,
1011                                  "uctl", NULL);
1012         if (alias_prop) {
1013                 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1014
1015                 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1016                                   octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1017                         pr_debug("Deleting uctl\n");
1018                         fdt_nop_node(initial_boot_params, uctl);
1019                         fdt_nop_property(initial_boot_params, aliases, "uctl");
1020                 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1021                            octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1022                         /* Missing "refclk-type" defaults to crystal. */
1023                         fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1024                 }
1025         }
1026
1027         /* DWC2 USB */
1028         alias_prop = fdt_getprop(initial_boot_params, aliases,
1029                                  "usbn", NULL);
1030         if (alias_prop) {
1031                 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1032
1033                 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1034                                   !octeon_has_feature(OCTEON_FEATURE_USB))) {
1035                         pr_debug("Deleting usbn\n");
1036                         fdt_nop_node(initial_boot_params, usbn);
1037                         fdt_nop_property(initial_boot_params, aliases, "usbn");
1038                 } else  {
1039                         __be32 new_f[1];
1040                         enum cvmx_helper_board_usb_clock_types c;
1041                         c = __cvmx_helper_board_usb_get_clock_type();
1042                         switch (c) {
1043                         case USB_CLOCK_TYPE_REF_48:
1044                                 new_f[0] = cpu_to_be32(48000000);
1045                                 fdt_setprop_inplace(initial_boot_params, usbn,
1046                                                     "refclk-frequency",  new_f, sizeof(new_f));
1047                                 /* Fall through ...*/
1048                         case USB_CLOCK_TYPE_REF_12:
1049                                 /* Missing "refclk-type" defaults to external. */
1050                                 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1051                                 break;
1052                         default:
1053                                 break;
1054                         }
1055                 }
1056         }
1057
1058         return 0;
1059 }
1060
1061 static int __init octeon_publish_devices(void)
1062 {
1063         return of_platform_bus_probe(NULL, octeon_ids, NULL);
1064 }
1065 arch_initcall(octeon_publish_devices);
1066
1067 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
1068 MODULE_LICENSE("GPL");
1069 MODULE_DESCRIPTION("Platform driver for Octeon SOC");