arch/mips/include/asm/io.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf GmbH
   7  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
  10  *      Author: Maciej W. Rozycki <macro@mips.com>
  11  */
  12 #ifndef _ASM_IO_H
  13 #define _ASM_IO_H
  14
  15 #include <linux/compiler.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/irqflags.h>
  19
  20 #include <asm/addrspace.h>
  21 #include <asm/bug.h>
  22 #include <asm/byteorder.h>
  23 #include <asm/cpu.h>
  24 #include <asm/cpu-features.h>
  25 #include <asm-generic/iomap.h>
  26 #include <asm/page.h>
  27 #include <asm/pgtable-bits.h>
  28 #include <asm/processor.h>
  29 #include <asm/string.h>
  30
  31 #include <ioremap.h>
  32 #include <mangle-port.h>
  33
  34 /*
  35  * Slowdown I/O port space accesses for antique hardware.
  36  */
  37 #undef CONF_SLOWDOWN_IO
  38
  39 /*
  40  * Raw operations are never swapped in software.  OTOH values that raw
  41  * operations are working on may or may not have been swapped by the bus
  42  * hardware.  An example use would be for flash memory that's used for
  43  * execute in place.
  44  */
  45 # define __raw_ioswabb(a, x)    (x)
  46 # define __raw_ioswabw(a, x)    (x)
  47 # define __raw_ioswabl(a, x)    (x)
  48 # define __raw_ioswabq(a, x)    (x)
  49 # define ____raw_ioswabq(a, x)  (x)
  50
  51 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
  52
  53 #define IO_SPACE_LIMIT 0xffff
  54
  55 /*
  56  * On MIPS I/O ports are memory mapped, so we access them using normal
  57  * load/store instructions. mips_io_port_base is the virtual address to
  58  * which all ports are being mapped.  For sake of efficiency some code
  59  * assumes that this is an address that can be loaded with a single lui
  60  * instruction, so the lower 16 bits must be zero.  Should be true on
  61  * on any sane architecture; generic code does not use this assumption.
  62  */
  63 extern unsigned long mips_io_port_base;
  64
  65 static inline void set_io_port_base(unsigned long base)
  66 {
  67         mips_io_port_base = base;
  68 }
  69
  70 /*
  71  * Thanks to James van Artsdalen for a better timing-fix than
  72  * the two short jumps: using outb's to a nonexistent port seems
  73  * to guarantee better timings even on fast machines.
  74  *
  75  * On the other hand, I'd like to be sure of a non-existent port:
  76  * I feel a bit unsafe about using 0x80 (should be safe, though)
  77  *
  78  *              Linus
  79  *
  80  */
  81
  82 #define __SLOW_DOWN_IO \
  83         __asm__ __volatile__( \
  84                 "sb\t$0,0x80(%0)" \
  85                 : : "r" (mips_io_port_base));
  86
  87 #ifdef CONF_SLOWDOWN_IO
  88 #ifdef REALLY_SLOW_IO
  89 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
  90 #else
  91 #define SLOW_DOWN_IO __SLOW_DOWN_IO
  92 #endif
  93 #else
  94 #define SLOW_DOWN_IO
  95 #endif
  96
  97 /*
  98  *     virt_to_phys    -       map virtual addresses to physical
  99  *     @address: address to remap
 100  *
 101  *     The returned physical address is the physical (CPU) mapping for
 102  *     the memory address given. It is only valid to use this function on
 103  *     addresses directly mapped or allocated via kmalloc.
 104  *
 105  *     This function does not give bus mappings for DMA transfers. In
 106  *     almost all conceivable cases a device driver should not be using
 107  *     this function
 108  */
 109 static inline unsigned long virt_to_phys(volatile const void *address)
 110 {
 111         return __pa(address);
 112 }
 113
 114 /*
 115  *     phys_to_virt    -       map physical address to virtual
 116  *     @address: address to remap
 117  *
 118  *     The returned virtual address is a current CPU mapping for
 119  *     the memory address given. It is only valid to use this function on
 120  *     addresses that have a kernel mapping
 121  *
 122  *     This function does not handle bus mappings for DMA transfers. In
 123  *     almost all conceivable cases a device driver should not be using
 124  *     this function
 125  */
 126 static inline void * phys_to_virt(unsigned long address)
 127 {
 128         return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
 129 }
 130
 131 /*
 132  * ISA I/O bus memory addresses are 1:1 with the physical address.
 133  */
 134 static inline unsigned long isa_virt_to_bus(volatile void *address)
 135 {
 136         return virt_to_phys(address);
 137 }
 138
 139 static inline void *isa_bus_to_virt(unsigned long address)
 140 {
 141         return phys_to_virt(address);
 142 }
 143
 144 #define isa_page_to_bus page_to_phys
 145
 146 /*
 147  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 148  * are forbidden in portable PCI drivers.
 149  *
 150  * Allow them for x86 for legacy drivers, though.
 151  */
 152 #define virt_to_bus virt_to_phys
 153 #define bus_to_virt phys_to_virt
 154
 155 /*
 156  * Change "struct page" to physical address.
 157  */
 158 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 159
 160 extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
 161 extern void __iounmap(const volatile void __iomem *addr);
 162
 163 #ifndef CONFIG_PCI
 164 struct pci_dev;
 165 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
 166 #endif
 167
 168 static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
 169         unsigned long flags)
 170 {
 171         void __iomem *addr = plat_ioremap(offset, size, flags);
 172
 173         if (addr)
 174                 return addr;
 175
 176 #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
 177
 178         if (cpu_has_64bit_addresses) {
 179                 u64 base = UNCAC_BASE;
 180
 181                 /*
 182                  * R10000 supports a 2 bit uncached attribute therefore
 183                  * UNCAC_BASE may not equal IO_BASE.
 184                  */
 185                 if (flags == _CACHE_UNCACHED)
 186                         base = (u64) IO_BASE;
 187                 return (void __iomem *) (unsigned long) (base + offset);
 188         } else if (__builtin_constant_p(offset) &&
 189                    __builtin_constant_p(size) && __builtin_constant_p(flags)) {
 190                 phys_addr_t phys_addr, last_addr;
 191
 192                 phys_addr = fixup_bigphys_addr(offset, size);
 193
 194                 /* Don't allow wraparound or zero size. */
 195                 last_addr = phys_addr + size - 1;
 196                 if (!size || last_addr < phys_addr)
 197                         return NULL;
 198
 199                 /*
 200                  * Map uncached objects in the low 512MB of address
 201                  * space using KSEG1.
 202                  */
 203                 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
 204                     flags == _CACHE_UNCACHED)
 205                         return (void __iomem *)
 206                                 (unsigned long)CKSEG1ADDR(phys_addr);
 207         }
 208
 209         return __ioremap(offset, size, flags);
 210
 211 #undef __IS_LOW512
 212 }
 213
 214 /*
 215  * ioremap     -   map bus memory into CPU space
 216  * @offset:    bus address of the memory
 217  * @size:      size of the resource to map
 218  *
 219  * ioremap performs a platform specific sequence of operations to
 220  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 221  * writew/writel functions and the other mmio helpers. The returned
 222  * address is not guaranteed to be usable directly as a virtual
 223  * address.
 224  */
 225 #define ioremap(offset, size)                                           \
 226         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 227
 228 /*
 229  * ioremap_nocache     -   map bus memory into CPU space
 230  * @offset:    bus address of the memory
 231  * @size:      size of the resource to map
 232  *
 233  * ioremap_nocache performs a platform specific sequence of operations to
 234  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 235  * writew/writel functions and the other mmio helpers. The returned
 236  * address is not guaranteed to be usable directly as a virtual
 237  * address.
 238  *
 239  * This version of ioremap ensures that the memory is marked uncachable
 240  * on the CPU as well as honouring existing caching rules from things like
 241  * the PCI bus. Note that there are other caches and buffers on many
 242  * busses. In particular driver authors should read up on PCI writes
 243  *
 244  * It's useful if some control registers are in such an area and
 245  * write combining or read caching is not desirable:
 246  */
 247 #define ioremap_nocache(offset, size)                                   \
 248         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 249 #define ioremap_uc ioremap_nocache
 250
 251 /*
 252  * ioremap_cachable -   map bus memory into CPU space
 253  * @offset:         bus address of the memory
 254  * @size:           size of the resource to map
 255  *
 256  * ioremap_nocache performs a platform specific sequence of operations to
 257  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 258  * writew/writel functions and the other mmio helpers. The returned
 259  * address is not guaranteed to be usable directly as a virtual
 260  * address.
 261  *
 262  * This version of ioremap ensures that the memory is marked cachable by
 263  * the CPU.  Also enables full write-combining.  Useful for some
 264  * memory-like regions on I/O busses.
 265  */
 266 #define ioremap_cachable(offset, size)                                  \
 267         __ioremap_mode((offset), (size), _page_cachable_default)
 268
 269 /*
 270  * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
 271  * requests a cachable mapping, ioremap_uncached_accelerated requests a
 272  * mapping using the uncached accelerated mode which isn't supported on
 273  * all processors.
 274  */
 275 #define ioremap_cacheable_cow(offset, size)                             \
 276         __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
 277 #define ioremap_uncached_accelerated(offset, size)                      \
 278         __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
 279
 280 static inline void iounmap(const volatile void __iomem *addr)
 281 {
 282         if (plat_iounmap(addr))
 283                 return;
 284
 285 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
 286
 287         if (cpu_has_64bit_addresses ||
 288             (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
 289                 return;
 290
 291         __iounmap(addr);
 292
 293 #undef __IS_KSEG1
 294 }
 295
 296 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 297 #define war_octeon_io_reorder_wmb()             wmb()
 298 #else
 299 #define war_octeon_io_reorder_wmb()             do { } while (0)
 300 #endif
 301
 302 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
 303                                                                         \
 304 static inline void pfx##write##bwlq(type val,                           \
 305                                     volatile void __iomem *mem)         \
 306 {                                                                       \
 307         volatile type *__mem;                                           \
 308         type __val;                                                     \
 309                                                                         \
 310         war_octeon_io_reorder_wmb();                                    \
 311                                                                         \
 312         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 313                                                                         \
 314         __val = pfx##ioswab##bwlq(__mem, val);                          \
 315                                                                         \
 316         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 317                 *__mem = __val;                                         \
 318         else if (cpu_has_64bits) {                                      \
 319                 unsigned long __flags;                                  \
 320                 type __tmp;                                             \
 321                                                                         \
 322                 if (irq)                                                \
 323                         local_irq_save(__flags);                        \
 324                 __asm__ __volatile__(                                   \
 325                         ".set   arch=r4000"     "\t\t# __writeq""\n\t"  \
 326                         "dsll32 %L0, %L0, 0"                    "\n\t"  \
 327                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
 328                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
 329                         "or     %L0, %L0, %M0"                  "\n\t"  \
 330                         "sd     %L0, %2"                        "\n\t"  \
 331                         ".set   mips0"                          "\n"    \
 332                         : "=r" (__tmp)                                  \
 333                         : "0" (__val), "m" (*__mem));                   \
 334                 if (irq)                                                \
 335                         local_irq_restore(__flags);                     \
 336         } else                                                          \
 337                 BUG();                                                  \
 338 }                                                                       \
 339                                                                         \
 340 static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
 341 {                                                                       \
 342         volatile type *__mem;                                           \
 343         type __val;                                                     \
 344                                                                         \
 345         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 346                                                                         \
 347         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 348                 __val = *__mem;                                         \
 349         else if (cpu_has_64bits) {                                      \
 350                 unsigned long __flags;                                  \
 351                                                                         \
 352                 if (irq)                                                \
 353                         local_irq_save(__flags);                        \
 354                 __asm__ __volatile__(                                   \
 355                         ".set   arch=r4000"     "\t\t# __readq" "\n\t"  \
 356                         "ld     %L0, %1"                        "\n\t"  \
 357                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
 358                         "sll    %L0, %L0, 0"                    "\n\t"  \
 359                         ".set   mips0"                          "\n"    \
 360                         : "=r" (__val)                                  \
 361                         : "m" (*__mem));                                \
 362                 if (irq)                                                \
 363                         local_irq_restore(__flags);                     \
 364         } else {                                                        \
 365                 __val = 0;                                              \
 366                 BUG();                                                  \
 367         }                                                               \
 368                                                                         \
 369         return pfx##ioswab##bwlq(__mem, __val);                         \
 370 }
 371
 372 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
 373                                                                         \
 374 static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
 375 {                                                                       \
 376         volatile type *__addr;                                          \
 377         type __val;                                                     \
 378                                                                         \
 379         war_octeon_io_reorder_wmb();                                    \
 380                                                                         \
 381         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 382                                                                         \
 383         __val = pfx##ioswab##bwlq(__addr, val);                         \
 384                                                                         \
 385         /* Really, we want this to be atomic */                         \
 386         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 387                                                                         \
 388         *__addr = __val;                                                \
 389         slow;                                                           \
 390 }                                                                       \
 391                                                                         \
 392 static inline type pfx##in##bwlq##p(unsigned long port)                 \
 393 {                                                                       \
 394         volatile type *__addr;                                          \
 395         type __val;                                                     \
 396                                                                         \
 397         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 398                                                                         \
 399         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 400                                                                         \
 401         __val = *__addr;                                                \
 402         slow;                                                           \
 403                                                                         \
 404         /* prevent prefetching of coherent DMA data prematurely */      \
 405         rmb();                                                          \
 406         return pfx##ioswab##bwlq(__addr, __val);                        \
 407 }
 408
 409 #define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
 410                                                                         \
 411 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
 412
 413 #define BUILDIO_MEM(bwlq, type)                                         \
 414                                                                         \
 415 __BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
 416 __BUILD_MEMORY_PFX(, bwlq, type)                                        \
 417 __BUILD_MEMORY_PFX(__mem_, bwlq, type)                                  \
 418
 419 BUILDIO_MEM(b, u8)
 420 BUILDIO_MEM(w, u16)
 421 BUILDIO_MEM(l, u32)
 422 BUILDIO_MEM(q, u64)
 423
 424 #define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
 425         __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
 426         __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
 427
 428 #define BUILDIO_IOPORT(bwlq, type)                                      \
 429         __BUILD_IOPORT_PFX(, bwlq, type)                                \
 430         __BUILD_IOPORT_PFX(__mem_, bwlq, type)
 431
 432 BUILDIO_IOPORT(b, u8)
 433 BUILDIO_IOPORT(w, u16)
 434 BUILDIO_IOPORT(l, u32)
 435 #ifdef CONFIG_64BIT
 436 BUILDIO_IOPORT(q, u64)
 437 #endif
 438
 439 #define __BUILDIO(bwlq, type)                                           \
 440                                                                         \
 441 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
 442
 443 __BUILDIO(q, u64)
 444
 445 #define readb_relaxed                   readb
 446 #define readw_relaxed                   readw
 447 #define readl_relaxed                   readl
 448 #define readq_relaxed                   readq
 449
 450 #define writeb_relaxed                  writeb
 451 #define writew_relaxed                  writew
 452 #define writel_relaxed                  writel
 453 #define writeq_relaxed                  writeq
 454
 455 #define readb_be(addr)                                                  \
 456         __raw_readb((__force unsigned *)(addr))
 457 #define readw_be(addr)                                                  \
 458         be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
 459 #define readl_be(addr)                                                  \
 460         be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
 461 #define readq_be(addr)                                                  \
 462         be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
 463
 464 #define writeb_be(val, addr)                                            \
 465         __raw_writeb((val), (__force unsigned *)(addr))
 466 #define writew_be(val, addr)                                            \
 467         __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
 468 #define writel_be(val, addr)                                            \
 469         __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
 470 #define writeq_be(val, addr)                                            \
 471         __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
 472
 473 /*
 474  * Some code tests for these symbols
 475  */
 476 #define readq                           readq
 477 #define writeq                          writeq
 478
 479 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
 480                                                                         \
 481 static inline void writes##bwlq(volatile void __iomem *mem,             \
 482                                 const void *addr, unsigned int count)   \
 483 {                                                                       \
 484         const volatile type *__addr = addr;                             \
 485                                                                         \
 486         while (count--) {                                               \
 487                 __mem_write##bwlq(*__addr, mem);                        \
 488                 __addr++;                                               \
 489         }                                                               \
 490 }                                                                       \
 491                                                                         \
 492 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
 493                                unsigned int count)                      \
 494 {                                                                       \
 495         volatile type *__addr = addr;                                   \
 496                                                                         \
 497         while (count--) {                                               \
 498                 *__addr = __mem_read##bwlq(mem);                        \
 499                 __addr++;                                               \
 500         }                                                               \
 501 }
 502
 503 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
 504                                                                         \
 505 static inline void outs##bwlq(unsigned long port, const void *addr,     \
 506                               unsigned int count)                       \
 507 {                                                                       \
 508         const volatile type *__addr = addr;                             \
 509                                                                         \
 510         while (count--) {                                               \
 511                 __mem_out##bwlq(*__addr, port);                         \
 512                 __addr++;                                               \
 513         }                                                               \
 514 }                                                                       \
 515                                                                         \
 516 static inline void ins##bwlq(unsigned long port, void *addr,            \
 517                              unsigned int count)                        \
 518 {                                                                       \
 519         volatile type *__addr = addr;                                   \
 520                                                                         \
 521         while (count--) {                                               \
 522                 *__addr = __mem_in##bwlq(port);                         \
 523                 __addr++;                                               \
 524         }                                                               \
 525 }
 526
 527 #define BUILDSTRING(bwlq, type)                                         \
 528                                                                         \
 529 __BUILD_MEMORY_STRING(bwlq, type)                                       \
 530 __BUILD_IOPORT_STRING(bwlq, type)
 531
 532 BUILDSTRING(b, u8)
 533 BUILDSTRING(w, u16)
 534 BUILDSTRING(l, u32)
 535 #ifdef CONFIG_64BIT
 536 BUILDSTRING(q, u64)
 537 #endif
 538
 539
 540 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 541 #define mmiowb() wmb()
 542 #else
 543 /* Depends on MIPS II instruction set */
 544 #define mmiowb() asm volatile ("sync" ::: "memory")
 545 #endif
 546
 547 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 548 {
 549         memset((void __force *) addr, val, count);
 550 }
 551 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
 552 {
 553         memcpy(dst, (void __force *) src, count);
 554 }
 555 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 556 {
 557         memcpy((void __force *) dst, src, count);
 558 }
 559
 560 /*
 561  * The caches on some architectures aren't dma-coherent and have need to
 562  * handle this in software.  There are three types of operations that
 563  * can be applied to dma buffers.
 564  *
 565  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 566  *    writing the content of the caches back to memory, if necessary.
 567  *    The function also invalidates the affected part of the caches as
 568  *    necessary before DMA transfers from outside to memory.
 569  *  - dma_cache_wback(start, size) makes caches and coherent by
 570  *    writing the content of the caches back to memory, if necessary.
 571  *    The function also invalidates the affected part of the caches as
 572  *    necessary before DMA transfers from outside to memory.
 573  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 574  *    caches.  Dirty lines of the caches may be written back or simply
 575  *    be discarded.  This operation is necessary before dma operations
 576  *    to the memory.
 577  *
 578  * This API used to be exported; it now is for arch code internal use only.
 579  */
 580 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
 581
 582 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 583 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 584 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 585
 586 #define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start, size)
 587 #define dma_cache_wback(start, size)            _dma_cache_wback(start, size)
 588 #define dma_cache_inv(start, size)              _dma_cache_inv(start, size)
 589
 590 #else /* Sane hardware */
 591
 592 #define dma_cache_wback_inv(start,size) \
 593         do { (void) (start); (void) (size); } while (0)
 594 #define dma_cache_wback(start,size)     \
 595         do { (void) (start); (void) (size); } while (0)
 596 #define dma_cache_inv(start,size)       \
 597         do { (void) (start); (void) (size); } while (0)
 598
 599 #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
 600
 601 /*
 602  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 603  * Avoid interrupt mucking, just adjust the address for 4-byte access.
 604  * Assume the addresses are 8-byte aligned.
 605  */
 606 #ifdef __MIPSEB__
 607 #define __CSR_32_ADJUST 4
 608 #else
 609 #define __CSR_32_ADJUST 0
 610 #endif
 611
 612 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
 613 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 614
 615 /*
 616  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 617  * access
 618  */
 619 #define xlate_dev_mem_ptr(p)    __va(p)
 620
 621 /*
 622  * Convert a virtual cached pointer to an uncached pointer
 623  */
 624 #define xlate_dev_kmem_ptr(p)   p
 625
 626 #endif /* _ASM_IO_H */