arch/mips/include/asm/io.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf GmbH
   7  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
  10  *      Author: Maciej W. Rozycki <macro@mips.com>
  11  */
  12 #ifndef _ASM_IO_H
  13 #define _ASM_IO_H
  14
  15 #define ARCH_HAS_IOREMAP_WC
  16
  17 #include <linux/compiler.h>
  18 #include <linux/kernel.h>
  19 #include <linux/types.h>
  20 #include <linux/irqflags.h>
  21
  22 #include <asm/addrspace.h>
  23 #include <asm/bug.h>
  24 #include <asm/byteorder.h>
  25 #include <asm/cpu.h>
  26 #include <asm/cpu-features.h>
  27 #include <asm-generic/iomap.h>
  28 #include <asm/page.h>
  29 #include <asm/pgtable-bits.h>
  30 #include <asm/processor.h>
  31 #include <asm/string.h>
  32
  33 #include <ioremap.h>
  34 #include <mangle-port.h>
  35
  36 /*
  37  * Slowdown I/O port space accesses for antique hardware.
  38  */
  39 #undef CONF_SLOWDOWN_IO
  40
  41 /*
  42  * Raw operations are never swapped in software.  OTOH values that raw
  43  * operations are working on may or may not have been swapped by the bus
  44  * hardware.  An example use would be for flash memory that's used for
  45  * execute in place.
  46  */
  47 # define __raw_ioswabb(a, x)    (x)
  48 # define __raw_ioswabw(a, x)    (x)
  49 # define __raw_ioswabl(a, x)    (x)
  50 # define __raw_ioswabq(a, x)    (x)
  51 # define ____raw_ioswabq(a, x)  (x)
  52
  53 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
  54
  55 #define IO_SPACE_LIMIT 0xffff
  56
  57 /*
  58  * On MIPS I/O ports are memory mapped, so we access them using normal
  59  * load/store instructions. mips_io_port_base is the virtual address to
  60  * which all ports are being mapped.  For sake of efficiency some code
  61  * assumes that this is an address that can be loaded with a single lui
  62  * instruction, so the lower 16 bits must be zero.  Should be true on
  63  * on any sane architecture; generic code does not use this assumption.
  64  */
  65 extern unsigned long mips_io_port_base;
  66
  67 static inline void set_io_port_base(unsigned long base)
  68 {
  69         mips_io_port_base = base;
  70 }
  71
  72 /*
  73  * Thanks to James van Artsdalen for a better timing-fix than
  74  * the two short jumps: using outb's to a nonexistent port seems
  75  * to guarantee better timings even on fast machines.
  76  *
  77  * On the other hand, I'd like to be sure of a non-existent port:
  78  * I feel a bit unsafe about using 0x80 (should be safe, though)
  79  *
  80  *              Linus
  81  *
  82  */
  83
  84 #define __SLOW_DOWN_IO \
  85         __asm__ __volatile__( \
  86                 "sb\t$0,0x80(%0)" \
  87                 : : "r" (mips_io_port_base));
  88
  89 #ifdef CONF_SLOWDOWN_IO
  90 #ifdef REALLY_SLOW_IO
  91 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
  92 #else
  93 #define SLOW_DOWN_IO __SLOW_DOWN_IO
  94 #endif
  95 #else
  96 #define SLOW_DOWN_IO
  97 #endif
  98
  99 /*
 100  *     virt_to_phys    -       map virtual addresses to physical
 101  *     @address: address to remap
 102  *
 103  *     The returned physical address is the physical (CPU) mapping for
 104  *     the memory address given. It is only valid to use this function on
 105  *     addresses directly mapped or allocated via kmalloc.
 106  *
 107  *     This function does not give bus mappings for DMA transfers. In
 108  *     almost all conceivable cases a device driver should not be using
 109  *     this function
 110  */
 111 static inline unsigned long virt_to_phys(volatile const void *address)
 112 {
 113         return __pa(address);
 114 }
 115
 116 /*
 117  *     phys_to_virt    -       map physical address to virtual
 118  *     @address: address to remap
 119  *
 120  *     The returned virtual address is a current CPU mapping for
 121  *     the memory address given. It is only valid to use this function on
 122  *     addresses that have a kernel mapping
 123  *
 124  *     This function does not handle bus mappings for DMA transfers. In
 125  *     almost all conceivable cases a device driver should not be using
 126  *     this function
 127  */
 128 static inline void * phys_to_virt(unsigned long address)
 129 {
 130         return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
 131 }
 132
 133 /*
 134  * ISA I/O bus memory addresses are 1:1 with the physical address.
 135  */
 136 static inline unsigned long isa_virt_to_bus(volatile void *address)
 137 {
 138         return virt_to_phys(address);
 139 }
 140
 141 static inline void *isa_bus_to_virt(unsigned long address)
 142 {
 143         return phys_to_virt(address);
 144 }
 145
 146 #define isa_page_to_bus page_to_phys
 147
 148 /*
 149  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 150  * are forbidden in portable PCI drivers.
 151  *
 152  * Allow them for x86 for legacy drivers, though.
 153  */
 154 #define virt_to_bus virt_to_phys
 155 #define bus_to_virt phys_to_virt
 156
 157 /*
 158  * Change "struct page" to physical address.
 159  */
 160 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 161
 162 extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
 163 extern void __iounmap(const volatile void __iomem *addr);
 164
 165 #ifndef CONFIG_PCI
 166 struct pci_dev;
 167 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
 168 #endif
 169
 170 static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
 171         unsigned long flags)
 172 {
 173         void __iomem *addr = plat_ioremap(offset, size, flags);
 174
 175         if (addr)
 176                 return addr;
 177
 178 #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
 179
 180         if (cpu_has_64bit_addresses) {
 181                 u64 base = UNCAC_BASE;
 182
 183                 /*
 184                  * R10000 supports a 2 bit uncached attribute therefore
 185                  * UNCAC_BASE may not equal IO_BASE.
 186                  */
 187                 if (flags == _CACHE_UNCACHED)
 188                         base = (u64) IO_BASE;
 189                 return (void __iomem *) (unsigned long) (base + offset);
 190         } else if (__builtin_constant_p(offset) &&
 191                    __builtin_constant_p(size) && __builtin_constant_p(flags)) {
 192                 phys_addr_t phys_addr, last_addr;
 193
 194                 phys_addr = fixup_bigphys_addr(offset, size);
 195
 196                 /* Don't allow wraparound or zero size. */
 197                 last_addr = phys_addr + size - 1;
 198                 if (!size || last_addr < phys_addr)
 199                         return NULL;
 200
 201                 /*
 202                  * Map uncached objects in the low 512MB of address
 203                  * space using KSEG1.
 204                  */
 205                 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
 206                     flags == _CACHE_UNCACHED)
 207                         return (void __iomem *)
 208                                 (unsigned long)CKSEG1ADDR(phys_addr);
 209         }
 210
 211         return __ioremap(offset, size, flags);
 212
 213 #undef __IS_LOW512
 214 }
 215
 216 /*
 217  * ioremap     -   map bus memory into CPU space
 218  * @offset:    bus address of the memory
 219  * @size:      size of the resource to map
 220  *
 221  * ioremap performs a platform specific sequence of operations to
 222  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 223  * writew/writel functions and the other mmio helpers. The returned
 224  * address is not guaranteed to be usable directly as a virtual
 225  * address.
 226  */
 227 #define ioremap(offset, size)                                           \
 228         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 229
 230 /*
 231  * ioremap_nocache     -   map bus memory into CPU space
 232  * @offset:    bus address of the memory
 233  * @size:      size of the resource to map
 234  *
 235  * ioremap_nocache performs a platform specific sequence of operations to
 236  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 237  * writew/writel functions and the other mmio helpers. The returned
 238  * address is not guaranteed to be usable directly as a virtual
 239  * address.
 240  *
 241  * This version of ioremap ensures that the memory is marked uncachable
 242  * on the CPU as well as honouring existing caching rules from things like
 243  * the PCI bus. Note that there are other caches and buffers on many
 244  * busses. In particular driver authors should read up on PCI writes
 245  *
 246  * It's useful if some control registers are in such an area and
 247  * write combining or read caching is not desirable:
 248  */
 249 #define ioremap_nocache(offset, size)                                   \
 250         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 251 #define ioremap_uc ioremap_nocache
 252
 253 /*
 254  * ioremap_cachable -   map bus memory into CPU space
 255  * @offset:         bus address of the memory
 256  * @size:           size of the resource to map
 257  *
 258  * ioremap_nocache performs a platform specific sequence of operations to
 259  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 260  * writew/writel functions and the other mmio helpers. The returned
 261  * address is not guaranteed to be usable directly as a virtual
 262  * address.
 263  *
 264  * This version of ioremap ensures that the memory is marked cachable by
 265  * the CPU.  Also enables full write-combining.  Useful for some
 266  * memory-like regions on I/O busses.
 267  */
 268 #define ioremap_cachable(offset, size)                                  \
 269         __ioremap_mode((offset), (size), _page_cachable_default)
 270 #define ioremap_cache ioremap_cachable
 271
 272 /*
 273  * ioremap_wc     -   map bus memory into CPU space
 274  * @offset:    bus address of the memory
 275  * @size:      size of the resource to map
 276  *
 277  * ioremap_wc performs a platform specific sequence of operations to
 278  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 279  * writew/writel functions and the other mmio helpers. The returned
 280  * address is not guaranteed to be usable directly as a virtual
 281  * address.
 282  *
 283  * This version of ioremap ensures that the memory is marked uncachable
 284  * but accelerated by means of write-combining feature. It is specifically
 285  * useful for PCIe prefetchable windows, which may vastly improve a
 286  * communications performance. If it was determined on boot stage, what
 287  * CPU CCA doesn't support UCA, the method shall fall-back to the
 288  * _CACHE_UNCACHED option (see cpu_probe() method).
 289  */
 290 #define ioremap_wc(offset, size)                                        \
 291         __ioremap_mode((offset), (size), boot_cpu_data.writecombine)
 292
 293 static inline void iounmap(const volatile void __iomem *addr)
 294 {
 295         if (plat_iounmap(addr))
 296                 return;
 297
 298 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
 299
 300         if (cpu_has_64bit_addresses ||
 301             (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
 302                 return;
 303
 304         __iounmap(addr);
 305
 306 #undef __IS_KSEG1
 307 }
 308
 309 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
 310 #define war_io_reorder_wmb()            wmb()
 311 #else
 312 #define war_io_reorder_wmb()            barrier()
 313 #endif
 314
 315 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
 316                                                                         \
 317 static inline void pfx##write##bwlq(type val,                           \
 318                                     volatile void __iomem *mem)         \
 319 {                                                                       \
 320         volatile type *__mem;                                           \
 321         type __val;                                                     \
 322                                                                         \
 323         war_io_reorder_wmb();                                   \
 324                                                                         \
 325         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 326                                                                         \
 327         __val = pfx##ioswab##bwlq(__mem, val);                          \
 328                                                                         \
 329         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 330                 *__mem = __val;                                         \
 331         else if (cpu_has_64bits) {                                      \
 332                 unsigned long __flags;                                  \
 333                 type __tmp;                                             \
 334                                                                         \
 335                 if (irq)                                                \
 336                         local_irq_save(__flags);                        \
 337                 __asm__ __volatile__(                                   \
 338                         ".set   arch=r4000"     "\t\t# __writeq""\n\t"  \
 339                         "dsll32 %L0, %L0, 0"                    "\n\t"  \
 340                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
 341                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
 342                         "or     %L0, %L0, %M0"                  "\n\t"  \
 343                         "sd     %L0, %2"                        "\n\t"  \
 344                         ".set   mips0"                          "\n"    \
 345                         : "=r" (__tmp)                                  \
 346                         : "0" (__val), "m" (*__mem));                   \
 347                 if (irq)                                                \
 348                         local_irq_restore(__flags);                     \
 349         } else                                                          \
 350                 BUG();                                                  \
 351 }                                                                       \
 352                                                                         \
 353 static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
 354 {                                                                       \
 355         volatile type *__mem;                                           \
 356         type __val;                                                     \
 357                                                                         \
 358         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 359                                                                         \
 360         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 361                 __val = *__mem;                                         \
 362         else if (cpu_has_64bits) {                                      \
 363                 unsigned long __flags;                                  \
 364                                                                         \
 365                 if (irq)                                                \
 366                         local_irq_save(__flags);                        \
 367                 __asm__ __volatile__(                                   \
 368                         ".set   arch=r4000"     "\t\t# __readq" "\n\t"  \
 369                         "ld     %L0, %1"                        "\n\t"  \
 370                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
 371                         "sll    %L0, %L0, 0"                    "\n\t"  \
 372                         ".set   mips0"                          "\n"    \
 373                         : "=r" (__val)                                  \
 374                         : "m" (*__mem));                                \
 375                 if (irq)                                                \
 376                         local_irq_restore(__flags);                     \
 377         } else {                                                        \
 378                 __val = 0;                                              \
 379                 BUG();                                                  \
 380         }                                                               \
 381                                                                         \
 382         /* prevent prefetching of coherent DMA data prematurely */      \
 383         rmb();                                                          \
 384         return pfx##ioswab##bwlq(__mem, __val);                         \
 385 }
 386
 387 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
 388                                                                         \
 389 static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
 390 {                                                                       \
 391         volatile type *__addr;                                          \
 392         type __val;                                                     \
 393                                                                         \
 394         war_io_reorder_wmb();                                   \
 395                                                                         \
 396         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 397                                                                         \
 398         __val = pfx##ioswab##bwlq(__addr, val);                         \
 399                                                                         \
 400         /* Really, we want this to be atomic */                         \
 401         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 402                                                                         \
 403         *__addr = __val;                                                \
 404         slow;                                                           \
 405 }                                                                       \
 406                                                                         \
 407 static inline type pfx##in##bwlq##p(unsigned long port)                 \
 408 {                                                                       \
 409         volatile type *__addr;                                          \
 410         type __val;                                                     \
 411                                                                         \
 412         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 413                                                                         \
 414         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 415                                                                         \
 416         __val = *__addr;                                                \
 417         slow;                                                           \
 418                                                                         \
 419         /* prevent prefetching of coherent DMA data prematurely */      \
 420         rmb();                                                          \
 421         return pfx##ioswab##bwlq(__addr, __val);                        \
 422 }
 423
 424 #define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
 425                                                                         \
 426 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
 427
 428 #define BUILDIO_MEM(bwlq, type)                                         \
 429                                                                         \
 430 __BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
 431 __BUILD_MEMORY_PFX(, bwlq, type)                                        \
 432 __BUILD_MEMORY_PFX(__mem_, bwlq, type)                                  \
 433
 434 BUILDIO_MEM(b, u8)
 435 BUILDIO_MEM(w, u16)
 436 BUILDIO_MEM(l, u32)
 437 BUILDIO_MEM(q, u64)
 438
 439 #define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
 440         __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
 441         __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
 442
 443 #define BUILDIO_IOPORT(bwlq, type)                                      \
 444         __BUILD_IOPORT_PFX(, bwlq, type)                                \
 445         __BUILD_IOPORT_PFX(__mem_, bwlq, type)
 446
 447 BUILDIO_IOPORT(b, u8)
 448 BUILDIO_IOPORT(w, u16)
 449 BUILDIO_IOPORT(l, u32)
 450 #ifdef CONFIG_64BIT
 451 BUILDIO_IOPORT(q, u64)
 452 #endif
 453
 454 #define __BUILDIO(bwlq, type)                                           \
 455                                                                         \
 456 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
 457
 458 __BUILDIO(q, u64)
 459
 460 #define readb_relaxed                   readb
 461 #define readw_relaxed                   readw
 462 #define readl_relaxed                   readl
 463 #define readq_relaxed                   readq
 464
 465 #define writeb_relaxed                  writeb
 466 #define writew_relaxed                  writew
 467 #define writel_relaxed                  writel
 468 #define writeq_relaxed                  writeq
 469
 470 #define readb_be(addr)                                                  \
 471         __raw_readb((__force unsigned *)(addr))
 472 #define readw_be(addr)                                                  \
 473         be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
 474 #define readl_be(addr)                                                  \
 475         be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
 476 #define readq_be(addr)                                                  \
 477         be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
 478
 479 #define writeb_be(val, addr)                                            \
 480         __raw_writeb((val), (__force unsigned *)(addr))
 481 #define writew_be(val, addr)                                            \
 482         __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
 483 #define writel_be(val, addr)                                            \
 484         __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
 485 #define writeq_be(val, addr)                                            \
 486         __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
 487
 488 /*
 489  * Some code tests for these symbols
 490  */
 491 #define readq                           readq
 492 #define writeq                          writeq
 493
 494 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
 495                                                                         \
 496 static inline void writes##bwlq(volatile void __iomem *mem,             \
 497                                 const void *addr, unsigned int count)   \
 498 {                                                                       \
 499         const volatile type *__addr = addr;                             \
 500                                                                         \
 501         while (count--) {                                               \
 502                 __mem_write##bwlq(*__addr, mem);                        \
 503                 __addr++;                                               \
 504         }                                                               \
 505 }                                                                       \
 506                                                                         \
 507 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
 508                                unsigned int count)                      \
 509 {                                                                       \
 510         volatile type *__addr = addr;                                   \
 511                                                                         \
 512         while (count--) {                                               \
 513                 *__addr = __mem_read##bwlq(mem);                        \
 514                 __addr++;                                               \
 515         }                                                               \
 516 }
 517
 518 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
 519                                                                         \
 520 static inline void outs##bwlq(unsigned long port, const void *addr,     \
 521                               unsigned int count)                       \
 522 {                                                                       \
 523         const volatile type *__addr = addr;                             \
 524                                                                         \
 525         while (count--) {                                               \
 526                 __mem_out##bwlq(*__addr, port);                         \
 527                 __addr++;                                               \
 528         }                                                               \
 529 }                                                                       \
 530                                                                         \
 531 static inline void ins##bwlq(unsigned long port, void *addr,            \
 532                              unsigned int count)                        \
 533 {                                                                       \
 534         volatile type *__addr = addr;                                   \
 535                                                                         \
 536         while (count--) {                                               \
 537                 *__addr = __mem_in##bwlq(port);                         \
 538                 __addr++;                                               \
 539         }                                                               \
 540 }
 541
 542 #define BUILDSTRING(bwlq, type)                                         \
 543                                                                         \
 544 __BUILD_MEMORY_STRING(bwlq, type)                                       \
 545 __BUILD_IOPORT_STRING(bwlq, type)
 546
 547 BUILDSTRING(b, u8)
 548 BUILDSTRING(w, u16)
 549 BUILDSTRING(l, u32)
 550 #ifdef CONFIG_64BIT
 551 BUILDSTRING(q, u64)
 552 #endif
 553
 554
 555 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 556 #define mmiowb() wmb()
 557 #else
 558 /* Depends on MIPS II instruction set */
 559 #define mmiowb() asm volatile ("sync" ::: "memory")
 560 #endif
 561
 562 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 563 {
 564         memset((void __force *) addr, val, count);
 565 }
 566 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
 567 {
 568         memcpy(dst, (void __force *) src, count);
 569 }
 570 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 571 {
 572         memcpy((void __force *) dst, src, count);
 573 }
 574
 575 /*
 576  * The caches on some architectures aren't dma-coherent and have need to
 577  * handle this in software.  There are three types of operations that
 578  * can be applied to dma buffers.
 579  *
 580  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 581  *    writing the content of the caches back to memory, if necessary.
 582  *    The function also invalidates the affected part of the caches as
 583  *    necessary before DMA transfers from outside to memory.
 584  *  - dma_cache_wback(start, size) makes caches and coherent by
 585  *    writing the content of the caches back to memory, if necessary.
 586  *    The function also invalidates the affected part of the caches as
 587  *    necessary before DMA transfers from outside to memory.
 588  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 589  *    caches.  Dirty lines of the caches may be written back or simply
 590  *    be discarded.  This operation is necessary before dma operations
 591  *    to the memory.
 592  *
 593  * This API used to be exported; it now is for arch code internal use only.
 594  */
 595 #ifdef CONFIG_DMA_NONCOHERENT
 596
 597 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 598 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 599 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 600
 601 #define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start, size)
 602 #define dma_cache_wback(start, size)            _dma_cache_wback(start, size)
 603 #define dma_cache_inv(start, size)              _dma_cache_inv(start, size)
 604
 605 #else /* Sane hardware */
 606
 607 #define dma_cache_wback_inv(start,size) \
 608         do { (void) (start); (void) (size); } while (0)
 609 #define dma_cache_wback(start,size)     \
 610         do { (void) (start); (void) (size); } while (0)
 611 #define dma_cache_inv(start,size)       \
 612         do { (void) (start); (void) (size); } while (0)
 613
 614 #endif /* CONFIG_DMA_NONCOHERENT */
 615
 616 /*
 617  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 618  * Avoid interrupt mucking, just adjust the address for 4-byte access.
 619  * Assume the addresses are 8-byte aligned.
 620  */
 621 #ifdef __MIPSEB__
 622 #define __CSR_32_ADJUST 4
 623 #else
 624 #define __CSR_32_ADJUST 0
 625 #endif
 626
 627 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
 628 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 629
 630 /*
 631  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 632  * access
 633  */
 634 #define xlate_dev_mem_ptr(p)    __va(p)
 635
 636 /*
 637  * Convert a virtual cached pointer to an uncached pointer
 638  */
 639 #define xlate_dev_kmem_ptr(p)   p
 640
 641 void __ioread64_copy(void *to, const void __iomem *from, size_t count);
 642
 643 #endif /* _ASM_IO_H */