arch/mips/include/asm/mach-jz4740/base.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_MACH_JZ4740_BASE_H__
   3 #define __ASM_MACH_JZ4740_BASE_H__
   4
   5 #define JZ4740_CPM_BASE_ADDR    0x10000000
   6 #define JZ4740_INTC_BASE_ADDR   0x10001000
   7 #define JZ4740_WDT_BASE_ADDR    0x10002000
   8 #define JZ4740_TCU_BASE_ADDR    0x10002010
   9 #define JZ4740_RTC_BASE_ADDR    0x10003000
  10 #define JZ4740_GPIO_BASE_ADDR   0x10010000
  11 #define JZ4740_AIC_BASE_ADDR    0x10020000
  12 #define JZ4740_MSC_BASE_ADDR    0x10021000
  13 #define JZ4740_UART0_BASE_ADDR  0x10030000
  14 #define JZ4740_UART1_BASE_ADDR  0x10031000
  15 #define JZ4740_I2C_BASE_ADDR    0x10042000
  16 #define JZ4740_SSI_BASE_ADDR    0x10043000
  17 #define JZ4740_SADC_BASE_ADDR   0x10070000
  18 #define JZ4740_EMC_BASE_ADDR    0x13010000
  19 #define JZ4740_DMAC_BASE_ADDR   0x13020000
  20 #define JZ4740_UHC_BASE_ADDR    0x13030000
  21 #define JZ4740_UDC_BASE_ADDR    0x13040000
  22 #define JZ4740_LCD_BASE_ADDR    0x13050000
  23 #define JZ4740_SLCD_BASE_ADDR   0x13050000
  24 #define JZ4740_CIM_BASE_ADDR    0x13060000
  25 #define JZ4740_IPU_BASE_ADDR    0x13080000
  26
  27 #endif