arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (C) 2003-2018 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_PCSXX_DEFS_H__
  29 #define __CVMX_PCSXX_DEFS_H__
  30
  31 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
  32 {
  33         switch (cvmx_get_octeon_family()) {
  34         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  35         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  36         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  37                 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
  38         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  39         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  40                 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
  41         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  42                 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
  43         }
  44         return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
  45 }
  46
  47 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
  48 {
  49         switch (cvmx_get_octeon_family()) {
  50         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  51         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  52         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  53                 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
  54         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  55         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  56                 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
  57         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  58                 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
  59         }
  60         return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
  61 }
  62
  63 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
  64 {
  65         switch (cvmx_get_octeon_family()) {
  66         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  67         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  68         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  69                 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
  70         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  71         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  72                 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
  73         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  74                 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
  75         }
  76         return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
  77 }
  78
  79 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
  80 {
  81         switch (cvmx_get_octeon_family()) {
  82         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  83         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  84         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  85                 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
  86         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  87         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  88                 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
  89         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  90                 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
  91         }
  92         return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
  93 }
  94
  95 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
  96 {
  97         switch (cvmx_get_octeon_family()) {
  98         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  99         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 100         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 101                 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
 102         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 103         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 104                 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
 105         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 106                 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
 107         }
 108         return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
 109 }
 110
 111 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
 112 {
 113         switch (cvmx_get_octeon_family()) {
 114         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 115         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 116         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 117                 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
 118         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 119         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 120                 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
 121         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 122                 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
 123         }
 124         return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
 125 }
 126
 127 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
 128 {
 129         switch (cvmx_get_octeon_family()) {
 130         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 131         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 132         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 133                 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
 134         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 135         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 136                 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
 137         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 138                 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
 139         }
 140         return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
 141 }
 142
 143 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
 144 {
 145         switch (cvmx_get_octeon_family()) {
 146         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 147         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 148         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 149                 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
 150         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 151         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 152                 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
 153         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 154                 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
 155         }
 156         return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
 157 }
 158
 159 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
 160 {
 161         switch (cvmx_get_octeon_family()) {
 162         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 163         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 164         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 165                 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
 166         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 167         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 168                 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
 169         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 170                 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
 171         }
 172         return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
 173 }
 174
 175 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
 176 {
 177         switch (cvmx_get_octeon_family()) {
 178         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 179         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 180         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 181                 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
 182         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 183         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 184                 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
 185         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 186                 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
 187         }
 188         return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
 189 }
 190
 191 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
 192 {
 193         switch (cvmx_get_octeon_family()) {
 194         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 195         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 196         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 197                 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
 198         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 199         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 200                 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
 201         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 202                 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
 203         }
 204         return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
 205 }
 206
 207 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
 208 {
 209         switch (cvmx_get_octeon_family()) {
 210         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 211         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 212         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 213                 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
 214         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 215         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 216                 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
 217         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 218                 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
 219         }
 220         return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
 221 }
 222
 223 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
 224 {
 225         switch (cvmx_get_octeon_family()) {
 226         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 227         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 228         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 229                 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
 230         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 231         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 232                 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
 233         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 234                 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
 235         }
 236         return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
 237 }
 238
 239 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
 240 {
 241         switch (cvmx_get_octeon_family()) {
 242         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 243         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 244         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 245                 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
 246         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 247         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 248                 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
 249         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 250                 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
 251         }
 252         return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
 253 }
 254
 255 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
 256 {
 257         switch (cvmx_get_octeon_family()) {
 258         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 259         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 260         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 261                 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
 262         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 263         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 264                 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
 265         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 266                 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
 267         }
 268         return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
 269 }
 270
 271 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
 272
 273 union cvmx_pcsxx_10gbx_status_reg {
 274         uint64_t u64;
 275         struct cvmx_pcsxx_10gbx_status_reg_s {
 276 #ifdef __BIG_ENDIAN_BITFIELD
 277                 uint64_t reserved_13_63:51;
 278                 uint64_t alignd:1;
 279                 uint64_t pattst:1;
 280                 uint64_t reserved_4_10:7;
 281                 uint64_t l3sync:1;
 282                 uint64_t l2sync:1;
 283                 uint64_t l1sync:1;
 284                 uint64_t l0sync:1;
 285 #else
 286                 uint64_t l0sync:1;
 287                 uint64_t l1sync:1;
 288                 uint64_t l2sync:1;
 289                 uint64_t l3sync:1;
 290                 uint64_t reserved_4_10:7;
 291                 uint64_t pattst:1;
 292                 uint64_t alignd:1;
 293                 uint64_t reserved_13_63:51;
 294 #endif
 295         } s;
 296         struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
 297         struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
 298         struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
 299         struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
 300         struct cvmx_pcsxx_10gbx_status_reg_s cn61xx;
 301         struct cvmx_pcsxx_10gbx_status_reg_s cn63xx;
 302         struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1;
 303         struct cvmx_pcsxx_10gbx_status_reg_s cn66xx;
 304         struct cvmx_pcsxx_10gbx_status_reg_s cn68xx;
 305         struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1;
 306 };
 307
 308 union cvmx_pcsxx_bist_status_reg {
 309         uint64_t u64;
 310         struct cvmx_pcsxx_bist_status_reg_s {
 311 #ifdef __BIG_ENDIAN_BITFIELD
 312                 uint64_t reserved_1_63:63;
 313                 uint64_t bist_status:1;
 314 #else
 315                 uint64_t bist_status:1;
 316                 uint64_t reserved_1_63:63;
 317 #endif
 318         } s;
 319         struct cvmx_pcsxx_bist_status_reg_s cn52xx;
 320         struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
 321         struct cvmx_pcsxx_bist_status_reg_s cn56xx;
 322         struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
 323         struct cvmx_pcsxx_bist_status_reg_s cn61xx;
 324         struct cvmx_pcsxx_bist_status_reg_s cn63xx;
 325         struct cvmx_pcsxx_bist_status_reg_s cn63xxp1;
 326         struct cvmx_pcsxx_bist_status_reg_s cn66xx;
 327         struct cvmx_pcsxx_bist_status_reg_s cn68xx;
 328         struct cvmx_pcsxx_bist_status_reg_s cn68xxp1;
 329 };
 330
 331 union cvmx_pcsxx_bit_lock_status_reg {
 332         uint64_t u64;
 333         struct cvmx_pcsxx_bit_lock_status_reg_s {
 334 #ifdef __BIG_ENDIAN_BITFIELD
 335                 uint64_t reserved_4_63:60;
 336                 uint64_t bitlck3:1;
 337                 uint64_t bitlck2:1;
 338                 uint64_t bitlck1:1;
 339                 uint64_t bitlck0:1;
 340 #else
 341                 uint64_t bitlck0:1;
 342                 uint64_t bitlck1:1;
 343                 uint64_t bitlck2:1;
 344                 uint64_t bitlck3:1;
 345                 uint64_t reserved_4_63:60;
 346 #endif
 347         } s;
 348         struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
 349         struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
 350         struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
 351         struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
 352         struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
 353         struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
 354         struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
 355         struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
 356         struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
 357         struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
 358 };
 359
 360 union cvmx_pcsxx_control1_reg {
 361         uint64_t u64;
 362         struct cvmx_pcsxx_control1_reg_s {
 363 #ifdef __BIG_ENDIAN_BITFIELD
 364                 uint64_t reserved_16_63:48;
 365                 uint64_t reset:1;
 366                 uint64_t loopbck1:1;
 367                 uint64_t spdsel1:1;
 368                 uint64_t reserved_12_12:1;
 369                 uint64_t lo_pwr:1;
 370                 uint64_t reserved_7_10:4;
 371                 uint64_t spdsel0:1;
 372                 uint64_t spd:4;
 373                 uint64_t reserved_0_1:2;
 374 #else
 375                 uint64_t reserved_0_1:2;
 376                 uint64_t spd:4;
 377                 uint64_t spdsel0:1;
 378                 uint64_t reserved_7_10:4;
 379                 uint64_t lo_pwr:1;
 380                 uint64_t reserved_12_12:1;
 381                 uint64_t spdsel1:1;
 382                 uint64_t loopbck1:1;
 383                 uint64_t reset:1;
 384                 uint64_t reserved_16_63:48;
 385 #endif
 386         } s;
 387         struct cvmx_pcsxx_control1_reg_s cn52xx;
 388         struct cvmx_pcsxx_control1_reg_s cn52xxp1;
 389         struct cvmx_pcsxx_control1_reg_s cn56xx;
 390         struct cvmx_pcsxx_control1_reg_s cn56xxp1;
 391         struct cvmx_pcsxx_control1_reg_s cn61xx;
 392         struct cvmx_pcsxx_control1_reg_s cn63xx;
 393         struct cvmx_pcsxx_control1_reg_s cn63xxp1;
 394         struct cvmx_pcsxx_control1_reg_s cn66xx;
 395         struct cvmx_pcsxx_control1_reg_s cn68xx;
 396         struct cvmx_pcsxx_control1_reg_s cn68xxp1;
 397 };
 398
 399 union cvmx_pcsxx_control2_reg {
 400         uint64_t u64;
 401         struct cvmx_pcsxx_control2_reg_s {
 402 #ifdef __BIG_ENDIAN_BITFIELD
 403                 uint64_t reserved_2_63:62;
 404                 uint64_t type:2;
 405 #else
 406                 uint64_t type:2;
 407                 uint64_t reserved_2_63:62;
 408 #endif
 409         } s;
 410         struct cvmx_pcsxx_control2_reg_s cn52xx;
 411         struct cvmx_pcsxx_control2_reg_s cn52xxp1;
 412         struct cvmx_pcsxx_control2_reg_s cn56xx;
 413         struct cvmx_pcsxx_control2_reg_s cn56xxp1;
 414         struct cvmx_pcsxx_control2_reg_s cn61xx;
 415         struct cvmx_pcsxx_control2_reg_s cn63xx;
 416         struct cvmx_pcsxx_control2_reg_s cn63xxp1;
 417         struct cvmx_pcsxx_control2_reg_s cn66xx;
 418         struct cvmx_pcsxx_control2_reg_s cn68xx;
 419         struct cvmx_pcsxx_control2_reg_s cn68xxp1;
 420 };
 421
 422 union cvmx_pcsxx_int_en_reg {
 423         uint64_t u64;
 424         struct cvmx_pcsxx_int_en_reg_s {
 425 #ifdef __BIG_ENDIAN_BITFIELD
 426                 uint64_t reserved_7_63:57;
 427                 uint64_t dbg_sync_en:1;
 428                 uint64_t algnlos_en:1;
 429                 uint64_t synlos_en:1;
 430                 uint64_t bitlckls_en:1;
 431                 uint64_t rxsynbad_en:1;
 432                 uint64_t rxbad_en:1;
 433                 uint64_t txflt_en:1;
 434 #else
 435                 uint64_t txflt_en:1;
 436                 uint64_t rxbad_en:1;
 437                 uint64_t rxsynbad_en:1;
 438                 uint64_t bitlckls_en:1;
 439                 uint64_t synlos_en:1;
 440                 uint64_t algnlos_en:1;
 441                 uint64_t dbg_sync_en:1;
 442                 uint64_t reserved_7_63:57;
 443 #endif
 444         } s;
 445         struct cvmx_pcsxx_int_en_reg_cn52xx {
 446 #ifdef __BIG_ENDIAN_BITFIELD
 447                 uint64_t reserved_6_63:58;
 448                 uint64_t algnlos_en:1;
 449                 uint64_t synlos_en:1;
 450                 uint64_t bitlckls_en:1;
 451                 uint64_t rxsynbad_en:1;
 452                 uint64_t rxbad_en:1;
 453                 uint64_t txflt_en:1;
 454 #else
 455                 uint64_t txflt_en:1;
 456                 uint64_t rxbad_en:1;
 457                 uint64_t rxsynbad_en:1;
 458                 uint64_t bitlckls_en:1;
 459                 uint64_t synlos_en:1;
 460                 uint64_t algnlos_en:1;
 461                 uint64_t reserved_6_63:58;
 462 #endif
 463         } cn52xx;
 464         struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1;
 465         struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx;
 466         struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1;
 467         struct cvmx_pcsxx_int_en_reg_s cn61xx;
 468         struct cvmx_pcsxx_int_en_reg_s cn63xx;
 469         struct cvmx_pcsxx_int_en_reg_s cn63xxp1;
 470         struct cvmx_pcsxx_int_en_reg_s cn66xx;
 471         struct cvmx_pcsxx_int_en_reg_s cn68xx;
 472         struct cvmx_pcsxx_int_en_reg_s cn68xxp1;
 473 };
 474
 475 union cvmx_pcsxx_int_reg {
 476         uint64_t u64;
 477         struct cvmx_pcsxx_int_reg_s {
 478 #ifdef __BIG_ENDIAN_BITFIELD
 479                 uint64_t reserved_7_63:57;
 480                 uint64_t dbg_sync:1;
 481                 uint64_t algnlos:1;
 482                 uint64_t synlos:1;
 483                 uint64_t bitlckls:1;
 484                 uint64_t rxsynbad:1;
 485                 uint64_t rxbad:1;
 486                 uint64_t txflt:1;
 487 #else
 488                 uint64_t txflt:1;
 489                 uint64_t rxbad:1;
 490                 uint64_t rxsynbad:1;
 491                 uint64_t bitlckls:1;
 492                 uint64_t synlos:1;
 493                 uint64_t algnlos:1;
 494                 uint64_t dbg_sync:1;
 495                 uint64_t reserved_7_63:57;
 496 #endif
 497         } s;
 498         struct cvmx_pcsxx_int_reg_cn52xx {
 499 #ifdef __BIG_ENDIAN_BITFIELD
 500                 uint64_t reserved_6_63:58;
 501                 uint64_t algnlos:1;
 502                 uint64_t synlos:1;
 503                 uint64_t bitlckls:1;
 504                 uint64_t rxsynbad:1;
 505                 uint64_t rxbad:1;
 506                 uint64_t txflt:1;
 507 #else
 508                 uint64_t txflt:1;
 509                 uint64_t rxbad:1;
 510                 uint64_t rxsynbad:1;
 511                 uint64_t bitlckls:1;
 512                 uint64_t synlos:1;
 513                 uint64_t algnlos:1;
 514                 uint64_t reserved_6_63:58;
 515 #endif
 516         } cn52xx;
 517         struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1;
 518         struct cvmx_pcsxx_int_reg_cn52xx cn56xx;
 519         struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1;
 520         struct cvmx_pcsxx_int_reg_s cn61xx;
 521         struct cvmx_pcsxx_int_reg_s cn63xx;
 522         struct cvmx_pcsxx_int_reg_s cn63xxp1;
 523         struct cvmx_pcsxx_int_reg_s cn66xx;
 524         struct cvmx_pcsxx_int_reg_s cn68xx;
 525         struct cvmx_pcsxx_int_reg_s cn68xxp1;
 526 };
 527
 528 union cvmx_pcsxx_log_anl_reg {
 529         uint64_t u64;
 530         struct cvmx_pcsxx_log_anl_reg_s {
 531 #ifdef __BIG_ENDIAN_BITFIELD
 532                 uint64_t reserved_7_63:57;
 533                 uint64_t enc_mode:1;
 534                 uint64_t drop_ln:2;
 535                 uint64_t lafifovfl:1;
 536                 uint64_t la_en:1;
 537                 uint64_t pkt_sz:2;
 538 #else
 539                 uint64_t pkt_sz:2;
 540                 uint64_t la_en:1;
 541                 uint64_t lafifovfl:1;
 542                 uint64_t drop_ln:2;
 543                 uint64_t enc_mode:1;
 544                 uint64_t reserved_7_63:57;
 545 #endif
 546         } s;
 547         struct cvmx_pcsxx_log_anl_reg_s cn52xx;
 548         struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
 549         struct cvmx_pcsxx_log_anl_reg_s cn56xx;
 550         struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
 551         struct cvmx_pcsxx_log_anl_reg_s cn61xx;
 552         struct cvmx_pcsxx_log_anl_reg_s cn63xx;
 553         struct cvmx_pcsxx_log_anl_reg_s cn63xxp1;
 554         struct cvmx_pcsxx_log_anl_reg_s cn66xx;
 555         struct cvmx_pcsxx_log_anl_reg_s cn68xx;
 556         struct cvmx_pcsxx_log_anl_reg_s cn68xxp1;
 557 };
 558
 559 union cvmx_pcsxx_misc_ctl_reg {
 560         uint64_t u64;
 561         struct cvmx_pcsxx_misc_ctl_reg_s {
 562 #ifdef __BIG_ENDIAN_BITFIELD
 563                 uint64_t reserved_4_63:60;
 564                 uint64_t tx_swap:1;
 565                 uint64_t rx_swap:1;
 566                 uint64_t xaui:1;
 567                 uint64_t gmxeno:1;
 568 #else
 569                 uint64_t gmxeno:1;
 570                 uint64_t xaui:1;
 571                 uint64_t rx_swap:1;
 572                 uint64_t tx_swap:1;
 573                 uint64_t reserved_4_63:60;
 574 #endif
 575         } s;
 576         struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
 577         struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
 578         struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
 579         struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
 580         struct cvmx_pcsxx_misc_ctl_reg_s cn61xx;
 581         struct cvmx_pcsxx_misc_ctl_reg_s cn63xx;
 582         struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1;
 583         struct cvmx_pcsxx_misc_ctl_reg_s cn66xx;
 584         struct cvmx_pcsxx_misc_ctl_reg_s cn68xx;
 585         struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1;
 586 };
 587
 588 union cvmx_pcsxx_rx_sync_states_reg {
 589         uint64_t u64;
 590         struct cvmx_pcsxx_rx_sync_states_reg_s {
 591 #ifdef __BIG_ENDIAN_BITFIELD
 592                 uint64_t reserved_16_63:48;
 593                 uint64_t sync3st:4;
 594                 uint64_t sync2st:4;
 595                 uint64_t sync1st:4;
 596                 uint64_t sync0st:4;
 597 #else
 598                 uint64_t sync0st:4;
 599                 uint64_t sync1st:4;
 600                 uint64_t sync2st:4;
 601                 uint64_t sync3st:4;
 602                 uint64_t reserved_16_63:48;
 603 #endif
 604         } s;
 605         struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
 606         struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
 607         struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
 608         struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
 609         struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
 610         struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
 611         struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
 612         struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
 613         struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
 614         struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
 615 };
 616
 617 union cvmx_pcsxx_spd_abil_reg {
 618         uint64_t u64;
 619         struct cvmx_pcsxx_spd_abil_reg_s {
 620 #ifdef __BIG_ENDIAN_BITFIELD
 621                 uint64_t reserved_2_63:62;
 622                 uint64_t tenpasst:1;
 623                 uint64_t tengb:1;
 624 #else
 625                 uint64_t tengb:1;
 626                 uint64_t tenpasst:1;
 627                 uint64_t reserved_2_63:62;
 628 #endif
 629         } s;
 630         struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
 631         struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
 632         struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
 633         struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
 634         struct cvmx_pcsxx_spd_abil_reg_s cn61xx;
 635         struct cvmx_pcsxx_spd_abil_reg_s cn63xx;
 636         struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1;
 637         struct cvmx_pcsxx_spd_abil_reg_s cn66xx;
 638         struct cvmx_pcsxx_spd_abil_reg_s cn68xx;
 639         struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1;
 640 };
 641
 642 union cvmx_pcsxx_status1_reg {
 643         uint64_t u64;
 644         struct cvmx_pcsxx_status1_reg_s {
 645 #ifdef __BIG_ENDIAN_BITFIELD
 646                 uint64_t reserved_8_63:56;
 647                 uint64_t flt:1;
 648                 uint64_t reserved_3_6:4;
 649                 uint64_t rcv_lnk:1;
 650                 uint64_t lpable:1;
 651                 uint64_t reserved_0_0:1;
 652 #else
 653                 uint64_t reserved_0_0:1;
 654                 uint64_t lpable:1;
 655                 uint64_t rcv_lnk:1;
 656                 uint64_t reserved_3_6:4;
 657                 uint64_t flt:1;
 658                 uint64_t reserved_8_63:56;
 659 #endif
 660         } s;
 661         struct cvmx_pcsxx_status1_reg_s cn52xx;
 662         struct cvmx_pcsxx_status1_reg_s cn52xxp1;
 663         struct cvmx_pcsxx_status1_reg_s cn56xx;
 664         struct cvmx_pcsxx_status1_reg_s cn56xxp1;
 665         struct cvmx_pcsxx_status1_reg_s cn61xx;
 666         struct cvmx_pcsxx_status1_reg_s cn63xx;
 667         struct cvmx_pcsxx_status1_reg_s cn63xxp1;
 668         struct cvmx_pcsxx_status1_reg_s cn66xx;
 669         struct cvmx_pcsxx_status1_reg_s cn68xx;
 670         struct cvmx_pcsxx_status1_reg_s cn68xxp1;
 671 };
 672
 673 union cvmx_pcsxx_status2_reg {
 674         uint64_t u64;
 675         struct cvmx_pcsxx_status2_reg_s {
 676 #ifdef __BIG_ENDIAN_BITFIELD
 677                 uint64_t reserved_16_63:48;
 678                 uint64_t dev:2;
 679                 uint64_t reserved_12_13:2;
 680                 uint64_t xmtflt:1;
 681                 uint64_t rcvflt:1;
 682                 uint64_t reserved_3_9:7;
 683                 uint64_t tengb_w:1;
 684                 uint64_t tengb_x:1;
 685                 uint64_t tengb_r:1;
 686 #else
 687                 uint64_t tengb_r:1;
 688                 uint64_t tengb_x:1;
 689                 uint64_t tengb_w:1;
 690                 uint64_t reserved_3_9:7;
 691                 uint64_t rcvflt:1;
 692                 uint64_t xmtflt:1;
 693                 uint64_t reserved_12_13:2;
 694                 uint64_t dev:2;
 695                 uint64_t reserved_16_63:48;
 696 #endif
 697         } s;
 698         struct cvmx_pcsxx_status2_reg_s cn52xx;
 699         struct cvmx_pcsxx_status2_reg_s cn52xxp1;
 700         struct cvmx_pcsxx_status2_reg_s cn56xx;
 701         struct cvmx_pcsxx_status2_reg_s cn56xxp1;
 702         struct cvmx_pcsxx_status2_reg_s cn61xx;
 703         struct cvmx_pcsxx_status2_reg_s cn63xx;
 704         struct cvmx_pcsxx_status2_reg_s cn63xxp1;
 705         struct cvmx_pcsxx_status2_reg_s cn66xx;
 706         struct cvmx_pcsxx_status2_reg_s cn68xx;
 707         struct cvmx_pcsxx_status2_reg_s cn68xxp1;
 708 };
 709
 710 union cvmx_pcsxx_tx_rx_polarity_reg {
 711         uint64_t u64;
 712         struct cvmx_pcsxx_tx_rx_polarity_reg_s {
 713 #ifdef __BIG_ENDIAN_BITFIELD
 714                 uint64_t reserved_10_63:54;
 715                 uint64_t xor_rxplrt:4;
 716                 uint64_t xor_txplrt:4;
 717                 uint64_t rxplrt:1;
 718                 uint64_t txplrt:1;
 719 #else
 720                 uint64_t txplrt:1;
 721                 uint64_t rxplrt:1;
 722                 uint64_t xor_txplrt:4;
 723                 uint64_t xor_rxplrt:4;
 724                 uint64_t reserved_10_63:54;
 725 #endif
 726         } s;
 727         struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
 728         struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
 729 #ifdef __BIG_ENDIAN_BITFIELD
 730                 uint64_t reserved_2_63:62;
 731                 uint64_t rxplrt:1;
 732                 uint64_t txplrt:1;
 733 #else
 734                 uint64_t txplrt:1;
 735                 uint64_t rxplrt:1;
 736                 uint64_t reserved_2_63:62;
 737 #endif
 738         } cn52xxp1;
 739         struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
 740         struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
 741         struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
 742         struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
 743         struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
 744         struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
 745         struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
 746         struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
 747 };
 748
 749 union cvmx_pcsxx_tx_rx_states_reg {
 750         uint64_t u64;
 751         struct cvmx_pcsxx_tx_rx_states_reg_s {
 752 #ifdef __BIG_ENDIAN_BITFIELD
 753                 uint64_t reserved_14_63:50;
 754                 uint64_t term_err:1;
 755                 uint64_t syn3bad:1;
 756                 uint64_t syn2bad:1;
 757                 uint64_t syn1bad:1;
 758                 uint64_t syn0bad:1;
 759                 uint64_t rxbad:1;
 760                 uint64_t algn_st:3;
 761                 uint64_t rx_st:2;
 762                 uint64_t tx_st:3;
 763 #else
 764                 uint64_t tx_st:3;
 765                 uint64_t rx_st:2;
 766                 uint64_t algn_st:3;
 767                 uint64_t rxbad:1;
 768                 uint64_t syn0bad:1;
 769                 uint64_t syn1bad:1;
 770                 uint64_t syn2bad:1;
 771                 uint64_t syn3bad:1;
 772                 uint64_t term_err:1;
 773                 uint64_t reserved_14_63:50;
 774 #endif
 775         } s;
 776         struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
 777         struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
 778 #ifdef __BIG_ENDIAN_BITFIELD
 779                 uint64_t reserved_13_63:51;
 780                 uint64_t syn3bad:1;
 781                 uint64_t syn2bad:1;
 782                 uint64_t syn1bad:1;
 783                 uint64_t syn0bad:1;
 784                 uint64_t rxbad:1;
 785                 uint64_t algn_st:3;
 786                 uint64_t rx_st:2;
 787                 uint64_t tx_st:3;
 788 #else
 789                 uint64_t tx_st:3;
 790                 uint64_t rx_st:2;
 791                 uint64_t algn_st:3;
 792                 uint64_t rxbad:1;
 793                 uint64_t syn0bad:1;
 794                 uint64_t syn1bad:1;
 795                 uint64_t syn2bad:1;
 796                 uint64_t syn3bad:1;
 797                 uint64_t reserved_13_63:51;
 798 #endif
 799         } cn52xxp1;
 800         struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
 801         struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
 802         struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx;
 803         struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx;
 804         struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1;
 805         struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx;
 806         struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx;
 807         struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1;
 808 };
 809
 810 #endif