arch/mips/include/asm/octeon/cvmx-spxx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
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  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
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  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_SPXX_DEFS_H__
  29 #define __CVMX_SPXX_DEFS_H__
  30
  31 #define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
  32 #define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
  33 #define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
  34 #define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
  35 #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
  36 #define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
  37 #define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
  38 #define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
  39 #define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
  40 #define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
  41 #define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
  42 #define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
  43 #define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
  44 #define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
  45 #define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
  46 #define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
  47
  48 void __cvmx_interrupt_spxx_int_msk_enable(int index);
  49
  50 union cvmx_spxx_bckprs_cnt {
  51         uint64_t u64;
  52         struct cvmx_spxx_bckprs_cnt_s {
  53 #ifdef __BIG_ENDIAN_BITFIELD
  54                 uint64_t reserved_32_63:32;
  55                 uint64_t cnt:32;
  56 #else
  57                 uint64_t cnt:32;
  58                 uint64_t reserved_32_63:32;
  59 #endif
  60         } s;
  61         struct cvmx_spxx_bckprs_cnt_s cn38xx;
  62         struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
  63         struct cvmx_spxx_bckprs_cnt_s cn58xx;
  64         struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
  65 };
  66
  67 union cvmx_spxx_bist_stat {
  68         uint64_t u64;
  69         struct cvmx_spxx_bist_stat_s {
  70 #ifdef __BIG_ENDIAN_BITFIELD
  71                 uint64_t reserved_3_63:61;
  72                 uint64_t stat2:1;
  73                 uint64_t stat1:1;
  74                 uint64_t stat0:1;
  75 #else
  76                 uint64_t stat0:1;
  77                 uint64_t stat1:1;
  78                 uint64_t stat2:1;
  79                 uint64_t reserved_3_63:61;
  80 #endif
  81         } s;
  82         struct cvmx_spxx_bist_stat_s cn38xx;
  83         struct cvmx_spxx_bist_stat_s cn38xxp2;
  84         struct cvmx_spxx_bist_stat_s cn58xx;
  85         struct cvmx_spxx_bist_stat_s cn58xxp1;
  86 };
  87
  88 union cvmx_spxx_clk_ctl {
  89         uint64_t u64;
  90         struct cvmx_spxx_clk_ctl_s {
  91 #ifdef __BIG_ENDIAN_BITFIELD
  92                 uint64_t reserved_17_63:47;
  93                 uint64_t seetrn:1;
  94                 uint64_t reserved_12_15:4;
  95                 uint64_t clkdly:5;
  96                 uint64_t runbist:1;
  97                 uint64_t statdrv:1;
  98                 uint64_t statrcv:1;
  99                 uint64_t sndtrn:1;
 100                 uint64_t drptrn:1;
 101                 uint64_t rcvtrn:1;
 102                 uint64_t srxdlck:1;
 103 #else
 104                 uint64_t srxdlck:1;
 105                 uint64_t rcvtrn:1;
 106                 uint64_t drptrn:1;
 107                 uint64_t sndtrn:1;
 108                 uint64_t statrcv:1;
 109                 uint64_t statdrv:1;
 110                 uint64_t runbist:1;
 111                 uint64_t clkdly:5;
 112                 uint64_t reserved_12_15:4;
 113                 uint64_t seetrn:1;
 114                 uint64_t reserved_17_63:47;
 115 #endif
 116         } s;
 117         struct cvmx_spxx_clk_ctl_s cn38xx;
 118         struct cvmx_spxx_clk_ctl_s cn38xxp2;
 119         struct cvmx_spxx_clk_ctl_s cn58xx;
 120         struct cvmx_spxx_clk_ctl_s cn58xxp1;
 121 };
 122
 123 union cvmx_spxx_clk_stat {
 124         uint64_t u64;
 125         struct cvmx_spxx_clk_stat_s {
 126 #ifdef __BIG_ENDIAN_BITFIELD
 127                 uint64_t reserved_11_63:53;
 128                 uint64_t stxcal:1;
 129                 uint64_t reserved_9_9:1;
 130                 uint64_t srxtrn:1;
 131                 uint64_t s4clk1:1;
 132                 uint64_t s4clk0:1;
 133                 uint64_t d4clk1:1;
 134                 uint64_t d4clk0:1;
 135                 uint64_t reserved_0_3:4;
 136 #else
 137                 uint64_t reserved_0_3:4;
 138                 uint64_t d4clk0:1;
 139                 uint64_t d4clk1:1;
 140                 uint64_t s4clk0:1;
 141                 uint64_t s4clk1:1;
 142                 uint64_t srxtrn:1;
 143                 uint64_t reserved_9_9:1;
 144                 uint64_t stxcal:1;
 145                 uint64_t reserved_11_63:53;
 146 #endif
 147         } s;
 148         struct cvmx_spxx_clk_stat_s cn38xx;
 149         struct cvmx_spxx_clk_stat_s cn38xxp2;
 150         struct cvmx_spxx_clk_stat_s cn58xx;
 151         struct cvmx_spxx_clk_stat_s cn58xxp1;
 152 };
 153
 154 union cvmx_spxx_dbg_deskew_ctl {
 155         uint64_t u64;
 156         struct cvmx_spxx_dbg_deskew_ctl_s {
 157 #ifdef __BIG_ENDIAN_BITFIELD
 158                 uint64_t reserved_30_63:34;
 159                 uint64_t fallnop:1;
 160                 uint64_t fall8:1;
 161                 uint64_t reserved_26_27:2;
 162                 uint64_t sstep_go:1;
 163                 uint64_t sstep:1;
 164                 uint64_t reserved_22_23:2;
 165                 uint64_t clrdly:1;
 166                 uint64_t dec:1;
 167                 uint64_t inc:1;
 168                 uint64_t mux:1;
 169                 uint64_t offset:5;
 170                 uint64_t bitsel:5;
 171                 uint64_t offdly:6;
 172                 uint64_t dllfrc:1;
 173                 uint64_t dlldis:1;
 174 #else
 175                 uint64_t dlldis:1;
 176                 uint64_t dllfrc:1;
 177                 uint64_t offdly:6;
 178                 uint64_t bitsel:5;
 179                 uint64_t offset:5;
 180                 uint64_t mux:1;
 181                 uint64_t inc:1;
 182                 uint64_t dec:1;
 183                 uint64_t clrdly:1;
 184                 uint64_t reserved_22_23:2;
 185                 uint64_t sstep:1;
 186                 uint64_t sstep_go:1;
 187                 uint64_t reserved_26_27:2;
 188                 uint64_t fall8:1;
 189                 uint64_t fallnop:1;
 190                 uint64_t reserved_30_63:34;
 191 #endif
 192         } s;
 193         struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
 194         struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
 195         struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
 196         struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
 197 };
 198
 199 union cvmx_spxx_dbg_deskew_state {
 200         uint64_t u64;
 201         struct cvmx_spxx_dbg_deskew_state_s {
 202 #ifdef __BIG_ENDIAN_BITFIELD
 203                 uint64_t reserved_9_63:55;
 204                 uint64_t testres:1;
 205                 uint64_t unxterm:1;
 206                 uint64_t muxsel:2;
 207                 uint64_t offset:5;
 208 #else
 209                 uint64_t offset:5;
 210                 uint64_t muxsel:2;
 211                 uint64_t unxterm:1;
 212                 uint64_t testres:1;
 213                 uint64_t reserved_9_63:55;
 214 #endif
 215         } s;
 216         struct cvmx_spxx_dbg_deskew_state_s cn38xx;
 217         struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
 218         struct cvmx_spxx_dbg_deskew_state_s cn58xx;
 219         struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
 220 };
 221
 222 union cvmx_spxx_drv_ctl {
 223         uint64_t u64;
 224         struct cvmx_spxx_drv_ctl_s {
 225 #ifdef __BIG_ENDIAN_BITFIELD
 226                 uint64_t reserved_0_63:64;
 227 #else
 228                 uint64_t reserved_0_63:64;
 229 #endif
 230         } s;
 231         struct cvmx_spxx_drv_ctl_cn38xx {
 232 #ifdef __BIG_ENDIAN_BITFIELD
 233                 uint64_t reserved_16_63:48;
 234                 uint64_t stx4ncmp:4;
 235                 uint64_t stx4pcmp:4;
 236                 uint64_t srx4cmp:8;
 237 #else
 238                 uint64_t srx4cmp:8;
 239                 uint64_t stx4pcmp:4;
 240                 uint64_t stx4ncmp:4;
 241                 uint64_t reserved_16_63:48;
 242 #endif
 243         } cn38xx;
 244         struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
 245         struct cvmx_spxx_drv_ctl_cn58xx {
 246 #ifdef __BIG_ENDIAN_BITFIELD
 247                 uint64_t reserved_24_63:40;
 248                 uint64_t stx4ncmp:4;
 249                 uint64_t stx4pcmp:4;
 250                 uint64_t reserved_10_15:6;
 251                 uint64_t srx4cmp:10;
 252 #else
 253                 uint64_t srx4cmp:10;
 254                 uint64_t reserved_10_15:6;
 255                 uint64_t stx4pcmp:4;
 256                 uint64_t stx4ncmp:4;
 257                 uint64_t reserved_24_63:40;
 258 #endif
 259         } cn58xx;
 260         struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
 261 };
 262
 263 union cvmx_spxx_err_ctl {
 264         uint64_t u64;
 265         struct cvmx_spxx_err_ctl_s {
 266 #ifdef __BIG_ENDIAN_BITFIELD
 267                 uint64_t reserved_9_63:55;
 268                 uint64_t prtnxa:1;
 269                 uint64_t dipcls:1;
 270                 uint64_t dippay:1;
 271                 uint64_t reserved_4_5:2;
 272                 uint64_t errcnt:4;
 273 #else
 274                 uint64_t errcnt:4;
 275                 uint64_t reserved_4_5:2;
 276                 uint64_t dippay:1;
 277                 uint64_t dipcls:1;
 278                 uint64_t prtnxa:1;
 279                 uint64_t reserved_9_63:55;
 280 #endif
 281         } s;
 282         struct cvmx_spxx_err_ctl_s cn38xx;
 283         struct cvmx_spxx_err_ctl_s cn38xxp2;
 284         struct cvmx_spxx_err_ctl_s cn58xx;
 285         struct cvmx_spxx_err_ctl_s cn58xxp1;
 286 };
 287
 288 union cvmx_spxx_int_dat {
 289         uint64_t u64;
 290         struct cvmx_spxx_int_dat_s {
 291 #ifdef __BIG_ENDIAN_BITFIELD
 292                 uint64_t reserved_32_63:32;
 293                 uint64_t mul:1;
 294                 uint64_t reserved_14_30:17;
 295                 uint64_t calbnk:2;
 296                 uint64_t rsvop:4;
 297                 uint64_t prt:8;
 298 #else
 299                 uint64_t prt:8;
 300                 uint64_t rsvop:4;
 301                 uint64_t calbnk:2;
 302                 uint64_t reserved_14_30:17;
 303                 uint64_t mul:1;
 304                 uint64_t reserved_32_63:32;
 305 #endif
 306         } s;
 307         struct cvmx_spxx_int_dat_s cn38xx;
 308         struct cvmx_spxx_int_dat_s cn38xxp2;
 309         struct cvmx_spxx_int_dat_s cn58xx;
 310         struct cvmx_spxx_int_dat_s cn58xxp1;
 311 };
 312
 313 union cvmx_spxx_int_msk {
 314         uint64_t u64;
 315         struct cvmx_spxx_int_msk_s {
 316 #ifdef __BIG_ENDIAN_BITFIELD
 317                 uint64_t reserved_12_63:52;
 318                 uint64_t calerr:1;
 319                 uint64_t syncerr:1;
 320                 uint64_t diperr:1;
 321                 uint64_t tpaovr:1;
 322                 uint64_t rsverr:1;
 323                 uint64_t drwnng:1;
 324                 uint64_t clserr:1;
 325                 uint64_t spiovr:1;
 326                 uint64_t reserved_2_3:2;
 327                 uint64_t abnorm:1;
 328                 uint64_t prtnxa:1;
 329 #else
 330                 uint64_t prtnxa:1;
 331                 uint64_t abnorm:1;
 332                 uint64_t reserved_2_3:2;
 333                 uint64_t spiovr:1;
 334                 uint64_t clserr:1;
 335                 uint64_t drwnng:1;
 336                 uint64_t rsverr:1;
 337                 uint64_t tpaovr:1;
 338                 uint64_t diperr:1;
 339                 uint64_t syncerr:1;
 340                 uint64_t calerr:1;
 341                 uint64_t reserved_12_63:52;
 342 #endif
 343         } s;
 344         struct cvmx_spxx_int_msk_s cn38xx;
 345         struct cvmx_spxx_int_msk_s cn38xxp2;
 346         struct cvmx_spxx_int_msk_s cn58xx;
 347         struct cvmx_spxx_int_msk_s cn58xxp1;
 348 };
 349
 350 union cvmx_spxx_int_reg {
 351         uint64_t u64;
 352         struct cvmx_spxx_int_reg_s {
 353 #ifdef __BIG_ENDIAN_BITFIELD
 354                 uint64_t reserved_32_63:32;
 355                 uint64_t spf:1;
 356                 uint64_t reserved_12_30:19;
 357                 uint64_t calerr:1;
 358                 uint64_t syncerr:1;
 359                 uint64_t diperr:1;
 360                 uint64_t tpaovr:1;
 361                 uint64_t rsverr:1;
 362                 uint64_t drwnng:1;
 363                 uint64_t clserr:1;
 364                 uint64_t spiovr:1;
 365                 uint64_t reserved_2_3:2;
 366                 uint64_t abnorm:1;
 367                 uint64_t prtnxa:1;
 368 #else
 369                 uint64_t prtnxa:1;
 370                 uint64_t abnorm:1;
 371                 uint64_t reserved_2_3:2;
 372                 uint64_t spiovr:1;
 373                 uint64_t clserr:1;
 374                 uint64_t drwnng:1;
 375                 uint64_t rsverr:1;
 376                 uint64_t tpaovr:1;
 377                 uint64_t diperr:1;
 378                 uint64_t syncerr:1;
 379                 uint64_t calerr:1;
 380                 uint64_t reserved_12_30:19;
 381                 uint64_t spf:1;
 382                 uint64_t reserved_32_63:32;
 383 #endif
 384         } s;
 385         struct cvmx_spxx_int_reg_s cn38xx;
 386         struct cvmx_spxx_int_reg_s cn38xxp2;
 387         struct cvmx_spxx_int_reg_s cn58xx;
 388         struct cvmx_spxx_int_reg_s cn58xxp1;
 389 };
 390
 391 union cvmx_spxx_int_sync {
 392         uint64_t u64;
 393         struct cvmx_spxx_int_sync_s {
 394 #ifdef __BIG_ENDIAN_BITFIELD
 395                 uint64_t reserved_12_63:52;
 396                 uint64_t calerr:1;
 397                 uint64_t syncerr:1;
 398                 uint64_t diperr:1;
 399                 uint64_t tpaovr:1;
 400                 uint64_t rsverr:1;
 401                 uint64_t drwnng:1;
 402                 uint64_t clserr:1;
 403                 uint64_t spiovr:1;
 404                 uint64_t reserved_2_3:2;
 405                 uint64_t abnorm:1;
 406                 uint64_t prtnxa:1;
 407 #else
 408                 uint64_t prtnxa:1;
 409                 uint64_t abnorm:1;
 410                 uint64_t reserved_2_3:2;
 411                 uint64_t spiovr:1;
 412                 uint64_t clserr:1;
 413                 uint64_t drwnng:1;
 414                 uint64_t rsverr:1;
 415                 uint64_t tpaovr:1;
 416                 uint64_t diperr:1;
 417                 uint64_t syncerr:1;
 418                 uint64_t calerr:1;
 419                 uint64_t reserved_12_63:52;
 420 #endif
 421         } s;
 422         struct cvmx_spxx_int_sync_s cn38xx;
 423         struct cvmx_spxx_int_sync_s cn38xxp2;
 424         struct cvmx_spxx_int_sync_s cn58xx;
 425         struct cvmx_spxx_int_sync_s cn58xxp1;
 426 };
 427
 428 union cvmx_spxx_tpa_acc {
 429         uint64_t u64;
 430         struct cvmx_spxx_tpa_acc_s {
 431 #ifdef __BIG_ENDIAN_BITFIELD
 432                 uint64_t reserved_32_63:32;
 433                 uint64_t cnt:32;
 434 #else
 435                 uint64_t cnt:32;
 436                 uint64_t reserved_32_63:32;
 437 #endif
 438         } s;
 439         struct cvmx_spxx_tpa_acc_s cn38xx;
 440         struct cvmx_spxx_tpa_acc_s cn38xxp2;
 441         struct cvmx_spxx_tpa_acc_s cn58xx;
 442         struct cvmx_spxx_tpa_acc_s cn58xxp1;
 443 };
 444
 445 union cvmx_spxx_tpa_max {
 446         uint64_t u64;
 447         struct cvmx_spxx_tpa_max_s {
 448 #ifdef __BIG_ENDIAN_BITFIELD
 449                 uint64_t reserved_32_63:32;
 450                 uint64_t max:32;
 451 #else
 452                 uint64_t max:32;
 453                 uint64_t reserved_32_63:32;
 454 #endif
 455         } s;
 456         struct cvmx_spxx_tpa_max_s cn38xx;
 457         struct cvmx_spxx_tpa_max_s cn38xxp2;
 458         struct cvmx_spxx_tpa_max_s cn58xx;
 459         struct cvmx_spxx_tpa_max_s cn58xxp1;
 460 };
 461
 462 union cvmx_spxx_tpa_sel {
 463         uint64_t u64;
 464         struct cvmx_spxx_tpa_sel_s {
 465 #ifdef __BIG_ENDIAN_BITFIELD
 466                 uint64_t reserved_4_63:60;
 467                 uint64_t prtsel:4;
 468 #else
 469                 uint64_t prtsel:4;
 470                 uint64_t reserved_4_63:60;
 471 #endif
 472         } s;
 473         struct cvmx_spxx_tpa_sel_s cn38xx;
 474         struct cvmx_spxx_tpa_sel_s cn38xxp2;
 475         struct cvmx_spxx_tpa_sel_s cn58xx;
 476         struct cvmx_spxx_tpa_sel_s cn58xxp1;
 477 };
 478
 479 union cvmx_spxx_trn4_ctl {
 480         uint64_t u64;
 481         struct cvmx_spxx_trn4_ctl_s {
 482 #ifdef __BIG_ENDIAN_BITFIELD
 483                 uint64_t reserved_13_63:51;
 484                 uint64_t trntest:1;
 485                 uint64_t jitter:3;
 486                 uint64_t clr_boot:1;
 487                 uint64_t set_boot:1;
 488                 uint64_t maxdist:5;
 489                 uint64_t macro_en:1;
 490                 uint64_t mux_en:1;
 491 #else
 492                 uint64_t mux_en:1;
 493                 uint64_t macro_en:1;
 494                 uint64_t maxdist:5;
 495                 uint64_t set_boot:1;
 496                 uint64_t clr_boot:1;
 497                 uint64_t jitter:3;
 498                 uint64_t trntest:1;
 499                 uint64_t reserved_13_63:51;
 500 #endif
 501         } s;
 502         struct cvmx_spxx_trn4_ctl_s cn38xx;
 503         struct cvmx_spxx_trn4_ctl_s cn38xxp2;
 504         struct cvmx_spxx_trn4_ctl_s cn58xx;
 505         struct cvmx_spxx_trn4_ctl_s cn58xxp1;
 506 };
 507
 508 #endif