arch/mips/kernel/smp-bmips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
   7  *
   8  * SMP support for BMIPS
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/sched.h>
  13 #include <linux/mm.h>
  14 #include <linux/delay.h>
  15 #include <linux/smp.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/cpu.h>
  19 #include <linux/cpumask.h>
  20 #include <linux/reboot.h>
  21 #include <linux/io.h>
  22 #include <linux/compiler.h>
  23 #include <linux/linkage.h>
  24 #include <linux/bug.h>
  25 #include <linux/kernel.h>
  26
  27 #include <asm/time.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/processor.h>
  30 #include <asm/bootinfo.h>
  31 #include <asm/pmon.h>
  32 #include <asm/cacheflush.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/mipsregs.h>
  35 #include <asm/bmips.h>
  36 #include <asm/traps.h>
  37 #include <asm/barrier.h>
  38 #include <asm/cpu-features.h>
  39
  40 static int __maybe_unused max_cpus = 1;
  41
  42 /* these may be configured by the platform code */
  43 int bmips_smp_enabled = 1;
  44 int bmips_cpu_offset;
  45 cpumask_t bmips_booted_mask;
  46 unsigned long bmips_tp1_irqs = IE_IRQ1;
  47
  48 #define RESET_FROM_KSEG0                0x80080800
  49 #define RESET_FROM_KSEG1                0xa0080800
  50
  51 static void bmips_set_reset_vec(int cpu, u32 val);
  52
  53 #ifdef CONFIG_SMP
  54
  55 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
  56 unsigned long bmips_smp_boot_sp;
  57 unsigned long bmips_smp_boot_gp;
  58
  59 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
  60 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
  61 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
  62 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
  63
  64 /* SW interrupts 0,1 are used for interprocessor signaling */
  65 #define IPI0_IRQ                        (MIPS_CPU_IRQ_BASE + 0)
  66 #define IPI1_IRQ                        (MIPS_CPU_IRQ_BASE + 1)
  67
  68 #define CPUNUM(cpu, shift)              (((cpu) + bmips_cpu_offset) << (shift))
  69 #define ACTION_CLR_IPI(cpu, ipi)        (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  70 #define ACTION_SET_IPI(cpu, ipi)        (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  71 #define ACTION_BOOT_THREAD(cpu)         (0x08 | CPUNUM(cpu, 0))
  72
  73 static void __init bmips_smp_setup(void)
  74 {
  75         int i, cpu = 1, boot_cpu = 0;
  76         int cpu_hw_intr;
  77
  78         switch (current_cpu_type()) {
  79         case CPU_BMIPS4350:
  80         case CPU_BMIPS4380:
  81                 /* arbitration priority */
  82                 clear_c0_brcm_cmt_ctrl(0x30);
  83
  84                 /* NBK and weak order flags */
  85                 set_c0_brcm_config_0(0x30000);
  86
  87                 /* Find out if we are running on TP0 or TP1 */
  88                 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
  89
  90                 /*
  91                  * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
  92                  * thread
  93                  * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
  94                  * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
  95                  */
  96                 if (boot_cpu == 0)
  97                         cpu_hw_intr = 0x02;
  98                 else
  99                         cpu_hw_intr = 0x1d;
 100
 101                 change_c0_brcm_cmt_intr(0xf8018000,
 102                                         (cpu_hw_intr << 27) | (0x03 << 15));
 103
 104                 /* single core, 2 threads (2 pipelines) */
 105                 max_cpus = 2;
 106
 107                 break;
 108         case CPU_BMIPS5000:
 109                 /* enable raceless SW interrupts */
 110                 set_c0_brcm_config(0x03 << 22);
 111
 112                 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
 113                 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
 114
 115                 /* N cores, 2 threads per core */
 116                 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
 117
 118                 /* clear any pending SW interrupts */
 119                 for (i = 0; i < max_cpus; i++) {
 120                         write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
 121                         write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
 122                 }
 123
 124                 break;
 125         default:
 126                 max_cpus = 1;
 127         }
 128
 129         if (!bmips_smp_enabled)
 130                 max_cpus = 1;
 131
 132         /* this can be overridden by the BSP */
 133         if (!board_ebase_setup)
 134                 board_ebase_setup = &bmips_ebase_setup;
 135
 136         __cpu_number_map[boot_cpu] = 0;
 137         __cpu_logical_map[0] = boot_cpu;
 138
 139         for (i = 0; i < max_cpus; i++) {
 140                 if (i != boot_cpu) {
 141                         __cpu_number_map[i] = cpu;
 142                         __cpu_logical_map[cpu] = i;
 143                         cpu++;
 144                 }
 145                 set_cpu_possible(i, 1);
 146                 set_cpu_present(i, 1);
 147         }
 148 }
 149
 150 /*
 151  * IPI IRQ setup - runs on CPU0
 152  */
 153 static void bmips_prepare_cpus(unsigned int max_cpus)
 154 {
 155         irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
 156
 157         switch (current_cpu_type()) {
 158         case CPU_BMIPS4350:
 159         case CPU_BMIPS4380:
 160                 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
 161                 break;
 162         case CPU_BMIPS5000:
 163                 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
 164                 break;
 165         default:
 166                 return;
 167         }
 168
 169         if (request_irq(IPI0_IRQ, bmips_ipi_interrupt,
 170                         IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL))
 171                 panic("Can't request IPI0 interrupt");
 172         if (request_irq(IPI1_IRQ, bmips_ipi_interrupt,
 173                         IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL))
 174                 panic("Can't request IPI1 interrupt");
 175 }
 176
 177 /*
 178  * Tell the hardware to boot CPUx - runs on CPU0
 179  */
 180 static void bmips_boot_secondary(int cpu, struct task_struct *idle)
 181 {
 182         bmips_smp_boot_sp = __KSTK_TOS(idle);
 183         bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
 184         mb();
 185
 186         /*
 187          * Initial boot sequence for secondary CPU:
 188          *   bmips_reset_nmi_vec @ a000_0000 ->
 189          *   bmips_smp_entry ->
 190          *   plat_wired_tlb_setup (cached function call; optional) ->
 191          *   start_secondary (cached jump)
 192          *
 193          * Warm restart sequence:
 194          *   play_dead WAIT loop ->
 195          *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
 196          *   eret to play_dead ->
 197          *   bmips_secondary_reentry ->
 198          *   start_secondary
 199          */
 200
 201         pr_info("SMP: Booting CPU%d...\n", cpu);
 202
 203         if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
 204                 /* kseg1 might not exist if this CPU enabled XKS01 */
 205                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
 206
 207                 switch (current_cpu_type()) {
 208                 case CPU_BMIPS4350:
 209                 case CPU_BMIPS4380:
 210                         bmips43xx_send_ipi_single(cpu, 0);
 211                         break;
 212                 case CPU_BMIPS5000:
 213                         bmips5000_send_ipi_single(cpu, 0);
 214                         break;
 215                 }
 216         } else {
 217                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
 218
 219                 switch (current_cpu_type()) {
 220                 case CPU_BMIPS4350:
 221                 case CPU_BMIPS4380:
 222                         /* Reset slave TP1 if booting from TP0 */
 223                         if (cpu_logical_map(cpu) == 1)
 224                                 set_c0_brcm_cmt_ctrl(0x01);
 225                         break;
 226                 case CPU_BMIPS5000:
 227                         write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
 228                         break;
 229                 }
 230                 cpumask_set_cpu(cpu, &bmips_booted_mask);
 231         }
 232 }
 233
 234 /*
 235  * Early setup - runs on secondary CPU after cache probe
 236  */
 237 static void bmips_init_secondary(void)
 238 {
 239         bmips_cpu_setup();
 240
 241         switch (current_cpu_type()) {
 242         case CPU_BMIPS4350:
 243         case CPU_BMIPS4380:
 244                 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
 245                 break;
 246         case CPU_BMIPS5000:
 247                 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
 248                 current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3;
 249                 break;
 250         }
 251 }
 252
 253 /*
 254  * Late setup - runs on secondary CPU before entering the idle loop
 255  */
 256 static void bmips_smp_finish(void)
 257 {
 258         pr_info("SMP: CPU%d is running\n", smp_processor_id());
 259
 260         /* make sure there won't be a timer interrupt for a little while */
 261         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 262
 263         irq_enable_hazard();
 264         set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
 265         irq_enable_hazard();
 266 }
 267
 268 /*
 269  * BMIPS5000 raceless IPIs
 270  *
 271  * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
 272  * IPI0 is used for SMP_RESCHEDULE_YOURSELF
 273  * IPI1 is used for SMP_CALL_FUNCTION
 274  */
 275
 276 static void bmips5000_send_ipi_single(int cpu, unsigned int action)
 277 {
 278         write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
 279 }
 280
 281 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
 282 {
 283         int action = irq - IPI0_IRQ;
 284
 285         write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
 286
 287         if (action == 0)
 288                 scheduler_ipi();
 289         else
 290                 generic_smp_call_function_interrupt();
 291
 292         return IRQ_HANDLED;
 293 }
 294
 295 static void bmips5000_send_ipi_mask(const struct cpumask *mask,
 296         unsigned int action)
 297 {
 298         unsigned int i;
 299
 300         for_each_cpu(i, mask)
 301                 bmips5000_send_ipi_single(i, action);
 302 }
 303
 304 /*
 305  * BMIPS43xx racey IPIs
 306  *
 307  * We use one inbound SW IRQ for each CPU.
 308  *
 309  * A spinlock must be held in order to keep CPUx from accidentally clearing
 310  * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy.  The
 311  * same spinlock is used to protect the action masks.
 312  */
 313
 314 static DEFINE_SPINLOCK(ipi_lock);
 315 static DEFINE_PER_CPU(int, ipi_action_mask);
 316
 317 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
 318 {
 319         unsigned long flags;
 320
 321         spin_lock_irqsave(&ipi_lock, flags);
 322         set_c0_cause(cpu ? C_SW1 : C_SW0);
 323         per_cpu(ipi_action_mask, cpu) |= action;
 324         irq_enable_hazard();
 325         spin_unlock_irqrestore(&ipi_lock, flags);
 326 }
 327
 328 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
 329 {
 330         unsigned long flags;
 331         int action, cpu = irq - IPI0_IRQ;
 332
 333         spin_lock_irqsave(&ipi_lock, flags);
 334         action = __this_cpu_read(ipi_action_mask);
 335         per_cpu(ipi_action_mask, cpu) = 0;
 336         clear_c0_cause(cpu ? C_SW1 : C_SW0);
 337         spin_unlock_irqrestore(&ipi_lock, flags);
 338
 339         if (action & SMP_RESCHEDULE_YOURSELF)
 340                 scheduler_ipi();
 341         if (action & SMP_CALL_FUNCTION)
 342                 generic_smp_call_function_interrupt();
 343
 344         return IRQ_HANDLED;
 345 }
 346
 347 static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
 348         unsigned int action)
 349 {
 350         unsigned int i;
 351
 352         for_each_cpu(i, mask)
 353                 bmips43xx_send_ipi_single(i, action);
 354 }
 355
 356 #ifdef CONFIG_HOTPLUG_CPU
 357
 358 static int bmips_cpu_disable(void)
 359 {
 360         unsigned int cpu = smp_processor_id();
 361
 362         if (cpu == 0)
 363                 return -EBUSY;
 364
 365         pr_info("SMP: CPU%d is offline\n", cpu);
 366
 367         set_cpu_online(cpu, false);
 368         calculate_cpu_foreign_map();
 369         cpumask_clear_cpu(cpu, &cpu_callin_map);
 370         clear_c0_status(IE_IRQ5);
 371
 372         local_flush_tlb_all();
 373         local_flush_icache_range(0, ~0);
 374
 375         return 0;
 376 }
 377
 378 static void bmips_cpu_die(unsigned int cpu)
 379 {
 380 }
 381
 382 void __ref play_dead(void)
 383 {
 384         idle_task_exit();
 385
 386         /* flush data cache */
 387         _dma_cache_wback_inv(0, ~0);
 388
 389         /*
 390          * Wakeup is on SW0 or SW1; disable everything else
 391          * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
 392          * IRQ handlers; this clears ST0_IE and returns immediately.
 393          */
 394         clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
 395         change_c0_status(
 396                 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
 397                 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
 398         irq_disable_hazard();
 399
 400         /*
 401          * wait for SW interrupt from bmips_boot_secondary(), then jump
 402          * back to start_secondary()
 403          */
 404         __asm__ __volatile__(
 405         "       wait\n"
 406         "       j       bmips_secondary_reentry\n"
 407         : : : "memory");
 408 }
 409
 410 #endif /* CONFIG_HOTPLUG_CPU */
 411
 412 struct plat_smp_ops bmips43xx_smp_ops = {
 413         .smp_setup              = bmips_smp_setup,
 414         .prepare_cpus           = bmips_prepare_cpus,
 415         .boot_secondary         = bmips_boot_secondary,
 416         .smp_finish             = bmips_smp_finish,
 417         .init_secondary         = bmips_init_secondary,
 418         .send_ipi_single        = bmips43xx_send_ipi_single,
 419         .send_ipi_mask          = bmips43xx_send_ipi_mask,
 420 #ifdef CONFIG_HOTPLUG_CPU
 421         .cpu_disable            = bmips_cpu_disable,
 422         .cpu_die                = bmips_cpu_die,
 423 #endif
 424 };
 425
 426 struct plat_smp_ops bmips5000_smp_ops = {
 427         .smp_setup              = bmips_smp_setup,
 428         .prepare_cpus           = bmips_prepare_cpus,
 429         .boot_secondary         = bmips_boot_secondary,
 430         .smp_finish             = bmips_smp_finish,
 431         .init_secondary         = bmips_init_secondary,
 432         .send_ipi_single        = bmips5000_send_ipi_single,
 433         .send_ipi_mask          = bmips5000_send_ipi_mask,
 434 #ifdef CONFIG_HOTPLUG_CPU
 435         .cpu_disable            = bmips_cpu_disable,
 436         .cpu_die                = bmips_cpu_die,
 437 #endif
 438 };
 439
 440 #endif /* CONFIG_SMP */
 441
 442 /***********************************************************************
 443  * BMIPS vector relocation
 444  * This is primarily used for SMP boot, but it is applicable to some
 445  * UP BMIPS systems as well.
 446  ***********************************************************************/
 447
 448 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
 449 {
 450         memcpy((void *)dst, start, end - start);
 451         dma_cache_wback(dst, end - start);
 452         local_flush_icache_range(dst, dst + (end - start));
 453         instruction_hazard();
 454 }
 455
 456 static inline void bmips_nmi_handler_setup(void)
 457 {
 458         bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec,
 459                 bmips_reset_nmi_vec_end);
 460         bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec,
 461                 bmips_smp_int_vec_end);
 462 }
 463
 464 struct reset_vec_info {
 465         int cpu;
 466         u32 val;
 467 };
 468
 469 static void bmips_set_reset_vec_remote(void *vinfo)
 470 {
 471         struct reset_vec_info *info = vinfo;
 472         int shift = info->cpu & 0x01 ? 16 : 0;
 473         u32 mask = ~(0xffff << shift), val = info->val >> 16;
 474
 475         preempt_disable();
 476         if (smp_processor_id() > 0) {
 477                 smp_call_function_single(0, &bmips_set_reset_vec_remote,
 478                                          info, 1);
 479         } else {
 480                 if (info->cpu & 0x02) {
 481                         /* BMIPS5200 "should" use mask/shift, but it's buggy */
 482                         bmips_write_zscm_reg(0xa0, (val << 16) | val);
 483                         bmips_read_zscm_reg(0xa0);
 484                 } else {
 485                         write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
 486                                               (val << shift));
 487                 }
 488         }
 489         preempt_enable();
 490 }
 491
 492 static void bmips_set_reset_vec(int cpu, u32 val)
 493 {
 494         struct reset_vec_info info;
 495
 496         if (current_cpu_type() == CPU_BMIPS5000) {
 497                 /* this needs to run from CPU0 (which is always online) */
 498                 info.cpu = cpu;
 499                 info.val = val;
 500                 bmips_set_reset_vec_remote(&info);
 501         } else {
 502                 void __iomem *cbr = BMIPS_GET_CBR();
 503
 504                 if (cpu == 0)
 505                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
 506                 else {
 507                         if (current_cpu_type() != CPU_BMIPS4380)
 508                                 return;
 509                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
 510                 }
 511         }
 512         __sync();
 513         back_to_back_c0_hazard();
 514 }
 515
 516 void bmips_ebase_setup(void)
 517 {
 518         unsigned long new_ebase = ebase;
 519
 520         BUG_ON(ebase != CKSEG0);
 521
 522         switch (current_cpu_type()) {
 523         case CPU_BMIPS4350:
 524                 /*
 525                  * BMIPS4350 cannot relocate the normal vectors, but it
 526                  * can relocate the BEV=1 vectors.  So CPU1 starts up at
 527                  * the relocated BEV=1, IV=0 general exception vector @
 528                  * 0xa000_0380.
 529                  *
 530                  * set_uncached_handler() is used here because:
 531                  *  - CPU1 will run this from uncached space
 532                  *  - None of the cacheflush functions are set up yet
 533                  */
 534                 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
 535                         &bmips_smp_int_vec, 0x80);
 536                 __sync();
 537                 return;
 538         case CPU_BMIPS3300:
 539         case CPU_BMIPS4380:
 540                 /*
 541                  * 0x8000_0000: reset/NMI (initially in kseg1)
 542                  * 0x8000_0400: normal vectors
 543                  */
 544                 new_ebase = 0x80000400;
 545                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 546                 break;
 547         case CPU_BMIPS5000:
 548                 /*
 549                  * 0x8000_0000: reset/NMI (initially in kseg1)
 550                  * 0x8000_1000: normal vectors
 551                  */
 552                 new_ebase = 0x80001000;
 553                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 554                 write_c0_ebase(new_ebase);
 555                 break;
 556         default:
 557                 return;
 558         }
 559
 560         board_nmi_handler_setup = &bmips_nmi_handler_setup;
 561         ebase = new_ebase;
 562 }
 563
 564 asmlinkage void __weak plat_wired_tlb_setup(void)
 565 {
 566         /*
 567          * Called when starting/restarting a secondary CPU.
 568          * Kernel stacks and other important data might only be accessible
 569          * once the wired entries are present.
 570          */
 571 }
 572
 573 void __init bmips_cpu_setup(void)
 574 {
 575         void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
 576         u32 __maybe_unused cfg;
 577
 578         switch (current_cpu_type()) {
 579         case CPU_BMIPS3300:
 580                 /* Set BIU to async mode */
 581                 set_c0_brcm_bus_pll(BIT(22));
 582                 __sync();
 583
 584                 /* put the BIU back in sync mode */
 585                 clear_c0_brcm_bus_pll(BIT(22));
 586
 587                 /* clear BHTD to enable branch history table */
 588                 clear_c0_brcm_reset(BIT(16));
 589
 590                 /* Flush and enable RAC */
 591                 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
 592                 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
 593                 __raw_readl(cbr + BMIPS_RAC_CONFIG);
 594
 595                 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
 596                 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);
 597                 __raw_readl(cbr + BMIPS_RAC_CONFIG);
 598
 599                 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 600                 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
 601                 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 602                 break;
 603
 604         case CPU_BMIPS4380:
 605                 /* CBG workaround for early BMIPS4380 CPUs */
 606                 switch (read_c0_prid()) {
 607                 case 0x2a040:
 608                 case 0x2a042:
 609                 case 0x2a044:
 610                 case 0x2a060:
 611                         cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
 612                         __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
 613                         __raw_readl(cbr + BMIPS_L2_CONFIG);
 614                 }
 615
 616                 /* clear BHTD to enable branch history table */
 617                 clear_c0_brcm_config_0(BIT(21));
 618
 619                 /* XI/ROTR enable */
 620                 set_c0_brcm_config_0(BIT(23));
 621                 set_c0_brcm_cmt_ctrl(BIT(15));
 622                 break;
 623
 624         case CPU_BMIPS5000:
 625                 /* enable RDHWR, BRDHWR */
 626                 set_c0_brcm_config(BIT(17) | BIT(21));
 627
 628                 /* Disable JTB */
 629                 __asm__ __volatile__(
 630                 "       .set    noreorder\n"
 631                 "       li      $8, 0x5a455048\n"
 632                 "       .word   0x4088b00f\n"   /* mtc0 t0, $22, 15 */
 633                 "       .word   0x4008b008\n"   /* mfc0 t0, $22, 8 */
 634                 "       li      $9, 0x00008000\n"
 635                 "       or      $8, $8, $9\n"
 636                 "       .word   0x4088b008\n"   /* mtc0 t0, $22, 8 */
 637                 "       sync\n"
 638                 "       li      $8, 0x0\n"
 639                 "       .word   0x4088b00f\n"   /* mtc0 t0, $22, 15 */
 640                 "       .set    reorder\n"
 641                 : : : "$8", "$9");
 642
 643                 /* XI enable */
 644                 set_c0_brcm_config(BIT(27));
 645
 646                 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
 647                 __asm__ __volatile__(
 648                 "       li      $8, 0x5a455048\n"
 649                 "       .word   0x4088b00f\n"   /* mtc0 $8, $22, 15 */
 650                 "       nop; nop; nop\n"
 651                 "       .word   0x4008b008\n"   /* mfc0 $8, $22, 8 */
 652                 "       lui     $9, 0x0100\n"
 653                 "       or      $8, $9\n"
 654                 "       .word   0x4088b008\n"   /* mtc0 $8, $22, 8 */
 655                 : : : "$8", "$9");
 656                 break;
 657         }
 658 }