arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/cpu_pm.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/init.h>
  13 #include <linux/highmem.h>
  14 #include <linux/kernel.h>
  15 #include <linux/linkage.h>
  16 #include <linux/preempt.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/bitops.h>
  22
  23 #include <asm/bcache.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/cache.h>
  26 #include <asm/cacheops.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpu-features.h>
  29 #include <asm/cpu-type.h>
  30 #include <asm/io.h>
  31 #include <asm/page.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/r4kcache.h>
  34 #include <asm/sections.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/war.h>
  37 #include <asm/cacheflush.h> /* for run_uncached() */
  38 #include <asm/traps.h>
  39 #include <asm/dma-coherence.h>
  40 #include <asm/mips-cm.h>
  41
  42 /*
  43  * Special Variant of smp_call_function for use by cache functions:
  44  *
  45  *  o No return value
  46  *  o collapses to normal function call on UP kernels
  47  *  o collapses to normal function call on systems with a single shared
  48  *    primary cache.
  49  *  o doesn't disable interrupts on the local CPU
  50  */
  51 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
  52 {
  53         preempt_disable();
  54
  55         /*
  56          * The Coherent Manager propagates address-based cache ops to other
  57          * cores but not index-based ops. However, r4k_on_each_cpu is used
  58          * in both cases so there is no easy way to tell what kind of op is
  59          * executed to the other cores. The best we can probably do is
  60          * to restrict that call when a CM is not present because both
  61          * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops.
  62          */
  63         if (!mips_cm_present())
  64                 smp_call_function_many(&cpu_foreign_map, func, info, 1);
  65         func(info);
  66         preempt_enable();
  67 }
  68
  69 #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
  70 #define cpu_has_safe_index_cacheops 0
  71 #else
  72 #define cpu_has_safe_index_cacheops 1
  73 #endif
  74
  75 /*
  76  * Must die.
  77  */
  78 static unsigned long icache_size __read_mostly;
  79 static unsigned long dcache_size __read_mostly;
  80 static unsigned long scache_size __read_mostly;
  81
  82 /*
  83  * Dummy cache handling routines for machines without boardcaches
  84  */
  85 static void cache_noop(void) {}
  86
  87 static struct bcache_ops no_sc_ops = {
  88         .bc_enable = (void *)cache_noop,
  89         .bc_disable = (void *)cache_noop,
  90         .bc_wback_inv = (void *)cache_noop,
  91         .bc_inv = (void *)cache_noop
  92 };
  93
  94 struct bcache_ops *bcops = &no_sc_ops;
  95
  96 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  97 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  98
  99 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
 100 do {                                                                    \
 101         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
 102                 *(volatile unsigned long *)CKSEG1;                      \
 103         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
 104                 __asm__ __volatile__("nop;nop;nop;nop");                \
 105 } while (0)
 106
 107 static void (*r4k_blast_dcache_page)(unsigned long addr);
 108
 109 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 110 {
 111         R4600_HIT_CACHEOP_WAR_IMPL;
 112         blast_dcache32_page(addr);
 113 }
 114
 115 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 116 {
 117         blast_dcache64_page(addr);
 118 }
 119
 120 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
 121 {
 122         blast_dcache128_page(addr);
 123 }
 124
 125 static void r4k_blast_dcache_page_setup(void)
 126 {
 127         unsigned long  dc_lsize = cpu_dcache_line_size();
 128
 129         switch (dc_lsize) {
 130         case 0:
 131                 r4k_blast_dcache_page = (void *)cache_noop;
 132                 break;
 133         case 16:
 134                 r4k_blast_dcache_page = blast_dcache16_page;
 135                 break;
 136         case 32:
 137                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 138                 break;
 139         case 64:
 140                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 141                 break;
 142         case 128:
 143                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
 144                 break;
 145         default:
 146                 break;
 147         }
 148 }
 149
 150 #ifndef CONFIG_EVA
 151 #define r4k_blast_dcache_user_page  r4k_blast_dcache_page
 152 #else
 153
 154 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
 155
 156 static void r4k_blast_dcache_user_page_setup(void)
 157 {
 158         unsigned long  dc_lsize = cpu_dcache_line_size();
 159
 160         if (dc_lsize == 0)
 161                 r4k_blast_dcache_user_page = (void *)cache_noop;
 162         else if (dc_lsize == 16)
 163                 r4k_blast_dcache_user_page = blast_dcache16_user_page;
 164         else if (dc_lsize == 32)
 165                 r4k_blast_dcache_user_page = blast_dcache32_user_page;
 166         else if (dc_lsize == 64)
 167                 r4k_blast_dcache_user_page = blast_dcache64_user_page;
 168 }
 169
 170 #endif
 171
 172 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 173
 174 static void r4k_blast_dcache_page_indexed_setup(void)
 175 {
 176         unsigned long dc_lsize = cpu_dcache_line_size();
 177
 178         if (dc_lsize == 0)
 179                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 180         else if (dc_lsize == 16)
 181                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 182         else if (dc_lsize == 32)
 183                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 184         else if (dc_lsize == 64)
 185                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 186         else if (dc_lsize == 128)
 187                 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
 188 }
 189
 190 void (* r4k_blast_dcache)(void);
 191 EXPORT_SYMBOL(r4k_blast_dcache);
 192
 193 static void r4k_blast_dcache_setup(void)
 194 {
 195         unsigned long dc_lsize = cpu_dcache_line_size();
 196
 197         if (dc_lsize == 0)
 198                 r4k_blast_dcache = (void *)cache_noop;
 199         else if (dc_lsize == 16)
 200                 r4k_blast_dcache = blast_dcache16;
 201         else if (dc_lsize == 32)
 202                 r4k_blast_dcache = blast_dcache32;
 203         else if (dc_lsize == 64)
 204                 r4k_blast_dcache = blast_dcache64;
 205         else if (dc_lsize == 128)
 206                 r4k_blast_dcache = blast_dcache128;
 207 }
 208
 209 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 210 #define JUMP_TO_ALIGN(order) \
 211         __asm__ __volatile__( \
 212                 "b\t1f\n\t" \
 213                 ".align\t" #order "\n\t" \
 214                 "1:\n\t" \
 215                 )
 216 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 217 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 218
 219 static inline void blast_r4600_v1_icache32(void)
 220 {
 221         unsigned long flags;
 222
 223         local_irq_save(flags);
 224         blast_icache32();
 225         local_irq_restore(flags);
 226 }
 227
 228 static inline void tx49_blast_icache32(void)
 229 {
 230         unsigned long start = INDEX_BASE;
 231         unsigned long end = start + current_cpu_data.icache.waysize;
 232         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 233         unsigned long ws_end = current_cpu_data.icache.ways <<
 234                                current_cpu_data.icache.waybit;
 235         unsigned long ws, addr;
 236
 237         CACHE32_UNROLL32_ALIGN2;
 238         /* I'm in even chunk.  blast odd chunks */
 239         for (ws = 0; ws < ws_end; ws += ws_inc)
 240                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 241                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 242         CACHE32_UNROLL32_ALIGN;
 243         /* I'm in odd chunk.  blast even chunks */
 244         for (ws = 0; ws < ws_end; ws += ws_inc)
 245                 for (addr = start; addr < end; addr += 0x400 * 2)
 246                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 247 }
 248
 249 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 250 {
 251         unsigned long flags;
 252
 253         local_irq_save(flags);
 254         blast_icache32_page_indexed(page);
 255         local_irq_restore(flags);
 256 }
 257
 258 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 259 {
 260         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 261         unsigned long start = INDEX_BASE + (page & indexmask);
 262         unsigned long end = start + PAGE_SIZE;
 263         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 264         unsigned long ws_end = current_cpu_data.icache.ways <<
 265                                current_cpu_data.icache.waybit;
 266         unsigned long ws, addr;
 267
 268         CACHE32_UNROLL32_ALIGN2;
 269         /* I'm in even chunk.  blast odd chunks */
 270         for (ws = 0; ws < ws_end; ws += ws_inc)
 271                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 272                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 273         CACHE32_UNROLL32_ALIGN;
 274         /* I'm in odd chunk.  blast even chunks */
 275         for (ws = 0; ws < ws_end; ws += ws_inc)
 276                 for (addr = start; addr < end; addr += 0x400 * 2)
 277                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 278 }
 279
 280 static void (* r4k_blast_icache_page)(unsigned long addr);
 281
 282 static void r4k_blast_icache_page_setup(void)
 283 {
 284         unsigned long ic_lsize = cpu_icache_line_size();
 285
 286         if (ic_lsize == 0)
 287                 r4k_blast_icache_page = (void *)cache_noop;
 288         else if (ic_lsize == 16)
 289                 r4k_blast_icache_page = blast_icache16_page;
 290         else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
 291                 r4k_blast_icache_page = loongson2_blast_icache32_page;
 292         else if (ic_lsize == 32)
 293                 r4k_blast_icache_page = blast_icache32_page;
 294         else if (ic_lsize == 64)
 295                 r4k_blast_icache_page = blast_icache64_page;
 296         else if (ic_lsize == 128)
 297                 r4k_blast_icache_page = blast_icache128_page;
 298 }
 299
 300 #ifndef CONFIG_EVA
 301 #define r4k_blast_icache_user_page  r4k_blast_icache_page
 302 #else
 303
 304 static void (*r4k_blast_icache_user_page)(unsigned long addr);
 305
 306 static void r4k_blast_icache_user_page_setup(void)
 307 {
 308         unsigned long ic_lsize = cpu_icache_line_size();
 309
 310         if (ic_lsize == 0)
 311                 r4k_blast_icache_user_page = (void *)cache_noop;
 312         else if (ic_lsize == 16)
 313                 r4k_blast_icache_user_page = blast_icache16_user_page;
 314         else if (ic_lsize == 32)
 315                 r4k_blast_icache_user_page = blast_icache32_user_page;
 316         else if (ic_lsize == 64)
 317                 r4k_blast_icache_user_page = blast_icache64_user_page;
 318 }
 319
 320 #endif
 321
 322 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 323
 324 static void r4k_blast_icache_page_indexed_setup(void)
 325 {
 326         unsigned long ic_lsize = cpu_icache_line_size();
 327
 328         if (ic_lsize == 0)
 329                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 330         else if (ic_lsize == 16)
 331                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 332         else if (ic_lsize == 32) {
 333                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 334                         r4k_blast_icache_page_indexed =
 335                                 blast_icache32_r4600_v1_page_indexed;
 336                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 337                         r4k_blast_icache_page_indexed =
 338                                 tx49_blast_icache32_page_indexed;
 339                 else if (current_cpu_type() == CPU_LOONGSON2)
 340                         r4k_blast_icache_page_indexed =
 341                                 loongson2_blast_icache32_page_indexed;
 342                 else
 343                         r4k_blast_icache_page_indexed =
 344                                 blast_icache32_page_indexed;
 345         } else if (ic_lsize == 64)
 346                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 347 }
 348
 349 void (* r4k_blast_icache)(void);
 350 EXPORT_SYMBOL(r4k_blast_icache);
 351
 352 static void r4k_blast_icache_setup(void)
 353 {
 354         unsigned long ic_lsize = cpu_icache_line_size();
 355
 356         if (ic_lsize == 0)
 357                 r4k_blast_icache = (void *)cache_noop;
 358         else if (ic_lsize == 16)
 359                 r4k_blast_icache = blast_icache16;
 360         else if (ic_lsize == 32) {
 361                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 362                         r4k_blast_icache = blast_r4600_v1_icache32;
 363                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 364                         r4k_blast_icache = tx49_blast_icache32;
 365                 else if (current_cpu_type() == CPU_LOONGSON2)
 366                         r4k_blast_icache = loongson2_blast_icache32;
 367                 else
 368                         r4k_blast_icache = blast_icache32;
 369         } else if (ic_lsize == 64)
 370                 r4k_blast_icache = blast_icache64;
 371         else if (ic_lsize == 128)
 372                 r4k_blast_icache = blast_icache128;
 373 }
 374
 375 static void (* r4k_blast_scache_page)(unsigned long addr);
 376
 377 static void r4k_blast_scache_page_setup(void)
 378 {
 379         unsigned long sc_lsize = cpu_scache_line_size();
 380
 381         if (scache_size == 0)
 382                 r4k_blast_scache_page = (void *)cache_noop;
 383         else if (sc_lsize == 16)
 384                 r4k_blast_scache_page = blast_scache16_page;
 385         else if (sc_lsize == 32)
 386                 r4k_blast_scache_page = blast_scache32_page;
 387         else if (sc_lsize == 64)
 388                 r4k_blast_scache_page = blast_scache64_page;
 389         else if (sc_lsize == 128)
 390                 r4k_blast_scache_page = blast_scache128_page;
 391 }
 392
 393 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 394
 395 static void r4k_blast_scache_page_indexed_setup(void)
 396 {
 397         unsigned long sc_lsize = cpu_scache_line_size();
 398
 399         if (scache_size == 0)
 400                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 401         else if (sc_lsize == 16)
 402                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 403         else if (sc_lsize == 32)
 404                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 405         else if (sc_lsize == 64)
 406                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 407         else if (sc_lsize == 128)
 408                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 409 }
 410
 411 static void (* r4k_blast_scache)(void);
 412
 413 static void r4k_blast_scache_setup(void)
 414 {
 415         unsigned long sc_lsize = cpu_scache_line_size();
 416
 417         if (scache_size == 0)
 418                 r4k_blast_scache = (void *)cache_noop;
 419         else if (sc_lsize == 16)
 420                 r4k_blast_scache = blast_scache16;
 421         else if (sc_lsize == 32)
 422                 r4k_blast_scache = blast_scache32;
 423         else if (sc_lsize == 64)
 424                 r4k_blast_scache = blast_scache64;
 425         else if (sc_lsize == 128)
 426                 r4k_blast_scache = blast_scache128;
 427 }
 428
 429 static inline void local_r4k___flush_cache_all(void * args)
 430 {
 431         switch (current_cpu_type()) {
 432         case CPU_LOONGSON2:
 433         case CPU_LOONGSON3:
 434         case CPU_R4000SC:
 435         case CPU_R4000MC:
 436         case CPU_R4400SC:
 437         case CPU_R4400MC:
 438         case CPU_R10000:
 439         case CPU_R12000:
 440         case CPU_R14000:
 441         case CPU_R16000:
 442                 /*
 443                  * These caches are inclusive caches, that is, if something
 444                  * is not cached in the S-cache, we know it also won't be
 445                  * in one of the primary caches.
 446                  */
 447                 r4k_blast_scache();
 448                 break;
 449
 450         case CPU_BMIPS5000:
 451                 r4k_blast_scache();
 452                 __sync();
 453                 break;
 454
 455         default:
 456                 r4k_blast_dcache();
 457                 r4k_blast_icache();
 458                 break;
 459         }
 460 }
 461
 462 static void r4k___flush_cache_all(void)
 463 {
 464         r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
 465 }
 466
 467 static inline int has_valid_asid(const struct mm_struct *mm)
 468 {
 469 #ifdef CONFIG_MIPS_MT_SMP
 470         int i;
 471
 472         for_each_online_cpu(i)
 473                 if (cpu_context(i, mm))
 474                         return 1;
 475
 476         return 0;
 477 #else
 478         return cpu_context(smp_processor_id(), mm);
 479 #endif
 480 }
 481
 482 static void r4k__flush_cache_vmap(void)
 483 {
 484         r4k_blast_dcache();
 485 }
 486
 487 static void r4k__flush_cache_vunmap(void)
 488 {
 489         r4k_blast_dcache();
 490 }
 491
 492 static inline void local_r4k_flush_cache_range(void * args)
 493 {
 494         struct vm_area_struct *vma = args;
 495         int exec = vma->vm_flags & VM_EXEC;
 496
 497         if (!(has_valid_asid(vma->vm_mm)))
 498                 return;
 499
 500         r4k_blast_dcache();
 501         if (exec)
 502                 r4k_blast_icache();
 503 }
 504
 505 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 506         unsigned long start, unsigned long end)
 507 {
 508         int exec = vma->vm_flags & VM_EXEC;
 509
 510         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 511                 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
 512 }
 513
 514 static inline void local_r4k_flush_cache_mm(void * args)
 515 {
 516         struct mm_struct *mm = args;
 517
 518         if (!has_valid_asid(mm))
 519                 return;
 520
 521         /*
 522          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 523          * only flush the primary caches but R1x000 behave sane ...
 524          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 525          * caches, so we can bail out early.
 526          */
 527         if (current_cpu_type() == CPU_R4000SC ||
 528             current_cpu_type() == CPU_R4000MC ||
 529             current_cpu_type() == CPU_R4400SC ||
 530             current_cpu_type() == CPU_R4400MC) {
 531                 r4k_blast_scache();
 532                 return;
 533         }
 534
 535         r4k_blast_dcache();
 536 }
 537
 538 static void r4k_flush_cache_mm(struct mm_struct *mm)
 539 {
 540         if (!cpu_has_dc_aliases)
 541                 return;
 542
 543         r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
 544 }
 545
 546 struct flush_cache_page_args {
 547         struct vm_area_struct *vma;
 548         unsigned long addr;
 549         unsigned long pfn;
 550 };
 551
 552 static inline void local_r4k_flush_cache_page(void *args)
 553 {
 554         struct flush_cache_page_args *fcp_args = args;
 555         struct vm_area_struct *vma = fcp_args->vma;
 556         unsigned long addr = fcp_args->addr;
 557         struct page *page = pfn_to_page(fcp_args->pfn);
 558         int exec = vma->vm_flags & VM_EXEC;
 559         struct mm_struct *mm = vma->vm_mm;
 560         int map_coherent = 0;
 561         pgd_t *pgdp;
 562         pud_t *pudp;
 563         pmd_t *pmdp;
 564         pte_t *ptep;
 565         void *vaddr;
 566
 567         /*
 568          * If ownes no valid ASID yet, cannot possibly have gotten
 569          * this page into the cache.
 570          */
 571         if (!has_valid_asid(mm))
 572                 return;
 573
 574         addr &= PAGE_MASK;
 575         pgdp = pgd_offset(mm, addr);
 576         pudp = pud_offset(pgdp, addr);
 577         pmdp = pmd_offset(pudp, addr);
 578         ptep = pte_offset(pmdp, addr);
 579
 580         /*
 581          * If the page isn't marked valid, the page cannot possibly be
 582          * in the cache.
 583          */
 584         if (!(pte_present(*ptep)))
 585                 return;
 586
 587         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 588                 vaddr = NULL;
 589         else {
 590                 /*
 591                  * Use kmap_coherent or kmap_atomic to do flushes for
 592                  * another ASID than the current one.
 593                  */
 594                 map_coherent = (cpu_has_dc_aliases &&
 595                                 page_mapped(page) && !Page_dcache_dirty(page));
 596                 if (map_coherent)
 597                         vaddr = kmap_coherent(page, addr);
 598                 else
 599                         vaddr = kmap_atomic(page);
 600                 addr = (unsigned long)vaddr;
 601         }
 602
 603         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 604                 vaddr ? r4k_blast_dcache_page(addr) :
 605                         r4k_blast_dcache_user_page(addr);
 606                 if (exec && !cpu_icache_snoops_remote_store)
 607                         r4k_blast_scache_page(addr);
 608         }
 609         if (exec) {
 610                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 611                         int cpu = smp_processor_id();
 612
 613                         if (cpu_context(cpu, mm) != 0)
 614                                 drop_mmu_context(mm, cpu);
 615                 } else
 616                         vaddr ? r4k_blast_icache_page(addr) :
 617                                 r4k_blast_icache_user_page(addr);
 618         }
 619
 620         if (vaddr) {
 621                 if (map_coherent)
 622                         kunmap_coherent();
 623                 else
 624                         kunmap_atomic(vaddr);
 625         }
 626 }
 627
 628 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 629         unsigned long addr, unsigned long pfn)
 630 {
 631         struct flush_cache_page_args args;
 632
 633         args.vma = vma;
 634         args.addr = addr;
 635         args.pfn = pfn;
 636
 637         r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
 638 }
 639
 640 static inline void local_r4k_flush_data_cache_page(void * addr)
 641 {
 642         r4k_blast_dcache_page((unsigned long) addr);
 643 }
 644
 645 static void r4k_flush_data_cache_page(unsigned long addr)
 646 {
 647         if (in_atomic())
 648                 local_r4k_flush_data_cache_page((void *)addr);
 649         else
 650                 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
 651 }
 652
 653 struct flush_icache_range_args {
 654         unsigned long start;
 655         unsigned long end;
 656 };
 657
 658 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
 659 {
 660         if (!cpu_has_ic_fills_f_dc) {
 661                 if (end - start >= dcache_size) {
 662                         r4k_blast_dcache();
 663                 } else {
 664                         R4600_HIT_CACHEOP_WAR_IMPL;
 665                         protected_blast_dcache_range(start, end);
 666                 }
 667         }
 668
 669         if (end - start > icache_size)
 670                 r4k_blast_icache();
 671         else {
 672                 switch (boot_cpu_type()) {
 673                 case CPU_LOONGSON2:
 674                         protected_loongson2_blast_icache_range(start, end);
 675                         break;
 676
 677                 default:
 678                         protected_blast_icache_range(start, end);
 679                         break;
 680                 }
 681         }
 682 #ifdef CONFIG_EVA
 683         /*
 684          * Due to all possible segment mappings, there might cache aliases
 685          * caused by the bootloader being in non-EVA mode, and the CPU switching
 686          * to EVA during early kernel init. It's best to flush the scache
 687          * to avoid having secondary cores fetching stale data and lead to
 688          * kernel crashes.
 689          */
 690         bc_wback_inv(start, (end - start));
 691         __sync();
 692 #endif
 693 }
 694
 695 static inline void local_r4k_flush_icache_range_ipi(void *args)
 696 {
 697         struct flush_icache_range_args *fir_args = args;
 698         unsigned long start = fir_args->start;
 699         unsigned long end = fir_args->end;
 700
 701         local_r4k_flush_icache_range(start, end);
 702 }
 703
 704 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 705 {
 706         struct flush_icache_range_args args;
 707
 708         args.start = start;
 709         args.end = end;
 710
 711         r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
 712         instruction_hazard();
 713 }
 714
 715 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
 716
 717 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 718 {
 719         /* Catch bad driver code */
 720         if (WARN_ON(size == 0))
 721                 return;
 722
 723         preempt_disable();
 724         if (cpu_has_inclusive_pcaches) {
 725                 if (size >= scache_size)
 726                         r4k_blast_scache();
 727                 else
 728                         blast_scache_range(addr, addr + size);
 729                 preempt_enable();
 730                 __sync();
 731                 return;
 732         }
 733
 734         /*
 735          * Either no secondary cache or the available caches don't have the
 736          * subset property so we have to flush the primary caches
 737          * explicitly
 738          */
 739         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 740                 r4k_blast_dcache();
 741         } else {
 742                 R4600_HIT_CACHEOP_WAR_IMPL;
 743                 blast_dcache_range(addr, addr + size);
 744         }
 745         preempt_enable();
 746
 747         bc_wback_inv(addr, size);
 748         __sync();
 749 }
 750
 751 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 752 {
 753         /* Catch bad driver code */
 754         if (WARN_ON(size == 0))
 755                 return;
 756
 757         preempt_disable();
 758         if (cpu_has_inclusive_pcaches) {
 759                 if (size >= scache_size)
 760                         r4k_blast_scache();
 761                 else {
 762                         /*
 763                          * There is no clearly documented alignment requirement
 764                          * for the cache instruction on MIPS processors and
 765                          * some processors, among them the RM5200 and RM7000
 766                          * QED processors will throw an address error for cache
 767                          * hit ops with insufficient alignment.  Solved by
 768                          * aligning the address to cache line size.
 769                          */
 770                         blast_inv_scache_range(addr, addr + size);
 771                 }
 772                 preempt_enable();
 773                 __sync();
 774                 return;
 775         }
 776
 777         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 778                 r4k_blast_dcache();
 779         } else {
 780                 R4600_HIT_CACHEOP_WAR_IMPL;
 781                 blast_inv_dcache_range(addr, addr + size);
 782         }
 783         preempt_enable();
 784
 785         bc_inv(addr, size);
 786         __sync();
 787 }
 788 #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
 789
 790 /*
 791  * While we're protected against bad userland addresses we don't care
 792  * very much about what happens in that case.  Usually a segmentation
 793  * fault will dump the process later on anyway ...
 794  */
 795 static void local_r4k_flush_cache_sigtramp(void * arg)
 796 {
 797         unsigned long ic_lsize = cpu_icache_line_size();
 798         unsigned long dc_lsize = cpu_dcache_line_size();
 799         unsigned long sc_lsize = cpu_scache_line_size();
 800         unsigned long addr = (unsigned long) arg;
 801
 802         R4600_HIT_CACHEOP_WAR_IMPL;
 803         if (dc_lsize)
 804                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 805         if (!cpu_icache_snoops_remote_store && scache_size)
 806                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 807         if (ic_lsize)
 808                 protected_flush_icache_line(addr & ~(ic_lsize - 1));
 809         if (MIPS4K_ICACHE_REFILL_WAR) {
 810                 __asm__ __volatile__ (
 811                         ".set push\n\t"
 812                         ".set noat\n\t"
 813                         ".set "MIPS_ISA_LEVEL"\n\t"
 814 #ifdef CONFIG_32BIT
 815                         "la     $at,1f\n\t"
 816 #endif
 817 #ifdef CONFIG_64BIT
 818                         "dla    $at,1f\n\t"
 819 #endif
 820                         "cache  %0,($at)\n\t"
 821                         "nop; nop; nop\n"
 822                         "1:\n\t"
 823                         ".set pop"
 824                         :
 825                         : "i" (Hit_Invalidate_I));
 826         }
 827         if (MIPS_CACHE_SYNC_WAR)
 828                 __asm__ __volatile__ ("sync");
 829 }
 830
 831 static void r4k_flush_cache_sigtramp(unsigned long addr)
 832 {
 833         r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
 834 }
 835
 836 static void r4k_flush_icache_all(void)
 837 {
 838         if (cpu_has_vtag_icache)
 839                 r4k_blast_icache();
 840 }
 841
 842 struct flush_kernel_vmap_range_args {
 843         unsigned long   vaddr;
 844         int             size;
 845 };
 846
 847 static inline void local_r4k_flush_kernel_vmap_range(void *args)
 848 {
 849         struct flush_kernel_vmap_range_args *vmra = args;
 850         unsigned long vaddr = vmra->vaddr;
 851         int size = vmra->size;
 852
 853         /*
 854          * Aliases only affect the primary caches so don't bother with
 855          * S-caches or T-caches.
 856          */
 857         if (cpu_has_safe_index_cacheops && size >= dcache_size)
 858                 r4k_blast_dcache();
 859         else {
 860                 R4600_HIT_CACHEOP_WAR_IMPL;
 861                 blast_dcache_range(vaddr, vaddr + size);
 862         }
 863 }
 864
 865 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
 866 {
 867         struct flush_kernel_vmap_range_args args;
 868
 869         args.vaddr = (unsigned long) vaddr;
 870         args.size = size;
 871
 872         r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
 873 }
 874
 875 static inline void rm7k_erratum31(void)
 876 {
 877         const unsigned long ic_lsize = 32;
 878         unsigned long addr;
 879
 880         /* RM7000 erratum #31. The icache is screwed at startup. */
 881         write_c0_taglo(0);
 882         write_c0_taghi(0);
 883
 884         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 885                 __asm__ __volatile__ (
 886                         ".set push\n\t"
 887                         ".set noreorder\n\t"
 888                         ".set mips3\n\t"
 889                         "cache\t%1, 0(%0)\n\t"
 890                         "cache\t%1, 0x1000(%0)\n\t"
 891                         "cache\t%1, 0x2000(%0)\n\t"
 892                         "cache\t%1, 0x3000(%0)\n\t"
 893                         "cache\t%2, 0(%0)\n\t"
 894                         "cache\t%2, 0x1000(%0)\n\t"
 895                         "cache\t%2, 0x2000(%0)\n\t"
 896                         "cache\t%2, 0x3000(%0)\n\t"
 897                         "cache\t%1, 0(%0)\n\t"
 898                         "cache\t%1, 0x1000(%0)\n\t"
 899                         "cache\t%1, 0x2000(%0)\n\t"
 900                         "cache\t%1, 0x3000(%0)\n\t"
 901                         ".set pop\n"
 902                         :
 903                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 904         }
 905 }
 906
 907 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
 908 {
 909         unsigned int imp = c->processor_id & PRID_IMP_MASK;
 910         unsigned int rev = c->processor_id & PRID_REV_MASK;
 911         int present = 0;
 912
 913         /*
 914          * Early versions of the 74K do not update the cache tags on a
 915          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
 916          * aliases.  In this case it is better to treat the cache as always
 917          * having aliases.  Also disable the synonym tag update feature
 918          * where available.  In this case no opportunistic tag update will
 919          * happen where a load causes a virtual address miss but a physical
 920          * address hit during a D-cache look-up.
 921          */
 922         switch (imp) {
 923         case PRID_IMP_74K:
 924                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
 925                         present = 1;
 926                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
 927                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 928                 break;
 929         case PRID_IMP_1074K:
 930                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
 931                         present = 1;
 932                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 933                 }
 934                 break;
 935         default:
 936                 BUG();
 937         }
 938
 939         return present;
 940 }
 941
 942 static void b5k_instruction_hazard(void)
 943 {
 944         __sync();
 945         __sync();
 946         __asm__ __volatile__(
 947         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
 948         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
 949         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
 950         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
 951         : : : "memory");
 952 }
 953
 954 static char *way_string[] = { NULL, "direct mapped", "2-way",
 955         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
 956         "9-way", "10-way", "11-way", "12-way",
 957         "13-way", "14-way", "15-way", "16-way",
 958 };
 959
 960 static void probe_pcache(void)
 961 {
 962         struct cpuinfo_mips *c = &current_cpu_data;
 963         unsigned int config = read_c0_config();
 964         unsigned int prid = read_c0_prid();
 965         int has_74k_erratum = 0;
 966         unsigned long config1;
 967         unsigned int lsize;
 968
 969         switch (current_cpu_type()) {
 970         case CPU_R4600:                 /* QED style two way caches? */
 971         case CPU_R4700:
 972         case CPU_R5000:
 973         case CPU_NEVADA:
 974                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 975                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 976                 c->icache.ways = 2;
 977                 c->icache.waybit = __ffs(icache_size/2);
 978
 979                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 980                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 981                 c->dcache.ways = 2;
 982                 c->dcache.waybit= __ffs(dcache_size/2);
 983
 984                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 985                 break;
 986
 987         case CPU_R5432:
 988         case CPU_R5500:
 989                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 990                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 991                 c->icache.ways = 2;
 992                 c->icache.waybit= 0;
 993
 994                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 995                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 996                 c->dcache.ways = 2;
 997                 c->dcache.waybit = 0;
 998
 999                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1000                 break;
1001
1002         case CPU_TX49XX:
1003                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1004                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1005                 c->icache.ways = 4;
1006                 c->icache.waybit= 0;
1007
1008                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1009                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1010                 c->dcache.ways = 4;
1011                 c->dcache.waybit = 0;
1012
1013                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1014                 c->options |= MIPS_CPU_PREFETCH;
1015                 break;
1016
1017         case CPU_R4000PC:
1018         case CPU_R4000SC:
1019         case CPU_R4000MC:
1020         case CPU_R4400PC:
1021         case CPU_R4400SC:
1022         case CPU_R4400MC:
1023         case CPU_R4300:
1024                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1025                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1026                 c->icache.ways = 1;
1027                 c->icache.waybit = 0;   /* doesn't matter */
1028
1029                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1030                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1031                 c->dcache.ways = 1;
1032                 c->dcache.waybit = 0;   /* does not matter */
1033
1034                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1035                 break;
1036
1037         case CPU_R10000:
1038         case CPU_R12000:
1039         case CPU_R14000:
1040         case CPU_R16000:
1041                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1042                 c->icache.linesz = 64;
1043                 c->icache.ways = 2;
1044                 c->icache.waybit = 0;
1045
1046                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1047                 c->dcache.linesz = 32;
1048                 c->dcache.ways = 2;
1049                 c->dcache.waybit = 0;
1050
1051                 c->options |= MIPS_CPU_PREFETCH;
1052                 break;
1053
1054         case CPU_VR4133:
1055                 write_c0_config(config & ~VR41_CONF_P4K);
1056         case CPU_VR4131:
1057                 /* Workaround for cache instruction bug of VR4131 */
1058                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1059                     c->processor_id == 0x0c82U) {
1060                         config |= 0x00400000U;
1061                         if (c->processor_id == 0x0c80U)
1062                                 config |= VR41_CONF_BP;
1063                         write_c0_config(config);
1064                 } else
1065                         c->options |= MIPS_CPU_CACHE_CDEX_P;
1066
1067                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1068                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1069                 c->icache.ways = 2;
1070                 c->icache.waybit = __ffs(icache_size/2);
1071
1072                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1073                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1074                 c->dcache.ways = 2;
1075                 c->dcache.waybit = __ffs(dcache_size/2);
1076                 break;
1077
1078         case CPU_VR41XX:
1079         case CPU_VR4111:
1080         case CPU_VR4121:
1081         case CPU_VR4122:
1082         case CPU_VR4181:
1083         case CPU_VR4181A:
1084                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1085                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1086                 c->icache.ways = 1;
1087                 c->icache.waybit = 0;   /* doesn't matter */
1088
1089                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1090                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1091                 c->dcache.ways = 1;
1092                 c->dcache.waybit = 0;   /* does not matter */
1093
1094                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1095                 break;
1096
1097         case CPU_RM7000:
1098                 rm7k_erratum31();
1099
1100                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1101                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1102                 c->icache.ways = 4;
1103                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1104
1105                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1106                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1107                 c->dcache.ways = 4;
1108                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1109
1110                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1111                 c->options |= MIPS_CPU_PREFETCH;
1112                 break;
1113
1114         case CPU_LOONGSON2:
1115                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1116                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1117                 if (prid & 0x3)
1118                         c->icache.ways = 4;
1119                 else
1120                         c->icache.ways = 2;
1121                 c->icache.waybit = 0;
1122
1123                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1124                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1125                 if (prid & 0x3)
1126                         c->dcache.ways = 4;
1127                 else
1128                         c->dcache.ways = 2;
1129                 c->dcache.waybit = 0;
1130                 break;
1131
1132         case CPU_LOONGSON3:
1133                 config1 = read_c0_config1();
1134                 lsize = (config1 >> 19) & 7;
1135                 if (lsize)
1136                         c->icache.linesz = 2 << lsize;
1137                 else
1138                         c->icache.linesz = 0;
1139                 c->icache.sets = 64 << ((config1 >> 22) & 7);
1140                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1141                 icache_size = c->icache.sets *
1142                                           c->icache.ways *
1143                                           c->icache.linesz;
1144                 c->icache.waybit = 0;
1145
1146                 lsize = (config1 >> 10) & 7;
1147                 if (lsize)
1148                         c->dcache.linesz = 2 << lsize;
1149                 else
1150                         c->dcache.linesz = 0;
1151                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1152                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1153                 dcache_size = c->dcache.sets *
1154                                           c->dcache.ways *
1155                                           c->dcache.linesz;
1156                 c->dcache.waybit = 0;
1157                 break;
1158
1159         case CPU_CAVIUM_OCTEON3:
1160                 /* For now lie about the number of ways. */
1161                 c->icache.linesz = 128;
1162                 c->icache.sets = 16;
1163                 c->icache.ways = 8;
1164                 c->icache.flags |= MIPS_CACHE_VTAG;
1165                 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1166
1167                 c->dcache.linesz = 128;
1168                 c->dcache.ways = 8;
1169                 c->dcache.sets = 8;
1170                 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1171                 c->options |= MIPS_CPU_PREFETCH;
1172                 break;
1173
1174         default:
1175                 if (!(config & MIPS_CONF_M))
1176                         panic("Don't know how to probe P-caches on this cpu.");
1177
1178                 /*
1179                  * So we seem to be a MIPS32 or MIPS64 CPU
1180                  * So let's probe the I-cache ...
1181                  */
1182                 config1 = read_c0_config1();
1183
1184                 lsize = (config1 >> 19) & 7;
1185
1186                 /* IL == 7 is reserved */
1187                 if (lsize == 7)
1188                         panic("Invalid icache line size");
1189
1190                 c->icache.linesz = lsize ? 2 << lsize : 0;
1191
1192                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1193                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1194
1195                 icache_size = c->icache.sets *
1196                               c->icache.ways *
1197                               c->icache.linesz;
1198                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1199
1200                 if (config & 0x8)               /* VI bit */
1201                         c->icache.flags |= MIPS_CACHE_VTAG;
1202
1203                 /*
1204                  * Now probe the MIPS32 / MIPS64 data cache.
1205                  */
1206                 c->dcache.flags = 0;
1207
1208                 lsize = (config1 >> 10) & 7;
1209
1210                 /* DL == 7 is reserved */
1211                 if (lsize == 7)
1212                         panic("Invalid dcache line size");
1213
1214                 c->dcache.linesz = lsize ? 2 << lsize : 0;
1215
1216                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1217                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1218
1219                 dcache_size = c->dcache.sets *
1220                               c->dcache.ways *
1221                               c->dcache.linesz;
1222                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1223
1224                 c->options |= MIPS_CPU_PREFETCH;
1225                 break;
1226         }
1227
1228         /*
1229          * Processor configuration sanity check for the R4000SC erratum
1230          * #5.  With page sizes larger than 32kB there is no possibility
1231          * to get a VCE exception anymore so we don't care about this
1232          * misconfiguration.  The case is rather theoretical anyway;
1233          * presumably no vendor is shipping his hardware in the "bad"
1234          * configuration.
1235          */
1236         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1237             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1238             !(config & CONF_SC) && c->icache.linesz != 16 &&
1239             PAGE_SIZE <= 0x8000)
1240                 panic("Improper R4000SC processor configuration detected");
1241
1242         /* compute a couple of other cache variables */
1243         c->icache.waysize = icache_size / c->icache.ways;
1244         c->dcache.waysize = dcache_size / c->dcache.ways;
1245
1246         c->icache.sets = c->icache.linesz ?
1247                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1248         c->dcache.sets = c->dcache.linesz ?
1249                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1250
1251         /*
1252          * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way
1253          * virtually indexed so normally would suffer from aliases.  So
1254          * normally they'd suffer from aliases but magic in the hardware deals
1255          * with that for us so we don't need to take care ourselves.
1256          */
1257         switch (current_cpu_type()) {
1258         case CPU_20KC:
1259         case CPU_25KF:
1260         case CPU_SB1:
1261         case CPU_SB1A:
1262         case CPU_XLR:
1263                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1264                 break;
1265
1266         case CPU_R10000:
1267         case CPU_R12000:
1268         case CPU_R14000:
1269         case CPU_R16000:
1270                 break;
1271
1272         case CPU_74K:
1273         case CPU_1074K:
1274                 has_74k_erratum = alias_74k_erratum(c);
1275                 /* Fall through. */
1276         case CPU_M14KC:
1277         case CPU_M14KEC:
1278         case CPU_24K:
1279         case CPU_34K:
1280         case CPU_1004K:
1281         case CPU_INTERAPTIV:
1282         case CPU_P5600:
1283         case CPU_PROAPTIV:
1284         case CPU_M5150:
1285         case CPU_QEMU_GENERIC:
1286         case CPU_I6400:
1287                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1288                     (c->icache.waysize > PAGE_SIZE))
1289                         c->icache.flags |= MIPS_CACHE_ALIASES;
1290                 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1291                         /*
1292                          * Effectively physically indexed dcache,
1293                          * thus no virtual aliases.
1294                         */
1295                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1296                         break;
1297                 }
1298         default:
1299                 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1300                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1301         }
1302
1303         switch (current_cpu_type()) {
1304         case CPU_20KC:
1305                 /*
1306                  * Some older 20Kc chips doesn't have the 'VI' bit in
1307                  * the config register.
1308                  */
1309                 c->icache.flags |= MIPS_CACHE_VTAG;
1310                 break;
1311
1312         case CPU_ALCHEMY:
1313                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1314                 break;
1315
1316         case CPU_BMIPS5000:
1317                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1318                 /* Cache aliases are handled in hardware; allow HIGHMEM */
1319                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1320                 break;
1321
1322         case CPU_LOONGSON2:
1323                 /*
1324                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1325                  * one op will act on all 4 ways
1326                  */
1327                 c->icache.ways = 1;
1328         }
1329
1330         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1331                icache_size >> 10,
1332                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1333                way_string[c->icache.ways], c->icache.linesz);
1334
1335         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1336                dcache_size >> 10, way_string[c->dcache.ways],
1337                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1338                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1339                         "cache aliases" : "no aliases",
1340                c->dcache.linesz);
1341 }
1342
1343 /*
1344  * If you even _breathe_ on this function, look at the gcc output and make sure
1345  * it does not pop things on and off the stack for the cache sizing loop that
1346  * executes in KSEG1 space or else you will crash and burn badly.  You have
1347  * been warned.
1348  */
1349 static int probe_scache(void)
1350 {
1351         unsigned long flags, addr, begin, end, pow2;
1352         unsigned int config = read_c0_config();
1353         struct cpuinfo_mips *c = &current_cpu_data;
1354
1355         if (config & CONF_SC)
1356                 return 0;
1357
1358         begin = (unsigned long) &_stext;
1359         begin &= ~((4 * 1024 * 1024) - 1);
1360         end = begin + (4 * 1024 * 1024);
1361
1362         /*
1363          * This is such a bitch, you'd think they would make it easy to do
1364          * this.  Away you daemons of stupidity!
1365          */
1366         local_irq_save(flags);
1367
1368         /* Fill each size-multiple cache line with a valid tag. */
1369         pow2 = (64 * 1024);
1370         for (addr = begin; addr < end; addr = (begin + pow2)) {
1371                 unsigned long *p = (unsigned long *) addr;
1372                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1373                 pow2 <<= 1;
1374         }
1375
1376         /* Load first line with zero (therefore invalid) tag. */
1377         write_c0_taglo(0);
1378         write_c0_taghi(0);
1379         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1380         cache_op(Index_Store_Tag_I, begin);
1381         cache_op(Index_Store_Tag_D, begin);
1382         cache_op(Index_Store_Tag_SD, begin);
1383
1384         /* Now search for the wrap around point. */
1385         pow2 = (128 * 1024);
1386         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1387                 cache_op(Index_Load_Tag_SD, addr);
1388                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1389                 if (!read_c0_taglo())
1390                         break;
1391                 pow2 <<= 1;
1392         }
1393         local_irq_restore(flags);
1394         addr -= begin;
1395
1396         scache_size = addr;
1397         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1398         c->scache.ways = 1;
1399         c->scache.waybit = 0;           /* does not matter */
1400
1401         return 1;
1402 }
1403
1404 static void loongson2_sc_init(void)
1405 {
1406         struct cpuinfo_mips *c = &current_cpu_data;
1407
1408         scache_size = 512*1024;
1409         c->scache.linesz = 32;
1410         c->scache.ways = 4;
1411         c->scache.waybit = 0;
1412         c->scache.waysize = scache_size / (c->scache.ways);
1413         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1414         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1415                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1416
1417         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1418 }
1419
1420 static void __init loongson3_sc_init(void)
1421 {
1422         struct cpuinfo_mips *c = &current_cpu_data;
1423         unsigned int config2, lsize;
1424
1425         config2 = read_c0_config2();
1426         lsize = (config2 >> 4) & 15;
1427         if (lsize)
1428                 c->scache.linesz = 2 << lsize;
1429         else
1430                 c->scache.linesz = 0;
1431         c->scache.sets = 64 << ((config2 >> 8) & 15);
1432         c->scache.ways = 1 + (config2 & 15);
1433
1434         scache_size = c->scache.sets *
1435                                   c->scache.ways *
1436                                   c->scache.linesz;
1437         /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1438         scache_size *= 4;
1439         c->scache.waybit = 0;
1440         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1441                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1442         if (scache_size)
1443                 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1444         return;
1445 }
1446
1447 extern int r5k_sc_init(void);
1448 extern int rm7k_sc_init(void);
1449 extern int mips_sc_init(void);
1450
1451 static void setup_scache(void)
1452 {
1453         struct cpuinfo_mips *c = &current_cpu_data;
1454         unsigned int config = read_c0_config();
1455         int sc_present = 0;
1456
1457         /*
1458          * Do the probing thing on R4000SC and R4400SC processors.  Other
1459          * processors don't have a S-cache that would be relevant to the
1460          * Linux memory management.
1461          */
1462         switch (current_cpu_type()) {
1463         case CPU_R4000SC:
1464         case CPU_R4000MC:
1465         case CPU_R4400SC:
1466         case CPU_R4400MC:
1467                 sc_present = run_uncached(probe_scache);
1468                 if (sc_present)
1469                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1470                 break;
1471
1472         case CPU_R10000:
1473         case CPU_R12000:
1474         case CPU_R14000:
1475         case CPU_R16000:
1476                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1477                 c->scache.linesz = 64 << ((config >> 13) & 1);
1478                 c->scache.ways = 2;
1479                 c->scache.waybit= 0;
1480                 sc_present = 1;
1481                 break;
1482
1483         case CPU_R5000:
1484         case CPU_NEVADA:
1485 #ifdef CONFIG_R5000_CPU_SCACHE
1486                 r5k_sc_init();
1487 #endif
1488                 return;
1489
1490         case CPU_RM7000:
1491 #ifdef CONFIG_RM7000_CPU_SCACHE
1492                 rm7k_sc_init();
1493 #endif
1494                 return;
1495
1496         case CPU_LOONGSON2:
1497                 loongson2_sc_init();
1498                 return;
1499
1500         case CPU_LOONGSON3:
1501                 loongson3_sc_init();
1502                 return;
1503
1504         case CPU_CAVIUM_OCTEON3:
1505         case CPU_XLP:
1506                 /* don't need to worry about L2, fully coherent */
1507                 return;
1508
1509         default:
1510                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1511                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1512                                     MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1513 #ifdef CONFIG_MIPS_CPU_SCACHE
1514                         if (mips_sc_init ()) {
1515                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1516                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1517                                        scache_size >> 10,
1518                                        way_string[c->scache.ways], c->scache.linesz);
1519                         }
1520 #else
1521                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1522                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1523 #endif
1524                         return;
1525                 }
1526                 sc_present = 0;
1527         }
1528
1529         if (!sc_present)
1530                 return;
1531
1532         /* compute a couple of other cache variables */
1533         c->scache.waysize = scache_size / c->scache.ways;
1534
1535         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1536
1537         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1538                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1539
1540         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1541 }
1542
1543 void au1x00_fixup_config_od(void)
1544 {
1545         /*
1546          * c0_config.od (bit 19) was write only (and read as 0)
1547          * on the early revisions of Alchemy SOCs.  It disables the bus
1548          * transaction overlapping and needs to be set to fix various errata.
1549          */
1550         switch (read_c0_prid()) {
1551         case 0x00030100: /* Au1000 DA */
1552         case 0x00030201: /* Au1000 HA */
1553         case 0x00030202: /* Au1000 HB */
1554         case 0x01030200: /* Au1500 AB */
1555         /*
1556          * Au1100 errata actually keeps silence about this bit, so we set it
1557          * just in case for those revisions that require it to be set according
1558          * to the (now gone) cpu table.
1559          */
1560         case 0x02030200: /* Au1100 AB */
1561         case 0x02030201: /* Au1100 BA */
1562         case 0x02030202: /* Au1100 BC */
1563                 set_c0_config(1 << 19);
1564                 break;
1565         }
1566 }
1567
1568 /* CP0 hazard avoidance. */
1569 #define NXP_BARRIER()                                                   \
1570          __asm__ __volatile__(                                          \
1571         ".set noreorder\n\t"                                            \
1572         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1573         ".set reorder\n\t")
1574
1575 static void nxp_pr4450_fixup_config(void)
1576 {
1577         unsigned long config0;
1578
1579         config0 = read_c0_config();
1580
1581         /* clear all three cache coherency fields */
1582         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1583         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1584                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1585                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1586         write_c0_config(config0);
1587         NXP_BARRIER();
1588 }
1589
1590 static int cca = -1;
1591
1592 static int __init cca_setup(char *str)
1593 {
1594         get_option(&str, &cca);
1595
1596         return 0;
1597 }
1598
1599 early_param("cca", cca_setup);
1600
1601 static void coherency_setup(void)
1602 {
1603         if (cca < 0 || cca > 7)
1604                 cca = read_c0_config() & CONF_CM_CMASK;
1605         _page_cachable_default = cca << _CACHE_SHIFT;
1606
1607         pr_debug("Using cache attribute %d\n", cca);
1608         change_c0_config(CONF_CM_CMASK, cca);
1609
1610         /*
1611          * c0_status.cu=0 specifies that updates by the sc instruction use
1612          * the coherency mode specified by the TLB; 1 means cachable
1613          * coherent update on write will be used.  Not all processors have
1614          * this bit and; some wire it to zero, others like Toshiba had the
1615          * silly idea of putting something else there ...
1616          */
1617         switch (current_cpu_type()) {
1618         case CPU_R4000PC:
1619         case CPU_R4000SC:
1620         case CPU_R4000MC:
1621         case CPU_R4400PC:
1622         case CPU_R4400SC:
1623         case CPU_R4400MC:
1624                 clear_c0_config(CONF_CU);
1625                 break;
1626         /*
1627          * We need to catch the early Alchemy SOCs with
1628          * the write-only co_config.od bit and set it back to one on:
1629          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1630          */
1631         case CPU_ALCHEMY:
1632                 au1x00_fixup_config_od();
1633                 break;
1634
1635         case PRID_IMP_PR4450:
1636                 nxp_pr4450_fixup_config();
1637                 break;
1638         }
1639 }
1640
1641 static void r4k_cache_error_setup(void)
1642 {
1643         extern char __weak except_vec2_generic;
1644         extern char __weak except_vec2_sb1;
1645
1646         switch (current_cpu_type()) {
1647         case CPU_SB1:
1648         case CPU_SB1A:
1649                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1650                 break;
1651
1652         default:
1653                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1654                 break;
1655         }
1656 }
1657
1658 void r4k_cache_init(void)
1659 {
1660         extern void build_clear_page(void);
1661         extern void build_copy_page(void);
1662         struct cpuinfo_mips *c = &current_cpu_data;
1663
1664         probe_pcache();
1665         setup_scache();
1666
1667         r4k_blast_dcache_page_setup();
1668         r4k_blast_dcache_page_indexed_setup();
1669         r4k_blast_dcache_setup();
1670         r4k_blast_icache_page_setup();
1671         r4k_blast_icache_page_indexed_setup();
1672         r4k_blast_icache_setup();
1673         r4k_blast_scache_page_setup();
1674         r4k_blast_scache_page_indexed_setup();
1675         r4k_blast_scache_setup();
1676 #ifdef CONFIG_EVA
1677         r4k_blast_dcache_user_page_setup();
1678         r4k_blast_icache_user_page_setup();
1679 #endif
1680
1681         /*
1682          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1683          * This code supports virtually indexed processors and will be
1684          * unnecessarily inefficient on physically indexed processors.
1685          */
1686         if (c->dcache.linesz)
1687                 shm_align_mask = max_t( unsigned long,
1688                                         c->dcache.sets * c->dcache.linesz - 1,
1689                                         PAGE_SIZE - 1);
1690         else
1691                 shm_align_mask = PAGE_SIZE-1;
1692
1693         __flush_cache_vmap      = r4k__flush_cache_vmap;
1694         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1695
1696         flush_cache_all         = cache_noop;
1697         __flush_cache_all       = r4k___flush_cache_all;
1698         flush_cache_mm          = r4k_flush_cache_mm;
1699         flush_cache_page        = r4k_flush_cache_page;
1700         flush_cache_range       = r4k_flush_cache_range;
1701
1702         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1703
1704         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1705         flush_icache_all        = r4k_flush_icache_all;
1706         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1707         flush_data_cache_page   = r4k_flush_data_cache_page;
1708         flush_icache_range      = r4k_flush_icache_range;
1709         local_flush_icache_range        = local_r4k_flush_icache_range;
1710
1711 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
1712         if (coherentio) {
1713                 _dma_cache_wback_inv    = (void *)cache_noop;
1714                 _dma_cache_wback        = (void *)cache_noop;
1715                 _dma_cache_inv          = (void *)cache_noop;
1716         } else {
1717                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1718                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1719                 _dma_cache_inv          = r4k_dma_cache_inv;
1720         }
1721 #endif
1722
1723         build_clear_page();
1724         build_copy_page();
1725
1726         /*
1727          * We want to run CMP kernels on core with and without coherent
1728          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1729          * or not to flush caches.
1730          */
1731         local_r4k___flush_cache_all(NULL);
1732
1733         coherency_setup();
1734         board_cache_error_setup = r4k_cache_error_setup;
1735
1736         /*
1737          * Per-CPU overrides
1738          */
1739         switch (current_cpu_type()) {
1740         case CPU_BMIPS4350:
1741         case CPU_BMIPS4380:
1742                 /* No IPI is needed because all CPUs share the same D$ */
1743                 flush_data_cache_page = r4k_blast_dcache_page;
1744                 break;
1745         case CPU_BMIPS5000:
1746                 /* We lose our superpowers if L2 is disabled */
1747                 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1748                         break;
1749
1750                 /* I$ fills from D$ just by emptying the write buffers */
1751                 flush_cache_page = (void *)b5k_instruction_hazard;
1752                 flush_cache_range = (void *)b5k_instruction_hazard;
1753                 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
1754                 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1755                 flush_data_cache_page = (void *)b5k_instruction_hazard;
1756                 flush_icache_range = (void *)b5k_instruction_hazard;
1757                 local_flush_icache_range = (void *)b5k_instruction_hazard;
1758
1759
1760                 /* Optimization: an L2 flush implicitly flushes the L1 */
1761                 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1762                 break;
1763         }
1764 }
1765
1766 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1767                                void *v)
1768 {
1769         switch (cmd) {
1770         case CPU_PM_ENTER_FAILED:
1771         case CPU_PM_EXIT:
1772                 coherency_setup();
1773                 break;
1774         }
1775
1776         return NOTIFY_OK;
1777 }
1778
1779 static struct notifier_block r4k_cache_pm_notifier_block = {
1780         .notifier_call = r4k_cache_pm_notifier,
1781 };
1782
1783 int __init r4k_cache_init_pm(void)
1784 {
1785         return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1786 }
1787 arch_initcall(r4k_cache_init_pm);