arch/openrisc/kernel/entry.S

   1 /*
   2  * OpenRISC entry.S
   3  *
   4  * Linux architectural port borrowing liberally from similar works of
   5  * others.  All original copyrights apply as per the original source
   6  * declaration.
   7  *
   8  * Modifications for the OpenRISC architecture:
   9  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  10  * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
  11  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  12  *
  13  *      This program is free software; you can redistribute it and/or
  14  *      modify it under the terms of the GNU General Public License
  15  *      as published by the Free Software Foundation; either version
  16  *      2 of the License, or (at your option) any later version.
  17  */
  18
  19 #include <linux/linkage.h>
  20
  21 #include <asm/processor.h>
  22 #include <asm/unistd.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/errno.h>
  25 #include <asm/spr_defs.h>
  26 #include <asm/page.h>
  27 #include <asm/mmu.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/asm-offsets.h>
  30
  31 #define DISABLE_INTERRUPTS(t1,t2)                       \
  32         l.mfspr t2,r0,SPR_SR                            ;\
  33         l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE))         ;\
  34         l.ori   t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE))      ;\
  35         l.and   t2,t2,t1                                ;\
  36         l.mtspr r0,t2,SPR_SR
  37
  38 #define ENABLE_INTERRUPTS(t1)                           \
  39         l.mfspr t1,r0,SPR_SR                            ;\
  40         l.ori   t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE)         ;\
  41         l.mtspr r0,t1,SPR_SR
  42
  43 /* =========================================================[ macros ]=== */
  44
  45 /*
  46  * We need to disable interrupts at beginning of RESTORE_ALL
  47  * since interrupt might come in after we've loaded EPC return address
  48  * and overwrite EPC with address somewhere in RESTORE_ALL
  49  * which is of course wrong!
  50  */
  51
  52 #define RESTORE_ALL                                             \
  53         DISABLE_INTERRUPTS(r3,r4)                               ;\
  54         l.lwz   r3,PT_PC(r1)                                    ;\
  55         l.mtspr r0,r3,SPR_EPCR_BASE                             ;\
  56         l.lwz   r3,PT_SR(r1)                                    ;\
  57         l.mtspr r0,r3,SPR_ESR_BASE                              ;\
  58         l.lwz   r2,PT_GPR2(r1)                                  ;\
  59         l.lwz   r3,PT_GPR3(r1)                                  ;\
  60         l.lwz   r4,PT_GPR4(r1)                                  ;\
  61         l.lwz   r5,PT_GPR5(r1)                                  ;\
  62         l.lwz   r6,PT_GPR6(r1)                                  ;\
  63         l.lwz   r7,PT_GPR7(r1)                                  ;\
  64         l.lwz   r8,PT_GPR8(r1)                                  ;\
  65         l.lwz   r9,PT_GPR9(r1)                                  ;\
  66         l.lwz   r10,PT_GPR10(r1)                                        ;\
  67         l.lwz   r11,PT_GPR11(r1)                                        ;\
  68         l.lwz   r12,PT_GPR12(r1)                                        ;\
  69         l.lwz   r13,PT_GPR13(r1)                                        ;\
  70         l.lwz   r14,PT_GPR14(r1)                                        ;\
  71         l.lwz   r15,PT_GPR15(r1)                                        ;\
  72         l.lwz   r16,PT_GPR16(r1)                                        ;\
  73         l.lwz   r17,PT_GPR17(r1)                                        ;\
  74         l.lwz   r18,PT_GPR18(r1)                                        ;\
  75         l.lwz   r19,PT_GPR19(r1)                                        ;\
  76         l.lwz   r20,PT_GPR20(r1)                                        ;\
  77         l.lwz   r21,PT_GPR21(r1)                                        ;\
  78         l.lwz   r22,PT_GPR22(r1)                                        ;\
  79         l.lwz   r23,PT_GPR23(r1)                                        ;\
  80         l.lwz   r24,PT_GPR24(r1)                                        ;\
  81         l.lwz   r25,PT_GPR25(r1)                                        ;\
  82         l.lwz   r26,PT_GPR26(r1)                                        ;\
  83         l.lwz   r27,PT_GPR27(r1)                                        ;\
  84         l.lwz   r28,PT_GPR28(r1)                                        ;\
  85         l.lwz   r29,PT_GPR29(r1)                                        ;\
  86         l.lwz   r30,PT_GPR30(r1)                                        ;\
  87         l.lwz   r31,PT_GPR31(r1)                                        ;\
  88         l.lwz   r1,PT_SP(r1)                                    ;\
  89         l.rfe
  90
  91
  92 #define EXCEPTION_ENTRY(handler)                                \
  93         .global handler                                         ;\
  94 handler:                                                        ;\
  95         /* r1, EPCR, ESR a already saved */                     ;\
  96         l.sw    PT_GPR2(r1),r2                                  ;\
  97         l.sw    PT_GPR3(r1),r3                                  ;\
  98         /* r4 already save */                                   ;\
  99         l.sw    PT_GPR5(r1),r5                                  ;\
 100         l.sw    PT_GPR6(r1),r6                                  ;\
 101         l.sw    PT_GPR7(r1),r7                                  ;\
 102         l.sw    PT_GPR8(r1),r8                                  ;\
 103         l.sw    PT_GPR9(r1),r9                                  ;\
 104         /* r10 already saved */                                 ;\
 105         l.sw    PT_GPR11(r1),r11                                        ;\
 106         /* r12 already saved */                                 ;\
 107         l.sw    PT_GPR13(r1),r13                                        ;\
 108         l.sw    PT_GPR14(r1),r14                                        ;\
 109         l.sw    PT_GPR15(r1),r15                                        ;\
 110         l.sw    PT_GPR16(r1),r16                                        ;\
 111         l.sw    PT_GPR17(r1),r17                                        ;\
 112         l.sw    PT_GPR18(r1),r18                                        ;\
 113         l.sw    PT_GPR19(r1),r19                                        ;\
 114         l.sw    PT_GPR20(r1),r20                                        ;\
 115         l.sw    PT_GPR21(r1),r21                                        ;\
 116         l.sw    PT_GPR22(r1),r22                                        ;\
 117         l.sw    PT_GPR23(r1),r23                                        ;\
 118         l.sw    PT_GPR24(r1),r24                                        ;\
 119         l.sw    PT_GPR25(r1),r25                                        ;\
 120         l.sw    PT_GPR26(r1),r26                                        ;\
 121         l.sw    PT_GPR27(r1),r27                                        ;\
 122         l.sw    PT_GPR28(r1),r28                                        ;\
 123         l.sw    PT_GPR29(r1),r29                                        ;\
 124         /* r30 already save */                                  ;\
 125 /*        l.sw    PT_GPR30(r1),r30*/                                    ;\
 126         l.sw    PT_GPR31(r1),r31                                        ;\
 127         /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
 128         l.addi  r30,r0,-1                                       ;\
 129         l.sw    PT_ORIG_GPR11(r1),r30
 130
 131 #define UNHANDLED_EXCEPTION(handler,vector)                     \
 132         .global handler                                         ;\
 133 handler:                                                        ;\
 134         /* r1, EPCR, ESR already saved */                       ;\
 135         l.sw    PT_GPR2(r1),r2                                  ;\
 136         l.sw    PT_GPR3(r1),r3                                  ;\
 137         l.sw    PT_GPR5(r1),r5                                  ;\
 138         l.sw    PT_GPR6(r1),r6                                  ;\
 139         l.sw    PT_GPR7(r1),r7                                  ;\
 140         l.sw    PT_GPR8(r1),r8                                  ;\
 141         l.sw    PT_GPR9(r1),r9                                  ;\
 142         /* r10 already saved */                                 ;\
 143         l.sw    PT_GPR11(r1),r11                                        ;\
 144         /* r12 already saved */                                 ;\
 145         l.sw    PT_GPR13(r1),r13                                        ;\
 146         l.sw    PT_GPR14(r1),r14                                        ;\
 147         l.sw    PT_GPR15(r1),r15                                        ;\
 148         l.sw    PT_GPR16(r1),r16                                        ;\
 149         l.sw    PT_GPR17(r1),r17                                        ;\
 150         l.sw    PT_GPR18(r1),r18                                        ;\
 151         l.sw    PT_GPR19(r1),r19                                        ;\
 152         l.sw    PT_GPR20(r1),r20                                        ;\
 153         l.sw    PT_GPR21(r1),r21                                        ;\
 154         l.sw    PT_GPR22(r1),r22                                        ;\
 155         l.sw    PT_GPR23(r1),r23                                        ;\
 156         l.sw    PT_GPR24(r1),r24                                        ;\
 157         l.sw    PT_GPR25(r1),r25                                        ;\
 158         l.sw    PT_GPR26(r1),r26                                        ;\
 159         l.sw    PT_GPR27(r1),r27                                        ;\
 160         l.sw    PT_GPR28(r1),r28                                        ;\
 161         l.sw    PT_GPR29(r1),r29                                        ;\
 162         /* r31 already saved */                                 ;\
 163         l.sw    PT_GPR30(r1),r30                                        ;\
 164 /*        l.sw    PT_GPR31(r1),r31      */                              ;\
 165         /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
 166         l.addi  r30,r0,-1                                       ;\
 167         l.sw    PT_ORIG_GPR11(r1),r30                           ;\
 168         l.addi  r3,r1,0                                         ;\
 169         /* r4 is exception EA */                                ;\
 170         l.addi  r5,r0,vector                                    ;\
 171         l.jal   unhandled_exception                             ;\
 172          l.nop                                                  ;\
 173         l.j     _ret_from_exception                             ;\
 174          l.nop
 175
 176 /* clobbers 'reg' */
 177 #define CLEAR_LWA_FLAG(reg)             \
 178         l.movhi reg,hi(lwa_flag)        ;\
 179         l.ori   reg,reg,lo(lwa_flag)    ;\
 180         l.sw    0(reg),r0
 181 /*
 182  * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
 183  *       contain the same values as when exception we're handling
 184  *       occured. in fact they never do. if you need them use
 185  *       values saved on stack (for SPR_EPC, SPR_ESR) or content
 186  *       of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
 187  *       in 'arch/openrisc/kernel/head.S'
 188  */
 189
 190 /* =====================================================[ exceptions] === */
 191
 192 /* ---[ 0x100: RESET exception ]----------------------------------------- */
 193
 194 EXCEPTION_ENTRY(_tng_kernel_start)
 195         l.jal   _start
 196          l.andi r0,r0,0
 197
 198 /* ---[ 0x200: BUS exception ]------------------------------------------- */
 199
 200 EXCEPTION_ENTRY(_bus_fault_handler)
 201         CLEAR_LWA_FLAG(r3)
 202         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 203         l.jal   do_bus_fault
 204          l.addi  r3,r1,0 /* pt_regs */
 205
 206         l.j     _ret_from_exception
 207          l.nop
 208
 209 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
 210 EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
 211         CLEAR_LWA_FLAG(r3)
 212         l.and   r5,r5,r0
 213         l.j     1f
 214          l.nop
 215
 216 EXCEPTION_ENTRY(_data_page_fault_handler)
 217         CLEAR_LWA_FLAG(r3)
 218         /* set up parameters for do_page_fault */
 219         l.ori   r5,r0,0x300                // exception vector
 220 1:
 221         l.addi  r3,r1,0                    // pt_regs
 222         /* r4 set be EXCEPTION_HANDLE */   // effective address of fault
 223
 224 #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
 225         l.lwz   r6,PT_PC(r3)               // address of an offending insn
 226         l.lwz   r6,0(r6)                   // instruction that caused pf
 227
 228         l.srli  r6,r6,26                   // check opcode for jump insn
 229         l.sfeqi r6,0                       // l.j
 230         l.bf    8f
 231         l.sfeqi r6,1                       // l.jal
 232         l.bf    8f
 233         l.sfeqi r6,3                       // l.bnf
 234         l.bf    8f
 235         l.sfeqi r6,4                       // l.bf
 236         l.bf    8f
 237         l.sfeqi r6,0x11                    // l.jr
 238         l.bf    8f
 239         l.sfeqi r6,0x12                    // l.jalr
 240         l.bf    8f
 241          l.nop
 242
 243         l.j     9f
 244          l.nop
 245
 246 8: // offending insn is in delay slot
 247         l.lwz   r6,PT_PC(r3)               // address of an offending insn
 248         l.addi  r6,r6,4
 249         l.lwz   r6,0(r6)                   // instruction that caused pf
 250         l.srli  r6,r6,26                   // get opcode
 251 9: // offending instruction opcode loaded in r6
 252
 253 #else
 254
 255         l.mfspr r6,r0,SPR_SR               // SR
 256         l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
 257         l.sfne  r6,r0                      // exception happened in delay slot
 258         l.bnf   7f
 259          l.lwz  r6,PT_PC(r3)               // address of an offending insn
 260
 261         l.addi  r6,r6,4                    // offending insn is in delay slot
 262 7:
 263         l.lwz   r6,0(r6)                   // instruction that caused pf
 264         l.srli  r6,r6,26                   // check opcode for write access
 265 #endif
 266
 267         l.sfgeui r6,0x33                   // check opcode for write access
 268         l.bnf   1f
 269         l.sfleui r6,0x37
 270         l.bnf   1f
 271         l.ori   r6,r0,0x1                  // write access
 272         l.j     2f
 273          l.nop
 274 1:      l.ori   r6,r0,0x0                  // !write access
 275 2:
 276
 277         /* call fault.c handler in or32/mm/fault.c */
 278         l.jal   do_page_fault
 279          l.nop
 280         l.j     _ret_from_exception
 281          l.nop
 282
 283 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
 284 EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
 285         CLEAR_LWA_FLAG(r3)
 286         l.and   r5,r5,r0
 287         l.j     1f
 288          l.nop
 289
 290 EXCEPTION_ENTRY(_insn_page_fault_handler)
 291         CLEAR_LWA_FLAG(r3)
 292         /* set up parameters for do_page_fault */
 293         l.ori   r5,r0,0x400                // exception vector
 294 1:
 295         l.addi  r3,r1,0                    // pt_regs
 296         /* r4 set be EXCEPTION_HANDLE */   // effective address of fault
 297         l.ori   r6,r0,0x0                  // !write access
 298
 299         /* call fault.c handler in or32/mm/fault.c */
 300         l.jal   do_page_fault
 301          l.nop
 302         l.j     _ret_from_exception
 303          l.nop
 304
 305
 306 /* ---[ 0x500: Timer exception ]----------------------------------------- */
 307
 308 EXCEPTION_ENTRY(_timer_handler)
 309         CLEAR_LWA_FLAG(r3)
 310         l.jal   timer_interrupt
 311          l.addi r3,r1,0 /* pt_regs */
 312
 313         l.j    _ret_from_intr
 314          l.nop
 315
 316 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
 317
 318 EXCEPTION_ENTRY(_alignment_handler)
 319         CLEAR_LWA_FLAG(r3)
 320         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 321         l.jal   do_unaligned_access
 322          l.addi  r3,r1,0 /* pt_regs */
 323
 324         l.j     _ret_from_exception
 325          l.nop
 326
 327 #if 0
 328 EXCEPTION_ENTRY(_alignment_handler)
 329 //        l.mfspr r2,r0,SPR_EEAR_BASE     /* Load the effective address */
 330         l.addi  r2,r4,0
 331 //        l.mfspr r5,r0,SPR_EPCR_BASE     /* Load the insn address */
 332         l.lwz   r5,PT_PC(r1)
 333
 334         l.lwz   r3,0(r5)                /* Load insn */
 335         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 336
 337         l.sfeqi r4,0x00                 /* Check if the load/store insn is in delay slot */
 338         l.bf    jmp
 339         l.sfeqi r4,0x01
 340         l.bf    jmp
 341         l.sfeqi r4,0x03
 342         l.bf    jmp
 343         l.sfeqi r4,0x04
 344         l.bf    jmp
 345         l.sfeqi r4,0x11
 346         l.bf    jr
 347         l.sfeqi r4,0x12
 348         l.bf    jr
 349         l.nop
 350         l.j     1f
 351         l.addi  r5,r5,4                 /* Increment PC to get return insn address */
 352
 353 jmp:
 354         l.slli  r4,r3,6                 /* Get the signed extended jump length */
 355         l.srai  r4,r4,4
 356
 357         l.lwz   r3,4(r5)                /* Load the real load/store insn */
 358
 359         l.add   r5,r5,r4                /* Calculate jump target address */
 360
 361         l.j     1f
 362         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 363
 364 jr:
 365         l.slli  r4,r3,9                 /* Shift to get the reg nb */
 366         l.andi  r4,r4,0x7c
 367
 368         l.lwz   r3,4(r5)                /* Load the real load/store insn */
 369
 370         l.add   r4,r4,r1                /* Load the jump register value from the stack */
 371         l.lwz   r5,0(r4)
 372
 373         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 374
 375
 376 1:
 377 //        l.mtspr r0,r5,SPR_EPCR_BASE
 378         l.sw    PT_PC(r1),r5
 379
 380         l.sfeqi r4,0x26
 381         l.bf    lhs
 382         l.sfeqi r4,0x25
 383         l.bf    lhz
 384         l.sfeqi r4,0x22
 385         l.bf    lws
 386         l.sfeqi r4,0x21
 387         l.bf    lwz
 388         l.sfeqi r4,0x37
 389         l.bf    sh
 390         l.sfeqi r4,0x35
 391         l.bf    sw
 392         l.nop
 393
 394 1:      l.j     1b                      /* I don't know what to do */
 395         l.nop
 396
 397 lhs:    l.lbs   r5,0(r2)
 398         l.slli  r5,r5,8
 399         l.lbz   r6,1(r2)
 400         l.or    r5,r5,r6
 401         l.srli  r4,r3,19
 402         l.andi  r4,r4,0x7c
 403         l.add   r4,r4,r1
 404         l.j     align_end
 405         l.sw    0(r4),r5
 406
 407 lhz:    l.lbz   r5,0(r2)
 408         l.slli  r5,r5,8
 409         l.lbz   r6,1(r2)
 410         l.or    r5,r5,r6
 411         l.srli  r4,r3,19
 412         l.andi  r4,r4,0x7c
 413         l.add   r4,r4,r1
 414         l.j     align_end
 415         l.sw    0(r4),r5
 416
 417 lws:    l.lbs   r5,0(r2)
 418         l.slli  r5,r5,24
 419         l.lbz   r6,1(r2)
 420         l.slli  r6,r6,16
 421         l.or    r5,r5,r6
 422         l.lbz   r6,2(r2)
 423         l.slli  r6,r6,8
 424         l.or    r5,r5,r6
 425         l.lbz   r6,3(r2)
 426         l.or    r5,r5,r6
 427         l.srli  r4,r3,19
 428         l.andi  r4,r4,0x7c
 429         l.add   r4,r4,r1
 430         l.j     align_end
 431         l.sw    0(r4),r5
 432
 433 lwz:    l.lbz   r5,0(r2)
 434         l.slli  r5,r5,24
 435         l.lbz   r6,1(r2)
 436         l.slli  r6,r6,16
 437         l.or    r5,r5,r6
 438         l.lbz   r6,2(r2)
 439         l.slli  r6,r6,8
 440         l.or    r5,r5,r6
 441         l.lbz   r6,3(r2)
 442         l.or    r5,r5,r6
 443         l.srli  r4,r3,19
 444         l.andi  r4,r4,0x7c
 445         l.add   r4,r4,r1
 446         l.j     align_end
 447         l.sw    0(r4),r5
 448
 449 sh:
 450         l.srli  r4,r3,9
 451         l.andi  r4,r4,0x7c
 452         l.add   r4,r4,r1
 453         l.lwz   r5,0(r4)
 454         l.sb    1(r2),r5
 455         l.srli  r5,r5,8
 456         l.j     align_end
 457         l.sb    0(r2),r5
 458
 459 sw:
 460         l.srli  r4,r3,9
 461         l.andi  r4,r4,0x7c
 462         l.add   r4,r4,r1
 463         l.lwz   r5,0(r4)
 464         l.sb    3(r2),r5
 465         l.srli  r5,r5,8
 466         l.sb    2(r2),r5
 467         l.srli  r5,r5,8
 468         l.sb    1(r2),r5
 469         l.srli  r5,r5,8
 470         l.j     align_end
 471         l.sb    0(r2),r5
 472
 473 align_end:
 474         l.j    _ret_from_intr
 475         l.nop
 476 #endif
 477
 478 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
 479
 480 EXCEPTION_ENTRY(_illegal_instruction_handler)
 481         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 482         l.jal   do_illegal_instruction
 483          l.addi  r3,r1,0 /* pt_regs */
 484
 485         l.j     _ret_from_exception
 486          l.nop
 487
 488 /* ---[ 0x800: External interrupt exception ]---------------------------- */
 489
 490 EXCEPTION_ENTRY(_external_irq_handler)
 491 #ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
 492         l.lwz   r4,PT_SR(r1)            // were interrupts enabled ?
 493         l.andi  r4,r4,SPR_SR_IEE
 494         l.sfeqi r4,0
 495         l.bnf   1f                      // ext irq enabled, all ok.
 496         l.nop
 497
 498 #ifdef CONFIG_PRINTK
 499         l.addi  r1,r1,-0x8
 500         l.movhi r3,hi(42f)
 501         l.ori   r3,r3,lo(42f)
 502         l.sw    0x0(r1),r3
 503         l.jal   printk
 504         l.sw    0x4(r1),r4
 505         l.addi  r1,r1,0x8
 506
 507         .section .rodata, "a"
 508 42:
 509                 .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
 510                 .align 4
 511         .previous
 512 #endif
 513
 514         l.ori   r4,r4,SPR_SR_IEE        // fix the bug
 515 //      l.sw    PT_SR(r1),r4
 516 1:
 517 #endif
 518         CLEAR_LWA_FLAG(r3)
 519         l.addi  r3,r1,0
 520         l.movhi r8,hi(do_IRQ)
 521         l.ori   r8,r8,lo(do_IRQ)
 522         l.jalr r8
 523         l.nop
 524         l.j    _ret_from_intr
 525         l.nop
 526
 527 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
 528
 529
 530 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
 531
 532
 533 /* ---[ 0xb00: Range exception ]----------------------------------------- */
 534
 535 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
 536
 537 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
 538
 539 /*
 540  * Syscalls are a special type of exception in that they are
 541  * _explicitly_ invoked by userspace and can therefore be
 542  * held to conform to the same ABI as normal functions with
 543  * respect to whether registers are preserved across the call
 544  * or not.
 545  */
 546
 547 /* Upon syscall entry we just save the callee-saved registers
 548  * and not the call-clobbered ones.
 549  */
 550
 551 _string_syscall_return:
 552         .string "syscall return %ld \n\r\0"
 553         .align 4
 554
 555 ENTRY(_sys_call_handler)
 556         /* syscalls run with interrupts enabled */
 557         ENABLE_INTERRUPTS(r29)          // enable interrupts, r29 is temp
 558
 559         /* r1, EPCR, ESR a already saved */
 560         l.sw    PT_GPR2(r1),r2
 561         /* r3-r8 must be saved because syscall restart relies
 562          * on us being able to restart the syscall args... technically
 563          * they should be clobbered, otherwise
 564          */
 565         l.sw    PT_GPR3(r1),r3
 566         /*
 567          * r4 already saved
 568          * r4 holds the EEAR address of the fault, use it as screatch reg and
 569          * then load the original r4
 570          */
 571         CLEAR_LWA_FLAG(r4)
 572         l.lwz   r4,PT_GPR4(r1)
 573         l.sw    PT_GPR5(r1),r5
 574         l.sw    PT_GPR6(r1),r6
 575         l.sw    PT_GPR7(r1),r7
 576         l.sw    PT_GPR8(r1),r8
 577         l.sw    PT_GPR9(r1),r9
 578         /* r10 already saved */
 579         l.sw    PT_GPR11(r1),r11
 580         /* orig_gpr11 must be set for syscalls */
 581         l.sw    PT_ORIG_GPR11(r1),r11
 582         /* r12,r13 already saved */
 583
 584         /* r14-r28 (even) aren't touched by the syscall fast path below
 585          * so we don't need to save them.  However, the functions that return
 586          * to userspace via a call to switch() DO need to save these because
 587          * switch() effectively clobbers them... saving these registers for
 588          * such functions is handled in their syscall wrappers (see fork, vfork,
 589          * and clone, below).
 590
 591         /* r30 is the only register we clobber in the fast path */
 592         /* r30 already saved */
 593 /*      l.sw    PT_GPR30(r1),r30 */
 594
 595 _syscall_check_trace_enter:
 596         /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
 597         l.lwz   r30,TI_FLAGS(r10)
 598         l.andi  r30,r30,_TIF_SYSCALL_TRACE
 599         l.sfne  r30,r0
 600         l.bf    _syscall_trace_enter
 601          l.nop
 602
 603 _syscall_check:
 604         /* Ensure that the syscall number is reasonable */
 605         l.sfgeui r11,__NR_syscalls
 606         l.bf    _syscall_badsys
 607          l.nop
 608
 609 _syscall_call:
 610         l.movhi r29,hi(sys_call_table)
 611         l.ori   r29,r29,lo(sys_call_table)
 612         l.slli  r11,r11,2
 613         l.add   r29,r29,r11
 614         l.lwz   r29,0(r29)
 615
 616         l.jalr  r29
 617          l.nop
 618
 619 _syscall_return:
 620         /* All syscalls return here... just pay attention to ret_from_fork
 621          * which does it in a round-about way.
 622          */
 623         l.sw    PT_GPR11(r1),r11           // save return value
 624
 625 #if 0
 626 _syscall_debug:
 627         l.movhi r3,hi(_string_syscall_return)
 628         l.ori   r3,r3,lo(_string_syscall_return)
 629         l.ori   r27,r0,1
 630         l.sw    -4(r1),r27
 631         l.sw    -8(r1),r11
 632         l.addi  r1,r1,-8
 633         l.movhi r27,hi(printk)
 634         l.ori   r27,r27,lo(printk)
 635         l.jalr  r27
 636          l.nop
 637         l.addi  r1,r1,8
 638 #endif
 639
 640 _syscall_check_trace_leave:
 641         /* r30 is a callee-saved register so this should still hold the
 642          * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
 643          * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
 644          */
 645         l.sfne  r30,r0
 646         l.bf    _syscall_trace_leave
 647          l.nop
 648
 649 /* This is where the exception-return code begins... interrupts need to be
 650  * disabled the rest of the way here because we can't afford to miss any
 651  * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
 652
 653 _syscall_check_work:
 654         /* Here we need to disable interrupts */
 655         DISABLE_INTERRUPTS(r27,r29)
 656         l.lwz   r30,TI_FLAGS(r10)
 657         l.andi  r30,r30,_TIF_WORK_MASK
 658         l.sfne  r30,r0
 659
 660         l.bnf   _syscall_resume_userspace
 661          l.nop
 662
 663         /* Work pending follows a different return path, so we need to
 664          * make sure that all the call-saved registers get into pt_regs
 665          * before branching...
 666          */
 667         l.sw    PT_GPR14(r1),r14
 668         l.sw    PT_GPR16(r1),r16
 669         l.sw    PT_GPR18(r1),r18
 670         l.sw    PT_GPR20(r1),r20
 671         l.sw    PT_GPR22(r1),r22
 672         l.sw    PT_GPR24(r1),r24
 673         l.sw    PT_GPR26(r1),r26
 674         l.sw    PT_GPR28(r1),r28
 675
 676         /* _work_pending needs to be called with interrupts disabled */
 677         l.j     _work_pending
 678          l.nop
 679
 680 _syscall_resume_userspace:
 681 //      ENABLE_INTERRUPTS(r29)
 682
 683
 684 /* This is the hot path for returning to userspace from a syscall.  If there's
 685  * work to be done and the branch to _work_pending was taken above, then the
 686  * return to userspace will be done via the normal exception return path...
 687  * that path restores _all_ registers and will overwrite the "clobbered"
 688  * registers with whatever garbage is in pt_regs -- that's OK because those
 689  * registers are clobbered anyway and because the extra work is insignificant
 690  * in the context of the extra work that _work_pending is doing.
 691
 692 /* Once again, syscalls are special and only guarantee to preserve the
 693  * same registers as a normal function call */
 694
 695 /* The assumption here is that the registers r14-r28 (even) are untouched and
 696  * don't need to be restored... be sure that that's really the case!
 697  */
 698
 699 /* This is still too much... we should only be restoring what we actually
 700  * clobbered... we should even be using 'scratch' (odd) regs above so that
 701  * we don't need to restore anything, hardly...
 702  */
 703
 704         l.lwz   r2,PT_GPR2(r1)
 705
 706         /* Restore args */
 707         /* r3-r8 are technically clobbered, but syscall restart needs these
 708          * to be restored...
 709          */
 710         l.lwz   r3,PT_GPR3(r1)
 711         l.lwz   r4,PT_GPR4(r1)
 712         l.lwz   r5,PT_GPR5(r1)
 713         l.lwz   r6,PT_GPR6(r1)
 714         l.lwz   r7,PT_GPR7(r1)
 715         l.lwz   r8,PT_GPR8(r1)
 716
 717         l.lwz   r9,PT_GPR9(r1)
 718         l.lwz   r10,PT_GPR10(r1)
 719         l.lwz   r11,PT_GPR11(r1)
 720
 721         /* r30 is the only register we clobber in the fast path */
 722         l.lwz   r30,PT_GPR30(r1)
 723
 724         /* Here we use r13-r19 (odd) as scratch regs */
 725         l.lwz   r13,PT_PC(r1)
 726         l.lwz   r15,PT_SR(r1)
 727         l.lwz   r1,PT_SP(r1)
 728         /* Interrupts need to be disabled for setting EPCR and ESR
 729          * so that another interrupt doesn't come in here and clobber
 730          * them before we can use them for our l.rfe */
 731         DISABLE_INTERRUPTS(r17,r19)
 732         l.mtspr r0,r13,SPR_EPCR_BASE
 733         l.mtspr r0,r15,SPR_ESR_BASE
 734         l.rfe
 735
 736 /* End of hot path!
 737  * Keep the below tracing and error handling out of the hot path...
 738 */
 739
 740 _syscall_trace_enter:
 741         /* Here we pass pt_regs to do_syscall_trace_enter.  Make sure
 742          * that function is really getting all the info it needs as
 743          * pt_regs isn't a complete set of userspace regs, just the
 744          * ones relevant to the syscall...
 745          *
 746          * Note use of delay slot for setting argument.
 747          */
 748         l.jal   do_syscall_trace_enter
 749          l.addi r3,r1,0
 750
 751         /* Restore arguments (not preserved across do_syscall_trace_enter)
 752          * so that we can do the syscall for real and return to the syscall
 753          * hot path.
 754          */
 755         l.lwz   r11,PT_GPR11(r1)
 756         l.lwz   r3,PT_GPR3(r1)
 757         l.lwz   r4,PT_GPR4(r1)
 758         l.lwz   r5,PT_GPR5(r1)
 759         l.lwz   r6,PT_GPR6(r1)
 760         l.lwz   r7,PT_GPR7(r1)
 761
 762         l.j     _syscall_check
 763          l.lwz  r8,PT_GPR8(r1)
 764
 765 _syscall_trace_leave:
 766         l.jal   do_syscall_trace_leave
 767          l.addi r3,r1,0
 768
 769         l.j     _syscall_check_work
 770          l.nop
 771
 772 _syscall_badsys:
 773         /* Here we effectively pretend to have executed an imaginary
 774          * syscall that returns -ENOSYS and then return to the regular
 775          * syscall hot path.
 776          * Note that "return value" is set in the delay slot...
 777          */
 778         l.j     _syscall_return
 779          l.addi r11,r0,-ENOSYS
 780
 781 /******* END SYSCALL HANDLING *******/
 782
 783 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
 784
 785 UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
 786
 787 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
 788
 789 EXCEPTION_ENTRY(_trap_handler)
 790         CLEAR_LWA_FLAG(r3)
 791         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 792         l.jal   do_trap
 793          l.addi  r3,r1,0 /* pt_regs */
 794
 795         l.j     _ret_from_exception
 796          l.nop
 797
 798 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
 799
 800 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
 801
 802 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
 803
 804 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
 805
 806 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
 807
 808 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
 809
 810 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
 811
 812 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
 813
 814 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
 815
 816 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
 817
 818 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
 819
 820 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
 821
 822 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
 823
 824 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
 825
 826 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
 827
 828 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
 829
 830 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
 831
 832 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
 833
 834 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
 835
 836 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
 837
 838 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
 839
 840 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
 841
 842 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
 843
 844 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
 845
 846 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
 847
 848 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
 849
 850 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
 851
 852 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
 853
 854 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
 855
 856 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
 857
 858 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
 859
 860 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
 861
 862 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
 863
 864 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
 865
 866 /* ========================================================[ return ] === */
 867
 868 _resume_userspace:
 869         DISABLE_INTERRUPTS(r3,r4)
 870         l.lwz   r4,TI_FLAGS(r10)
 871         l.andi  r13,r4,_TIF_WORK_MASK
 872         l.sfeqi r13,0
 873         l.bf    _restore_all
 874          l.nop
 875
 876 _work_pending:
 877         l.lwz   r5,PT_ORIG_GPR11(r1)
 878         l.sfltsi r5,0
 879         l.bnf   1f
 880          l.nop
 881         l.andi  r5,r5,0
 882 1:
 883         l.jal   do_work_pending
 884          l.ori  r3,r1,0                 /* pt_regs */
 885
 886         l.sfeqi r11,0
 887         l.bf    _restore_all
 888          l.nop
 889         l.sfltsi r11,0
 890         l.bnf   1f
 891          l.nop
 892         l.and   r11,r11,r0
 893         l.ori   r11,r11,__NR_restart_syscall
 894         l.j     _syscall_check_trace_enter
 895          l.nop
 896 1:
 897         l.lwz   r11,PT_ORIG_GPR11(r1)
 898         /* Restore arg registers */
 899         l.lwz   r3,PT_GPR3(r1)
 900         l.lwz   r4,PT_GPR4(r1)
 901         l.lwz   r5,PT_GPR5(r1)
 902         l.lwz   r6,PT_GPR6(r1)
 903         l.lwz   r7,PT_GPR7(r1)
 904         l.j     _syscall_check_trace_enter
 905          l.lwz  r8,PT_GPR8(r1)
 906
 907 _restore_all:
 908         RESTORE_ALL
 909         /* This returns to userspace code */
 910
 911
 912 ENTRY(_ret_from_intr)
 913 ENTRY(_ret_from_exception)
 914         l.lwz   r4,PT_SR(r1)
 915         l.andi  r3,r4,SPR_SR_SM
 916         l.sfeqi r3,0
 917         l.bnf   _restore_all
 918          l.nop
 919         l.j     _resume_userspace
 920          l.nop
 921
 922 ENTRY(ret_from_fork)
 923         l.jal   schedule_tail
 924          l.nop
 925
 926         /* Check if we are a kernel thread */
 927         l.sfeqi r20,0
 928         l.bf    1f
 929          l.nop
 930
 931         /* ...we are a kernel thread so invoke the requested callback */
 932         l.jalr  r20
 933          l.or   r3,r22,r0
 934
 935 1:
 936         /* _syscall_returns expect r11 to contain return value */
 937         l.lwz   r11,PT_GPR11(r1)
 938
 939         /* The syscall fast path return expects call-saved registers
 940          * r12-r28 to be untouched, so we restore them here as they
 941          * will have been effectively clobbered when arriving here
 942          * via the call to switch()
 943          */
 944         l.lwz   r12,PT_GPR12(r1)
 945         l.lwz   r14,PT_GPR14(r1)
 946         l.lwz   r16,PT_GPR16(r1)
 947         l.lwz   r18,PT_GPR18(r1)
 948         l.lwz   r20,PT_GPR20(r1)
 949         l.lwz   r22,PT_GPR22(r1)
 950         l.lwz   r24,PT_GPR24(r1)
 951         l.lwz   r26,PT_GPR26(r1)
 952         l.lwz   r28,PT_GPR28(r1)
 953
 954         l.j     _syscall_return
 955          l.nop
 956
 957 /* ========================================================[ switch ] === */
 958
 959 /*
 960  * This routine switches between two different tasks.  The process
 961  * state of one is saved on its kernel stack.  Then the state
 962  * of the other is restored from its kernel stack.  The memory
 963  * management hardware is updated to the second process's state.
 964  * Finally, we can return to the second process, via the 'return'.
 965  *
 966  * Note: there are two ways to get to the "going out" portion
 967  * of this code; either by coming in via the entry (_switch)
 968  * or via "fork" which must set up an environment equivalent
 969  * to the "_switch" path.  If you change this (or in particular, the
 970  * SAVE_REGS macro), you'll have to change the fork code also.
 971  */
 972
 973
 974 /* _switch MUST never lay on page boundry, cause it runs from
 975  * effective addresses and beeing interrupted by iTLB miss would kill it.
 976  * dTLB miss seams to never accour in the bad place since data accesses
 977  * are from task structures which are always page aligned.
 978  *
 979  * The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
 980  * register, then load the previous register values and only at the end call
 981  * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
 982  * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
 983  * holds for ESR)
 984  *
 985  * To avoid this problems it is sufficient to align _switch to
 986  * some nice round number smaller than it's size...
 987  */
 988
 989 /* ABI rules apply here... we either enter _switch via schedule() or via
 990  * an imaginary call to which we shall return at return_from_fork.  Either
 991  * way, we are a function call and only need to preserve the callee-saved
 992  * registers when we return.  As such, we don't need to save the registers
 993  * on the stack that we won't be returning as they were...
 994  */
 995
 996         .align 0x400
 997 ENTRY(_switch)
 998         /* We don't store SR as _switch only gets called in a context where
 999          * the SR will be the same going in and coming out... */
1000
1001         /* Set up new pt_regs struct for saving task state */
1002         l.addi  r1,r1,-(INT_FRAME_SIZE)
1003
1004         /* No need to store r1/PT_SP as it goes into KSP below */
1005         l.sw    PT_GPR2(r1),r2
1006         l.sw    PT_GPR9(r1),r9
1007         /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1008          * and expects r12 to be callee-saved... */
1009         l.sw    PT_GPR12(r1),r12
1010         l.sw    PT_GPR14(r1),r14
1011         l.sw    PT_GPR16(r1),r16
1012         l.sw    PT_GPR18(r1),r18
1013         l.sw    PT_GPR20(r1),r20
1014         l.sw    PT_GPR22(r1),r22
1015         l.sw    PT_GPR24(r1),r24
1016         l.sw    PT_GPR26(r1),r26
1017         l.sw    PT_GPR28(r1),r28
1018         l.sw    PT_GPR30(r1),r30
1019
1020         l.addi  r11,r10,0                       /* Save old 'current' to 'last' return value*/
1021
1022         /* We use thread_info->ksp for storing the address of the above
1023          * structure so that we can get back to it later... we don't want
1024          * to lose the value of thread_info->ksp, though, so store it as
1025          * pt_regs->sp so that we can easily restore it when we are made
1026          * live again...
1027          */
1028
1029         /* Save the old value of thread_info->ksp as pt_regs->sp */
1030         l.lwz   r29,TI_KSP(r10)
1031         l.sw    PT_SP(r1),r29
1032
1033         /* Swap kernel stack pointers */
1034         l.sw    TI_KSP(r10),r1                  /* Save old stack pointer */
1035         l.or    r10,r4,r0                       /* Set up new current_thread_info */
1036         l.lwz   r1,TI_KSP(r10)                  /* Load new stack pointer */
1037
1038         /* Restore the old value of thread_info->ksp */
1039         l.lwz   r29,PT_SP(r1)
1040         l.sw    TI_KSP(r10),r29
1041
1042         /* ...and restore the registers, except r11 because the return value
1043          * has already been set above.
1044          */
1045         l.lwz   r2,PT_GPR2(r1)
1046         l.lwz   r9,PT_GPR9(r1)
1047         /* No need to restore r10 */
1048         /* ...and do not restore r11 */
1049
1050         /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1051          * and expects r12 to be callee-saved... */
1052         l.lwz   r12,PT_GPR12(r1)
1053         l.lwz   r14,PT_GPR14(r1)
1054         l.lwz   r16,PT_GPR16(r1)
1055         l.lwz   r18,PT_GPR18(r1)
1056         l.lwz   r20,PT_GPR20(r1)
1057         l.lwz   r22,PT_GPR22(r1)
1058         l.lwz   r24,PT_GPR24(r1)
1059         l.lwz   r26,PT_GPR26(r1)
1060         l.lwz   r28,PT_GPR28(r1)
1061         l.lwz   r30,PT_GPR30(r1)
1062
1063         /* Unwind stack to pre-switch state */
1064         l.addi  r1,r1,(INT_FRAME_SIZE)
1065
1066         /* Return via the link-register back to where we 'came from', where
1067          * that may be either schedule(), ret_from_fork(), or
1068          * ret_from_kernel_thread().  If we are returning to a new thread,
1069          * we are expected to have set up the arg to schedule_tail already,
1070          * hence we do so here unconditionally:
1071          */
1072         l.lwz   r3,TI_TASK(r3)          /* Load 'prev' as schedule_tail arg */
1073         l.jr    r9
1074          l.nop
1075
1076 /* ==================================================================== */
1077
1078 /* These all use the delay slot for setting the argument register, so the
1079  * jump is always happening after the l.addi instruction.
1080  *
1081  * These are all just wrappers that don't touch the link-register r9, so the
1082  * return from the "real" syscall function will return back to the syscall
1083  * code that did the l.jal that brought us here.
1084  */
1085
1086 /* fork requires that we save all the callee-saved registers because they
1087  * are all effectively clobbered by the call to _switch.  Here we store
1088  * all the registers that aren't touched by the syscall fast path and thus
1089  * weren't saved there.
1090  */
1091
1092 _fork_save_extra_regs_and_call:
1093         l.sw    PT_GPR14(r1),r14
1094         l.sw    PT_GPR16(r1),r16
1095         l.sw    PT_GPR18(r1),r18
1096         l.sw    PT_GPR20(r1),r20
1097         l.sw    PT_GPR22(r1),r22
1098         l.sw    PT_GPR24(r1),r24
1099         l.sw    PT_GPR26(r1),r26
1100         l.jr    r29
1101          l.sw    PT_GPR28(r1),r28
1102
1103 ENTRY(__sys_clone)
1104         l.movhi r29,hi(sys_clone)
1105         l.ori   r29,r29,lo(sys_clone)
1106         l.j     _fork_save_extra_regs_and_call
1107          l.nop
1108
1109 ENTRY(__sys_fork)
1110         l.movhi r29,hi(sys_fork)
1111         l.ori   r29,r29,lo(sys_fork)
1112         l.j     _fork_save_extra_regs_and_call
1113          l.nop
1114
1115 ENTRY(sys_rt_sigreturn)
1116         l.jal   _sys_rt_sigreturn
1117          l.addi r3,r1,0
1118         l.sfne  r30,r0
1119         l.bnf   _no_syscall_trace
1120          l.nop
1121         l.jal   do_syscall_trace_leave
1122          l.addi r3,r1,0
1123 _no_syscall_trace:
1124         l.j     _resume_userspace
1125          l.nop
1126
1127 /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1128  * The functions takes a variable number of parameters depending on which
1129  * particular flavour of atomic you want... parameter 1 is a flag identifying
1130  * the atomic in question.  Currently, this function implements the
1131  * following variants:
1132  *
1133  * XCHG:
1134  *  @flag: 1
1135  *  @ptr1:
1136  *  @ptr2:
1137  * Atomically exchange the values in pointers 1 and 2.
1138  *
1139  */
1140
1141 ENTRY(sys_or1k_atomic)
1142         /* FIXME: This ignores r3 and always does an XCHG */
1143         DISABLE_INTERRUPTS(r17,r19)
1144         l.lwz   r29,0(r4)
1145         l.lwz   r27,0(r5)
1146         l.sw    0(r4),r27
1147         l.sw    0(r5),r29
1148         ENABLE_INTERRUPTS(r17)
1149         l.jr    r9
1150          l.or   r11,r0,r0
1151
1152 /* ============================================================[ EOF ]=== */