arch/openrisc/kernel/entry.S

   1 /*
   2  * OpenRISC entry.S
   3  *
   4  * Linux architectural port borrowing liberally from similar works of
   5  * others.  All original copyrights apply as per the original source
   6  * declaration.
   7  *
   8  * Modifications for the OpenRISC architecture:
   9  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  10  * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
  11  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  12  *
  13  *      This program is free software; you can redistribute it and/or
  14  *      modify it under the terms of the GNU General Public License
  15  *      as published by the Free Software Foundation; either version
  16  *      2 of the License, or (at your option) any later version.
  17  */
  18
  19 #include <linux/linkage.h>
  20
  21 #include <asm/processor.h>
  22 #include <asm/unistd.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/errno.h>
  25 #include <asm/spr_defs.h>
  26 #include <asm/page.h>
  27 #include <asm/mmu.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/asm-offsets.h>
  30
  31 #define DISABLE_INTERRUPTS(t1,t2)                       \
  32         l.mfspr t2,r0,SPR_SR                            ;\
  33         l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE))         ;\
  34         l.ori   t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE))      ;\
  35         l.and   t2,t2,t1                                ;\
  36         l.mtspr r0,t2,SPR_SR
  37
  38 #define ENABLE_INTERRUPTS(t1)                           \
  39         l.mfspr t1,r0,SPR_SR                            ;\
  40         l.ori   t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE)         ;\
  41         l.mtspr r0,t1,SPR_SR
  42
  43 /* =========================================================[ macros ]=== */
  44
  45 #ifdef CONFIG_TRACE_IRQFLAGS
  46 /*
  47  * Trace irq on/off creating a stack frame.
  48  */
  49 #define TRACE_IRQS_OP(trace_op)                                 \
  50         l.sw    -8(r1),r2       /* store frame pointer */               ;\
  51         l.sw    -4(r1),r9       /* store return address */              ;\
  52         l.addi  r2,r1,0         /* move sp to fp */                     ;\
  53         l.jal   trace_op                                                ;\
  54          l.addi r1,r1,-8                                                ;\
  55         l.ori   r1,r2,0         /* restore sp */                        ;\
  56         l.lwz   r9,-4(r1)       /* restore return address */            ;\
  57         l.lwz   r2,-8(r1)       /* restore fp */                        ;\
  58 /*
  59  * Trace irq on/off and save registers we need that would otherwise be
  60  * clobbered.
  61  */
  62 #define TRACE_IRQS_SAVE(t1,trace_op)                                    \
  63         l.sw    -12(r1),t1      /* save extra reg */                    ;\
  64         l.sw    -8(r1),r2       /* store frame pointer */               ;\
  65         l.sw    -4(r1),r9       /* store return address */              ;\
  66         l.addi  r2,r1,0         /* move sp to fp */                     ;\
  67         l.jal   trace_op                                                ;\
  68          l.addi r1,r1,-12                                               ;\
  69         l.ori   r1,r2,0         /* restore sp */                        ;\
  70         l.lwz   r9,-4(r1)       /* restore return address */            ;\
  71         l.lwz   r2,-8(r1)       /* restore fp */                        ;\
  72         l.lwz   t1,-12(r1)      /* restore extra reg */
  73
  74 #define TRACE_IRQS_OFF  TRACE_IRQS_OP(trace_hardirqs_off)
  75 #define TRACE_IRQS_ON   TRACE_IRQS_OP(trace_hardirqs_on)
  76 #define TRACE_IRQS_ON_SYSCALL                                           \
  77         TRACE_IRQS_SAVE(r10,trace_hardirqs_on)                          ;\
  78         l.lwz   r3,PT_GPR3(r1)                                          ;\
  79         l.lwz   r4,PT_GPR4(r1)                                          ;\
  80         l.lwz   r5,PT_GPR5(r1)                                          ;\
  81         l.lwz   r6,PT_GPR6(r1)                                          ;\
  82         l.lwz   r7,PT_GPR7(r1)                                          ;\
  83         l.lwz   r8,PT_GPR8(r1)                                          ;\
  84         l.lwz   r11,PT_GPR11(r1)
  85 #define TRACE_IRQS_OFF_ENTRY                                            \
  86         l.lwz   r5,PT_SR(r1)                                            ;\
  87         l.andi  r3,r5,(SPR_SR_IEE|SPR_SR_TEE)                           ;\
  88         l.sfeq  r5,r0           /* skip trace if irqs were already off */;\
  89         l.bf    1f                                                      ;\
  90          l.nop                                                          ;\
  91         TRACE_IRQS_SAVE(r4,trace_hardirqs_off)                          ;\
  92 1:
  93 #else
  94 #define TRACE_IRQS_OFF
  95 #define TRACE_IRQS_ON
  96 #define TRACE_IRQS_OFF_ENTRY
  97 #define TRACE_IRQS_ON_SYSCALL
  98 #endif
  99
 100 /*
 101  * We need to disable interrupts at beginning of RESTORE_ALL
 102  * since interrupt might come in after we've loaded EPC return address
 103  * and overwrite EPC with address somewhere in RESTORE_ALL
 104  * which is of course wrong!
 105  */
 106
 107 #define RESTORE_ALL                                             \
 108         DISABLE_INTERRUPTS(r3,r4)                               ;\
 109         l.lwz   r3,PT_PC(r1)                                    ;\
 110         l.mtspr r0,r3,SPR_EPCR_BASE                             ;\
 111         l.lwz   r3,PT_SR(r1)                                    ;\
 112         l.mtspr r0,r3,SPR_ESR_BASE                              ;\
 113         l.lwz   r2,PT_GPR2(r1)                                  ;\
 114         l.lwz   r3,PT_GPR3(r1)                                  ;\
 115         l.lwz   r4,PT_GPR4(r1)                                  ;\
 116         l.lwz   r5,PT_GPR5(r1)                                  ;\
 117         l.lwz   r6,PT_GPR6(r1)                                  ;\
 118         l.lwz   r7,PT_GPR7(r1)                                  ;\
 119         l.lwz   r8,PT_GPR8(r1)                                  ;\
 120         l.lwz   r9,PT_GPR9(r1)                                  ;\
 121         l.lwz   r10,PT_GPR10(r1)                                        ;\
 122         l.lwz   r11,PT_GPR11(r1)                                        ;\
 123         l.lwz   r12,PT_GPR12(r1)                                        ;\
 124         l.lwz   r13,PT_GPR13(r1)                                        ;\
 125         l.lwz   r14,PT_GPR14(r1)                                        ;\
 126         l.lwz   r15,PT_GPR15(r1)                                        ;\
 127         l.lwz   r16,PT_GPR16(r1)                                        ;\
 128         l.lwz   r17,PT_GPR17(r1)                                        ;\
 129         l.lwz   r18,PT_GPR18(r1)                                        ;\
 130         l.lwz   r19,PT_GPR19(r1)                                        ;\
 131         l.lwz   r20,PT_GPR20(r1)                                        ;\
 132         l.lwz   r21,PT_GPR21(r1)                                        ;\
 133         l.lwz   r22,PT_GPR22(r1)                                        ;\
 134         l.lwz   r23,PT_GPR23(r1)                                        ;\
 135         l.lwz   r24,PT_GPR24(r1)                                        ;\
 136         l.lwz   r25,PT_GPR25(r1)                                        ;\
 137         l.lwz   r26,PT_GPR26(r1)                                        ;\
 138         l.lwz   r27,PT_GPR27(r1)                                        ;\
 139         l.lwz   r28,PT_GPR28(r1)                                        ;\
 140         l.lwz   r29,PT_GPR29(r1)                                        ;\
 141         l.lwz   r30,PT_GPR30(r1)                                        ;\
 142         l.lwz   r31,PT_GPR31(r1)                                        ;\
 143         l.lwz   r1,PT_SP(r1)                                    ;\
 144         l.rfe
 145
 146
 147 #define EXCEPTION_ENTRY(handler)                                \
 148         .global handler                                         ;\
 149 handler:                                                        ;\
 150         /* r1, EPCR, ESR a already saved */                     ;\
 151         l.sw    PT_GPR2(r1),r2                                  ;\
 152         l.sw    PT_GPR3(r1),r3                                  ;\
 153         /* r4 already save */                                   ;\
 154         l.sw    PT_GPR5(r1),r5                                  ;\
 155         l.sw    PT_GPR6(r1),r6                                  ;\
 156         l.sw    PT_GPR7(r1),r7                                  ;\
 157         l.sw    PT_GPR8(r1),r8                                  ;\
 158         l.sw    PT_GPR9(r1),r9                                  ;\
 159         /* r10 already saved */                                 ;\
 160         l.sw    PT_GPR11(r1),r11                                        ;\
 161         /* r12 already saved */                                 ;\
 162         l.sw    PT_GPR13(r1),r13                                        ;\
 163         l.sw    PT_GPR14(r1),r14                                        ;\
 164         l.sw    PT_GPR15(r1),r15                                        ;\
 165         l.sw    PT_GPR16(r1),r16                                        ;\
 166         l.sw    PT_GPR17(r1),r17                                        ;\
 167         l.sw    PT_GPR18(r1),r18                                        ;\
 168         l.sw    PT_GPR19(r1),r19                                        ;\
 169         l.sw    PT_GPR20(r1),r20                                        ;\
 170         l.sw    PT_GPR21(r1),r21                                        ;\
 171         l.sw    PT_GPR22(r1),r22                                        ;\
 172         l.sw    PT_GPR23(r1),r23                                        ;\
 173         l.sw    PT_GPR24(r1),r24                                        ;\
 174         l.sw    PT_GPR25(r1),r25                                        ;\
 175         l.sw    PT_GPR26(r1),r26                                        ;\
 176         l.sw    PT_GPR27(r1),r27                                        ;\
 177         l.sw    PT_GPR28(r1),r28                                        ;\
 178         l.sw    PT_GPR29(r1),r29                                        ;\
 179         /* r30 already save */                                  ;\
 180 /*        l.sw    PT_GPR30(r1),r30*/                                    ;\
 181         l.sw    PT_GPR31(r1),r31                                        ;\
 182         TRACE_IRQS_OFF_ENTRY                                            ;\
 183         /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
 184         l.addi  r30,r0,-1                                       ;\
 185         l.sw    PT_ORIG_GPR11(r1),r30
 186
 187 #define UNHANDLED_EXCEPTION(handler,vector)                     \
 188         .global handler                                         ;\
 189 handler:                                                        ;\
 190         /* r1, EPCR, ESR already saved */                       ;\
 191         l.sw    PT_GPR2(r1),r2                                  ;\
 192         l.sw    PT_GPR3(r1),r3                                  ;\
 193         l.sw    PT_GPR5(r1),r5                                  ;\
 194         l.sw    PT_GPR6(r1),r6                                  ;\
 195         l.sw    PT_GPR7(r1),r7                                  ;\
 196         l.sw    PT_GPR8(r1),r8                                  ;\
 197         l.sw    PT_GPR9(r1),r9                                  ;\
 198         /* r10 already saved */                                 ;\
 199         l.sw    PT_GPR11(r1),r11                                        ;\
 200         /* r12 already saved */                                 ;\
 201         l.sw    PT_GPR13(r1),r13                                        ;\
 202         l.sw    PT_GPR14(r1),r14                                        ;\
 203         l.sw    PT_GPR15(r1),r15                                        ;\
 204         l.sw    PT_GPR16(r1),r16                                        ;\
 205         l.sw    PT_GPR17(r1),r17                                        ;\
 206         l.sw    PT_GPR18(r1),r18                                        ;\
 207         l.sw    PT_GPR19(r1),r19                                        ;\
 208         l.sw    PT_GPR20(r1),r20                                        ;\
 209         l.sw    PT_GPR21(r1),r21                                        ;\
 210         l.sw    PT_GPR22(r1),r22                                        ;\
 211         l.sw    PT_GPR23(r1),r23                                        ;\
 212         l.sw    PT_GPR24(r1),r24                                        ;\
 213         l.sw    PT_GPR25(r1),r25                                        ;\
 214         l.sw    PT_GPR26(r1),r26                                        ;\
 215         l.sw    PT_GPR27(r1),r27                                        ;\
 216         l.sw    PT_GPR28(r1),r28                                        ;\
 217         l.sw    PT_GPR29(r1),r29                                        ;\
 218         /* r31 already saved */                                 ;\
 219         l.sw    PT_GPR30(r1),r30                                        ;\
 220 /*        l.sw    PT_GPR31(r1),r31      */                              ;\
 221         /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
 222         l.addi  r30,r0,-1                                       ;\
 223         l.sw    PT_ORIG_GPR11(r1),r30                           ;\
 224         l.addi  r3,r1,0                                         ;\
 225         /* r4 is exception EA */                                ;\
 226         l.addi  r5,r0,vector                                    ;\
 227         l.jal   unhandled_exception                             ;\
 228          l.nop                                                  ;\
 229         l.j     _ret_from_exception                             ;\
 230          l.nop
 231
 232 /* clobbers 'reg' */
 233 #define CLEAR_LWA_FLAG(reg)             \
 234         l.movhi reg,hi(lwa_flag)        ;\
 235         l.ori   reg,reg,lo(lwa_flag)    ;\
 236         l.sw    0(reg),r0
 237 /*
 238  * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
 239  *       contain the same values as when exception we're handling
 240  *       occured. in fact they never do. if you need them use
 241  *       values saved on stack (for SPR_EPC, SPR_ESR) or content
 242  *       of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
 243  *       in 'arch/openrisc/kernel/head.S'
 244  */
 245
 246 /* =====================================================[ exceptions] === */
 247
 248 /* ---[ 0x100: RESET exception ]----------------------------------------- */
 249
 250 EXCEPTION_ENTRY(_tng_kernel_start)
 251         l.jal   _start
 252          l.andi r0,r0,0
 253
 254 /* ---[ 0x200: BUS exception ]------------------------------------------- */
 255
 256 EXCEPTION_ENTRY(_bus_fault_handler)
 257         CLEAR_LWA_FLAG(r3)
 258         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 259         l.jal   do_bus_fault
 260          l.addi  r3,r1,0 /* pt_regs */
 261
 262         l.j     _ret_from_exception
 263          l.nop
 264
 265 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
 266 EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
 267         CLEAR_LWA_FLAG(r3)
 268         l.and   r5,r5,r0
 269         l.j     1f
 270          l.nop
 271
 272 EXCEPTION_ENTRY(_data_page_fault_handler)
 273         CLEAR_LWA_FLAG(r3)
 274         /* set up parameters for do_page_fault */
 275         l.ori   r5,r0,0x300                // exception vector
 276 1:
 277         l.addi  r3,r1,0                    // pt_regs
 278         /* r4 set be EXCEPTION_HANDLE */   // effective address of fault
 279
 280 #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
 281         l.lwz   r6,PT_PC(r3)               // address of an offending insn
 282         l.lwz   r6,0(r6)                   // instruction that caused pf
 283
 284         l.srli  r6,r6,26                   // check opcode for jump insn
 285         l.sfeqi r6,0                       // l.j
 286         l.bf    8f
 287         l.sfeqi r6,1                       // l.jal
 288         l.bf    8f
 289         l.sfeqi r6,3                       // l.bnf
 290         l.bf    8f
 291         l.sfeqi r6,4                       // l.bf
 292         l.bf    8f
 293         l.sfeqi r6,0x11                    // l.jr
 294         l.bf    8f
 295         l.sfeqi r6,0x12                    // l.jalr
 296         l.bf    8f
 297          l.nop
 298
 299         l.j     9f
 300          l.nop
 301
 302 8: // offending insn is in delay slot
 303         l.lwz   r6,PT_PC(r3)               // address of an offending insn
 304         l.addi  r6,r6,4
 305         l.lwz   r6,0(r6)                   // instruction that caused pf
 306         l.srli  r6,r6,26                   // get opcode
 307 9: // offending instruction opcode loaded in r6
 308
 309 #else
 310
 311         l.mfspr r6,r0,SPR_SR               // SR
 312         l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
 313         l.sfne  r6,r0                      // exception happened in delay slot
 314         l.bnf   7f
 315          l.lwz  r6,PT_PC(r3)               // address of an offending insn
 316
 317         l.addi  r6,r6,4                    // offending insn is in delay slot
 318 7:
 319         l.lwz   r6,0(r6)                   // instruction that caused pf
 320         l.srli  r6,r6,26                   // check opcode for write access
 321 #endif
 322
 323         l.sfgeui r6,0x33                   // check opcode for write access
 324         l.bnf   1f
 325         l.sfleui r6,0x37
 326         l.bnf   1f
 327         l.ori   r6,r0,0x1                  // write access
 328         l.j     2f
 329          l.nop
 330 1:      l.ori   r6,r0,0x0                  // !write access
 331 2:
 332
 333         /* call fault.c handler in or32/mm/fault.c */
 334         l.jal   do_page_fault
 335          l.nop
 336         l.j     _ret_from_exception
 337          l.nop
 338
 339 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
 340 EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
 341         CLEAR_LWA_FLAG(r3)
 342         l.and   r5,r5,r0
 343         l.j     1f
 344          l.nop
 345
 346 EXCEPTION_ENTRY(_insn_page_fault_handler)
 347         CLEAR_LWA_FLAG(r3)
 348         /* set up parameters for do_page_fault */
 349         l.ori   r5,r0,0x400                // exception vector
 350 1:
 351         l.addi  r3,r1,0                    // pt_regs
 352         /* r4 set be EXCEPTION_HANDLE */   // effective address of fault
 353         l.ori   r6,r0,0x0                  // !write access
 354
 355         /* call fault.c handler in or32/mm/fault.c */
 356         l.jal   do_page_fault
 357          l.nop
 358         l.j     _ret_from_exception
 359          l.nop
 360
 361
 362 /* ---[ 0x500: Timer exception ]----------------------------------------- */
 363
 364 EXCEPTION_ENTRY(_timer_handler)
 365         CLEAR_LWA_FLAG(r3)
 366         l.jal   timer_interrupt
 367          l.addi r3,r1,0 /* pt_regs */
 368
 369         l.j    _ret_from_intr
 370          l.nop
 371
 372 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
 373
 374 EXCEPTION_ENTRY(_alignment_handler)
 375         CLEAR_LWA_FLAG(r3)
 376         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 377         l.jal   do_unaligned_access
 378          l.addi  r3,r1,0 /* pt_regs */
 379
 380         l.j     _ret_from_exception
 381          l.nop
 382
 383 #if 0
 384 EXCEPTION_ENTRY(_alignment_handler)
 385 //        l.mfspr r2,r0,SPR_EEAR_BASE     /* Load the effective address */
 386         l.addi  r2,r4,0
 387 //        l.mfspr r5,r0,SPR_EPCR_BASE     /* Load the insn address */
 388         l.lwz   r5,PT_PC(r1)
 389
 390         l.lwz   r3,0(r5)                /* Load insn */
 391         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 392
 393         l.sfeqi r4,0x00                 /* Check if the load/store insn is in delay slot */
 394         l.bf    jmp
 395         l.sfeqi r4,0x01
 396         l.bf    jmp
 397         l.sfeqi r4,0x03
 398         l.bf    jmp
 399         l.sfeqi r4,0x04
 400         l.bf    jmp
 401         l.sfeqi r4,0x11
 402         l.bf    jr
 403         l.sfeqi r4,0x12
 404         l.bf    jr
 405         l.nop
 406         l.j     1f
 407         l.addi  r5,r5,4                 /* Increment PC to get return insn address */
 408
 409 jmp:
 410         l.slli  r4,r3,6                 /* Get the signed extended jump length */
 411         l.srai  r4,r4,4
 412
 413         l.lwz   r3,4(r5)                /* Load the real load/store insn */
 414
 415         l.add   r5,r5,r4                /* Calculate jump target address */
 416
 417         l.j     1f
 418         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 419
 420 jr:
 421         l.slli  r4,r3,9                 /* Shift to get the reg nb */
 422         l.andi  r4,r4,0x7c
 423
 424         l.lwz   r3,4(r5)                /* Load the real load/store insn */
 425
 426         l.add   r4,r4,r1                /* Load the jump register value from the stack */
 427         l.lwz   r5,0(r4)
 428
 429         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 430
 431
 432 1:
 433 //        l.mtspr r0,r5,SPR_EPCR_BASE
 434         l.sw    PT_PC(r1),r5
 435
 436         l.sfeqi r4,0x26
 437         l.bf    lhs
 438         l.sfeqi r4,0x25
 439         l.bf    lhz
 440         l.sfeqi r4,0x22
 441         l.bf    lws
 442         l.sfeqi r4,0x21
 443         l.bf    lwz
 444         l.sfeqi r4,0x37
 445         l.bf    sh
 446         l.sfeqi r4,0x35
 447         l.bf    sw
 448         l.nop
 449
 450 1:      l.j     1b                      /* I don't know what to do */
 451         l.nop
 452
 453 lhs:    l.lbs   r5,0(r2)
 454         l.slli  r5,r5,8
 455         l.lbz   r6,1(r2)
 456         l.or    r5,r5,r6
 457         l.srli  r4,r3,19
 458         l.andi  r4,r4,0x7c
 459         l.add   r4,r4,r1
 460         l.j     align_end
 461         l.sw    0(r4),r5
 462
 463 lhz:    l.lbz   r5,0(r2)
 464         l.slli  r5,r5,8
 465         l.lbz   r6,1(r2)
 466         l.or    r5,r5,r6
 467         l.srli  r4,r3,19
 468         l.andi  r4,r4,0x7c
 469         l.add   r4,r4,r1
 470         l.j     align_end
 471         l.sw    0(r4),r5
 472
 473 lws:    l.lbs   r5,0(r2)
 474         l.slli  r5,r5,24
 475         l.lbz   r6,1(r2)
 476         l.slli  r6,r6,16
 477         l.or    r5,r5,r6
 478         l.lbz   r6,2(r2)
 479         l.slli  r6,r6,8
 480         l.or    r5,r5,r6
 481         l.lbz   r6,3(r2)
 482         l.or    r5,r5,r6
 483         l.srli  r4,r3,19
 484         l.andi  r4,r4,0x7c
 485         l.add   r4,r4,r1
 486         l.j     align_end
 487         l.sw    0(r4),r5
 488
 489 lwz:    l.lbz   r5,0(r2)
 490         l.slli  r5,r5,24
 491         l.lbz   r6,1(r2)
 492         l.slli  r6,r6,16
 493         l.or    r5,r5,r6
 494         l.lbz   r6,2(r2)
 495         l.slli  r6,r6,8
 496         l.or    r5,r5,r6
 497         l.lbz   r6,3(r2)
 498         l.or    r5,r5,r6
 499         l.srli  r4,r3,19
 500         l.andi  r4,r4,0x7c
 501         l.add   r4,r4,r1
 502         l.j     align_end
 503         l.sw    0(r4),r5
 504
 505 sh:
 506         l.srli  r4,r3,9
 507         l.andi  r4,r4,0x7c
 508         l.add   r4,r4,r1
 509         l.lwz   r5,0(r4)
 510         l.sb    1(r2),r5
 511         l.srli  r5,r5,8
 512         l.j     align_end
 513         l.sb    0(r2),r5
 514
 515 sw:
 516         l.srli  r4,r3,9
 517         l.andi  r4,r4,0x7c
 518         l.add   r4,r4,r1
 519         l.lwz   r5,0(r4)
 520         l.sb    3(r2),r5
 521         l.srli  r5,r5,8
 522         l.sb    2(r2),r5
 523         l.srli  r5,r5,8
 524         l.sb    1(r2),r5
 525         l.srli  r5,r5,8
 526         l.j     align_end
 527         l.sb    0(r2),r5
 528
 529 align_end:
 530         l.j    _ret_from_intr
 531         l.nop
 532 #endif
 533
 534 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
 535
 536 EXCEPTION_ENTRY(_illegal_instruction_handler)
 537         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 538         l.jal   do_illegal_instruction
 539          l.addi  r3,r1,0 /* pt_regs */
 540
 541         l.j     _ret_from_exception
 542          l.nop
 543
 544 /* ---[ 0x800: External interrupt exception ]---------------------------- */
 545
 546 EXCEPTION_ENTRY(_external_irq_handler)
 547 #ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
 548         l.lwz   r4,PT_SR(r1)            // were interrupts enabled ?
 549         l.andi  r4,r4,SPR_SR_IEE
 550         l.sfeqi r4,0
 551         l.bnf   1f                      // ext irq enabled, all ok.
 552         l.nop
 553
 554 #ifdef CONFIG_PRINTK
 555         l.addi  r1,r1,-0x8
 556         l.movhi r3,hi(42f)
 557         l.ori   r3,r3,lo(42f)
 558         l.sw    0x0(r1),r3
 559         l.jal   printk
 560         l.sw    0x4(r1),r4
 561         l.addi  r1,r1,0x8
 562
 563         .section .rodata, "a"
 564 42:
 565                 .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
 566                 .align 4
 567         .previous
 568 #endif
 569
 570         l.ori   r4,r4,SPR_SR_IEE        // fix the bug
 571 //      l.sw    PT_SR(r1),r4
 572 1:
 573 #endif
 574         CLEAR_LWA_FLAG(r3)
 575         l.addi  r3,r1,0
 576         l.movhi r8,hi(do_IRQ)
 577         l.ori   r8,r8,lo(do_IRQ)
 578         l.jalr r8
 579         l.nop
 580         l.j    _ret_from_intr
 581         l.nop
 582
 583 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
 584
 585
 586 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
 587
 588
 589 /* ---[ 0xb00: Range exception ]----------------------------------------- */
 590
 591 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
 592
 593 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
 594
 595 /*
 596  * Syscalls are a special type of exception in that they are
 597  * _explicitly_ invoked by userspace and can therefore be
 598  * held to conform to the same ABI as normal functions with
 599  * respect to whether registers are preserved across the call
 600  * or not.
 601  */
 602
 603 /* Upon syscall entry we just save the callee-saved registers
 604  * and not the call-clobbered ones.
 605  */
 606
 607 _string_syscall_return:
 608         .string "syscall return %ld \n\r\0"
 609         .align 4
 610
 611 ENTRY(_sys_call_handler)
 612         /* r1, EPCR, ESR a already saved */
 613         l.sw    PT_GPR2(r1),r2
 614         /* r3-r8 must be saved because syscall restart relies
 615          * on us being able to restart the syscall args... technically
 616          * they should be clobbered, otherwise
 617          */
 618         l.sw    PT_GPR3(r1),r3
 619         /*
 620          * r4 already saved
 621          * r4 holds the EEAR address of the fault, use it as screatch reg and
 622          * then load the original r4
 623          */
 624         CLEAR_LWA_FLAG(r4)
 625         l.lwz   r4,PT_GPR4(r1)
 626         l.sw    PT_GPR5(r1),r5
 627         l.sw    PT_GPR6(r1),r6
 628         l.sw    PT_GPR7(r1),r7
 629         l.sw    PT_GPR8(r1),r8
 630         l.sw    PT_GPR9(r1),r9
 631         /* r10 already saved */
 632         l.sw    PT_GPR11(r1),r11
 633         /* orig_gpr11 must be set for syscalls */
 634         l.sw    PT_ORIG_GPR11(r1),r11
 635         /* r12,r13 already saved */
 636
 637         /* r14-r28 (even) aren't touched by the syscall fast path below
 638          * so we don't need to save them.  However, the functions that return
 639          * to userspace via a call to switch() DO need to save these because
 640          * switch() effectively clobbers them... saving these registers for
 641          * such functions is handled in their syscall wrappers (see fork, vfork,
 642          * and clone, below).
 643
 644         /* r30 is the only register we clobber in the fast path */
 645         /* r30 already saved */
 646 /*      l.sw    PT_GPR30(r1),r30 */
 647
 648 _syscall_check_trace_enter:
 649         /* syscalls run with interrupts enabled */
 650         TRACE_IRQS_ON_SYSCALL
 651         ENABLE_INTERRUPTS(r29)          // enable interrupts, r29 is temp
 652
 653         /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
 654         l.lwz   r30,TI_FLAGS(r10)
 655         l.andi  r30,r30,_TIF_SYSCALL_TRACE
 656         l.sfne  r30,r0
 657         l.bf    _syscall_trace_enter
 658          l.nop
 659
 660 _syscall_check:
 661         /* Ensure that the syscall number is reasonable */
 662         l.sfgeui r11,__NR_syscalls
 663         l.bf    _syscall_badsys
 664          l.nop
 665
 666 _syscall_call:
 667         l.movhi r29,hi(sys_call_table)
 668         l.ori   r29,r29,lo(sys_call_table)
 669         l.slli  r11,r11,2
 670         l.add   r29,r29,r11
 671         l.lwz   r29,0(r29)
 672
 673         l.jalr  r29
 674          l.nop
 675
 676 _syscall_return:
 677         /* All syscalls return here... just pay attention to ret_from_fork
 678          * which does it in a round-about way.
 679          */
 680         l.sw    PT_GPR11(r1),r11           // save return value
 681
 682 #if 0
 683 _syscall_debug:
 684         l.movhi r3,hi(_string_syscall_return)
 685         l.ori   r3,r3,lo(_string_syscall_return)
 686         l.ori   r27,r0,1
 687         l.sw    -4(r1),r27
 688         l.sw    -8(r1),r11
 689         l.addi  r1,r1,-8
 690         l.movhi r27,hi(printk)
 691         l.ori   r27,r27,lo(printk)
 692         l.jalr  r27
 693          l.nop
 694         l.addi  r1,r1,8
 695 #endif
 696
 697 _syscall_check_trace_leave:
 698         /* r30 is a callee-saved register so this should still hold the
 699          * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
 700          * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
 701          */
 702         l.sfne  r30,r0
 703         l.bf    _syscall_trace_leave
 704          l.nop
 705
 706 /* This is where the exception-return code begins... interrupts need to be
 707  * disabled the rest of the way here because we can't afford to miss any
 708  * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
 709
 710 _syscall_check_work:
 711         /* Here we need to disable interrupts */
 712         DISABLE_INTERRUPTS(r27,r29)
 713         TRACE_IRQS_OFF
 714         l.lwz   r30,TI_FLAGS(r10)
 715         l.andi  r30,r30,_TIF_WORK_MASK
 716         l.sfne  r30,r0
 717
 718         l.bnf   _syscall_resume_userspace
 719          l.nop
 720
 721         /* Work pending follows a different return path, so we need to
 722          * make sure that all the call-saved registers get into pt_regs
 723          * before branching...
 724          */
 725         l.sw    PT_GPR14(r1),r14
 726         l.sw    PT_GPR16(r1),r16
 727         l.sw    PT_GPR18(r1),r18
 728         l.sw    PT_GPR20(r1),r20
 729         l.sw    PT_GPR22(r1),r22
 730         l.sw    PT_GPR24(r1),r24
 731         l.sw    PT_GPR26(r1),r26
 732         l.sw    PT_GPR28(r1),r28
 733
 734         /* _work_pending needs to be called with interrupts disabled */
 735         l.j     _work_pending
 736          l.nop
 737
 738 _syscall_resume_userspace:
 739 //      ENABLE_INTERRUPTS(r29)
 740
 741
 742 /* This is the hot path for returning to userspace from a syscall.  If there's
 743  * work to be done and the branch to _work_pending was taken above, then the
 744  * return to userspace will be done via the normal exception return path...
 745  * that path restores _all_ registers and will overwrite the "clobbered"
 746  * registers with whatever garbage is in pt_regs -- that's OK because those
 747  * registers are clobbered anyway and because the extra work is insignificant
 748  * in the context of the extra work that _work_pending is doing.
 749
 750 /* Once again, syscalls are special and only guarantee to preserve the
 751  * same registers as a normal function call */
 752
 753 /* The assumption here is that the registers r14-r28 (even) are untouched and
 754  * don't need to be restored... be sure that that's really the case!
 755  */
 756
 757 /* This is still too much... we should only be restoring what we actually
 758  * clobbered... we should even be using 'scratch' (odd) regs above so that
 759  * we don't need to restore anything, hardly...
 760  */
 761
 762         l.lwz   r2,PT_GPR2(r1)
 763
 764         /* Restore args */
 765         /* r3-r8 are technically clobbered, but syscall restart needs these
 766          * to be restored...
 767          */
 768         l.lwz   r3,PT_GPR3(r1)
 769         l.lwz   r4,PT_GPR4(r1)
 770         l.lwz   r5,PT_GPR5(r1)
 771         l.lwz   r6,PT_GPR6(r1)
 772         l.lwz   r7,PT_GPR7(r1)
 773         l.lwz   r8,PT_GPR8(r1)
 774
 775         l.lwz   r9,PT_GPR9(r1)
 776         l.lwz   r10,PT_GPR10(r1)
 777         l.lwz   r11,PT_GPR11(r1)
 778
 779         /* r30 is the only register we clobber in the fast path */
 780         l.lwz   r30,PT_GPR30(r1)
 781
 782         /* Here we use r13-r19 (odd) as scratch regs */
 783         l.lwz   r13,PT_PC(r1)
 784         l.lwz   r15,PT_SR(r1)
 785         l.lwz   r1,PT_SP(r1)
 786         /* Interrupts need to be disabled for setting EPCR and ESR
 787          * so that another interrupt doesn't come in here and clobber
 788          * them before we can use them for our l.rfe */
 789         DISABLE_INTERRUPTS(r17,r19)
 790         l.mtspr r0,r13,SPR_EPCR_BASE
 791         l.mtspr r0,r15,SPR_ESR_BASE
 792         l.rfe
 793
 794 /* End of hot path!
 795  * Keep the below tracing and error handling out of the hot path...
 796 */
 797
 798 _syscall_trace_enter:
 799         /* Here we pass pt_regs to do_syscall_trace_enter.  Make sure
 800          * that function is really getting all the info it needs as
 801          * pt_regs isn't a complete set of userspace regs, just the
 802          * ones relevant to the syscall...
 803          *
 804          * Note use of delay slot for setting argument.
 805          */
 806         l.jal   do_syscall_trace_enter
 807          l.addi r3,r1,0
 808
 809         /* Restore arguments (not preserved across do_syscall_trace_enter)
 810          * so that we can do the syscall for real and return to the syscall
 811          * hot path.
 812          */
 813         l.lwz   r11,PT_GPR11(r1)
 814         l.lwz   r3,PT_GPR3(r1)
 815         l.lwz   r4,PT_GPR4(r1)
 816         l.lwz   r5,PT_GPR5(r1)
 817         l.lwz   r6,PT_GPR6(r1)
 818         l.lwz   r7,PT_GPR7(r1)
 819
 820         l.j     _syscall_check
 821          l.lwz  r8,PT_GPR8(r1)
 822
 823 _syscall_trace_leave:
 824         l.jal   do_syscall_trace_leave
 825          l.addi r3,r1,0
 826
 827         l.j     _syscall_check_work
 828          l.nop
 829
 830 _syscall_badsys:
 831         /* Here we effectively pretend to have executed an imaginary
 832          * syscall that returns -ENOSYS and then return to the regular
 833          * syscall hot path.
 834          * Note that "return value" is set in the delay slot...
 835          */
 836         l.j     _syscall_return
 837          l.addi r11,r0,-ENOSYS
 838
 839 /******* END SYSCALL HANDLING *******/
 840
 841 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
 842
 843 UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
 844
 845 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
 846
 847 EXCEPTION_ENTRY(_trap_handler)
 848         CLEAR_LWA_FLAG(r3)
 849         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 850         l.jal   do_trap
 851          l.addi  r3,r1,0 /* pt_regs */
 852
 853         l.j     _ret_from_exception
 854          l.nop
 855
 856 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
 857
 858 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
 859
 860 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
 861
 862 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
 863
 864 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
 865
 866 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
 867
 868 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
 869
 870 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
 871
 872 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
 873
 874 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
 875
 876 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
 877
 878 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
 879
 880 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
 881
 882 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
 883
 884 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
 885
 886 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
 887
 888 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
 889
 890 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
 891
 892 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
 893
 894 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
 895
 896 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
 897
 898 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
 899
 900 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
 901
 902 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
 903
 904 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
 905
 906 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
 907
 908 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
 909
 910 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
 911
 912 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
 913
 914 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
 915
 916 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
 917
 918 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
 919
 920 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
 921
 922 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
 923
 924 /* ========================================================[ return ] === */
 925
 926 _resume_userspace:
 927         DISABLE_INTERRUPTS(r3,r4)
 928         TRACE_IRQS_OFF
 929         l.lwz   r4,TI_FLAGS(r10)
 930         l.andi  r13,r4,_TIF_WORK_MASK
 931         l.sfeqi r13,0
 932         l.bf    _restore_all
 933          l.nop
 934
 935 _work_pending:
 936         l.lwz   r5,PT_ORIG_GPR11(r1)
 937         l.sfltsi r5,0
 938         l.bnf   1f
 939          l.nop
 940         l.andi  r5,r5,0
 941 1:
 942         l.jal   do_work_pending
 943          l.ori  r3,r1,0                 /* pt_regs */
 944
 945         l.sfeqi r11,0
 946         l.bf    _restore_all
 947          l.nop
 948         l.sfltsi r11,0
 949         l.bnf   1f
 950          l.nop
 951         l.and   r11,r11,r0
 952         l.ori   r11,r11,__NR_restart_syscall
 953         l.j     _syscall_check_trace_enter
 954          l.nop
 955 1:
 956         l.lwz   r11,PT_ORIG_GPR11(r1)
 957         /* Restore arg registers */
 958         l.lwz   r3,PT_GPR3(r1)
 959         l.lwz   r4,PT_GPR4(r1)
 960         l.lwz   r5,PT_GPR5(r1)
 961         l.lwz   r6,PT_GPR6(r1)
 962         l.lwz   r7,PT_GPR7(r1)
 963         l.j     _syscall_check_trace_enter
 964          l.lwz  r8,PT_GPR8(r1)
 965
 966 _restore_all:
 967 #ifdef CONFIG_TRACE_IRQFLAGS
 968         l.lwz   r4,PT_SR(r1)
 969         l.andi  r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
 970         l.sfeq  r3,r0           /* skip trace if irqs were off */
 971         l.bf    skip_hardirqs_on
 972          l.nop
 973         TRACE_IRQS_ON
 974 skip_hardirqs_on:
 975 #endif
 976         RESTORE_ALL
 977         /* This returns to userspace code */
 978
 979
 980 ENTRY(_ret_from_intr)
 981 ENTRY(_ret_from_exception)
 982         l.lwz   r4,PT_SR(r1)
 983         l.andi  r3,r4,SPR_SR_SM
 984         l.sfeqi r3,0
 985         l.bnf   _restore_all
 986          l.nop
 987         l.j     _resume_userspace
 988          l.nop
 989
 990 ENTRY(ret_from_fork)
 991         l.jal   schedule_tail
 992          l.nop
 993
 994         /* Check if we are a kernel thread */
 995         l.sfeqi r20,0
 996         l.bf    1f
 997          l.nop
 998
 999         /* ...we are a kernel thread so invoke the requested callback */
1000         l.jalr  r20
1001          l.or   r3,r22,r0
1002
1003 1:
1004         /* _syscall_returns expect r11 to contain return value */
1005         l.lwz   r11,PT_GPR11(r1)
1006
1007         /* The syscall fast path return expects call-saved registers
1008          * r12-r28 to be untouched, so we restore them here as they
1009          * will have been effectively clobbered when arriving here
1010          * via the call to switch()
1011          */
1012         l.lwz   r12,PT_GPR12(r1)
1013         l.lwz   r14,PT_GPR14(r1)
1014         l.lwz   r16,PT_GPR16(r1)
1015         l.lwz   r18,PT_GPR18(r1)
1016         l.lwz   r20,PT_GPR20(r1)
1017         l.lwz   r22,PT_GPR22(r1)
1018         l.lwz   r24,PT_GPR24(r1)
1019         l.lwz   r26,PT_GPR26(r1)
1020         l.lwz   r28,PT_GPR28(r1)
1021
1022         l.j     _syscall_return
1023          l.nop
1024
1025 /* ========================================================[ switch ] === */
1026
1027 /*
1028  * This routine switches between two different tasks.  The process
1029  * state of one is saved on its kernel stack.  Then the state
1030  * of the other is restored from its kernel stack.  The memory
1031  * management hardware is updated to the second process's state.
1032  * Finally, we can return to the second process, via the 'return'.
1033  *
1034  * Note: there are two ways to get to the "going out" portion
1035  * of this code; either by coming in via the entry (_switch)
1036  * or via "fork" which must set up an environment equivalent
1037  * to the "_switch" path.  If you change this (or in particular, the
1038  * SAVE_REGS macro), you'll have to change the fork code also.
1039  */
1040
1041
1042 /* _switch MUST never lay on page boundry, cause it runs from
1043  * effective addresses and beeing interrupted by iTLB miss would kill it.
1044  * dTLB miss seams to never accour in the bad place since data accesses
1045  * are from task structures which are always page aligned.
1046  *
1047  * The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
1048  * register, then load the previous register values and only at the end call
1049  * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
1050  * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
1051  * holds for ESR)
1052  *
1053  * To avoid this problems it is sufficient to align _switch to
1054  * some nice round number smaller than it's size...
1055  */
1056
1057 /* ABI rules apply here... we either enter _switch via schedule() or via
1058  * an imaginary call to which we shall return at return_from_fork.  Either
1059  * way, we are a function call and only need to preserve the callee-saved
1060  * registers when we return.  As such, we don't need to save the registers
1061  * on the stack that we won't be returning as they were...
1062  */
1063
1064         .align 0x400
1065 ENTRY(_switch)
1066         /* We don't store SR as _switch only gets called in a context where
1067          * the SR will be the same going in and coming out... */
1068
1069         /* Set up new pt_regs struct for saving task state */
1070         l.addi  r1,r1,-(INT_FRAME_SIZE)
1071
1072         /* No need to store r1/PT_SP as it goes into KSP below */
1073         l.sw    PT_GPR2(r1),r2
1074         l.sw    PT_GPR9(r1),r9
1075         /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1076          * and expects r12 to be callee-saved... */
1077         l.sw    PT_GPR12(r1),r12
1078         l.sw    PT_GPR14(r1),r14
1079         l.sw    PT_GPR16(r1),r16
1080         l.sw    PT_GPR18(r1),r18
1081         l.sw    PT_GPR20(r1),r20
1082         l.sw    PT_GPR22(r1),r22
1083         l.sw    PT_GPR24(r1),r24
1084         l.sw    PT_GPR26(r1),r26
1085         l.sw    PT_GPR28(r1),r28
1086         l.sw    PT_GPR30(r1),r30
1087
1088         l.addi  r11,r10,0                       /* Save old 'current' to 'last' return value*/
1089
1090         /* We use thread_info->ksp for storing the address of the above
1091          * structure so that we can get back to it later... we don't want
1092          * to lose the value of thread_info->ksp, though, so store it as
1093          * pt_regs->sp so that we can easily restore it when we are made
1094          * live again...
1095          */
1096
1097         /* Save the old value of thread_info->ksp as pt_regs->sp */
1098         l.lwz   r29,TI_KSP(r10)
1099         l.sw    PT_SP(r1),r29
1100
1101         /* Swap kernel stack pointers */
1102         l.sw    TI_KSP(r10),r1                  /* Save old stack pointer */
1103         l.or    r10,r4,r0                       /* Set up new current_thread_info */
1104         l.lwz   r1,TI_KSP(r10)                  /* Load new stack pointer */
1105
1106         /* Restore the old value of thread_info->ksp */
1107         l.lwz   r29,PT_SP(r1)
1108         l.sw    TI_KSP(r10),r29
1109
1110         /* ...and restore the registers, except r11 because the return value
1111          * has already been set above.
1112          */
1113         l.lwz   r2,PT_GPR2(r1)
1114         l.lwz   r9,PT_GPR9(r1)
1115         /* No need to restore r10 */
1116         /* ...and do not restore r11 */
1117
1118         /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1119          * and expects r12 to be callee-saved... */
1120         l.lwz   r12,PT_GPR12(r1)
1121         l.lwz   r14,PT_GPR14(r1)
1122         l.lwz   r16,PT_GPR16(r1)
1123         l.lwz   r18,PT_GPR18(r1)
1124         l.lwz   r20,PT_GPR20(r1)
1125         l.lwz   r22,PT_GPR22(r1)
1126         l.lwz   r24,PT_GPR24(r1)
1127         l.lwz   r26,PT_GPR26(r1)
1128         l.lwz   r28,PT_GPR28(r1)
1129         l.lwz   r30,PT_GPR30(r1)
1130
1131         /* Unwind stack to pre-switch state */
1132         l.addi  r1,r1,(INT_FRAME_SIZE)
1133
1134         /* Return via the link-register back to where we 'came from', where
1135          * that may be either schedule(), ret_from_fork(), or
1136          * ret_from_kernel_thread().  If we are returning to a new thread,
1137          * we are expected to have set up the arg to schedule_tail already,
1138          * hence we do so here unconditionally:
1139          */
1140         l.lwz   r3,TI_TASK(r3)          /* Load 'prev' as schedule_tail arg */
1141         l.jr    r9
1142          l.nop
1143
1144 /* ==================================================================== */
1145
1146 /* These all use the delay slot for setting the argument register, so the
1147  * jump is always happening after the l.addi instruction.
1148  *
1149  * These are all just wrappers that don't touch the link-register r9, so the
1150  * return from the "real" syscall function will return back to the syscall
1151  * code that did the l.jal that brought us here.
1152  */
1153
1154 /* fork requires that we save all the callee-saved registers because they
1155  * are all effectively clobbered by the call to _switch.  Here we store
1156  * all the registers that aren't touched by the syscall fast path and thus
1157  * weren't saved there.
1158  */
1159
1160 _fork_save_extra_regs_and_call:
1161         l.sw    PT_GPR14(r1),r14
1162         l.sw    PT_GPR16(r1),r16
1163         l.sw    PT_GPR18(r1),r18
1164         l.sw    PT_GPR20(r1),r20
1165         l.sw    PT_GPR22(r1),r22
1166         l.sw    PT_GPR24(r1),r24
1167         l.sw    PT_GPR26(r1),r26
1168         l.jr    r29
1169          l.sw    PT_GPR28(r1),r28
1170
1171 ENTRY(__sys_clone)
1172         l.movhi r29,hi(sys_clone)
1173         l.ori   r29,r29,lo(sys_clone)
1174         l.j     _fork_save_extra_regs_and_call
1175          l.nop
1176
1177 ENTRY(__sys_fork)
1178         l.movhi r29,hi(sys_fork)
1179         l.ori   r29,r29,lo(sys_fork)
1180         l.j     _fork_save_extra_regs_and_call
1181          l.nop
1182
1183 ENTRY(sys_rt_sigreturn)
1184         l.jal   _sys_rt_sigreturn
1185          l.addi r3,r1,0
1186         l.sfne  r30,r0
1187         l.bnf   _no_syscall_trace
1188          l.nop
1189         l.jal   do_syscall_trace_leave
1190          l.addi r3,r1,0
1191 _no_syscall_trace:
1192         l.j     _resume_userspace
1193          l.nop
1194
1195 /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1196  * The functions takes a variable number of parameters depending on which
1197  * particular flavour of atomic you want... parameter 1 is a flag identifying
1198  * the atomic in question.  Currently, this function implements the
1199  * following variants:
1200  *
1201  * XCHG:
1202  *  @flag: 1
1203  *  @ptr1:
1204  *  @ptr2:
1205  * Atomically exchange the values in pointers 1 and 2.
1206  *
1207  */
1208
1209 ENTRY(sys_or1k_atomic)
1210         /* FIXME: This ignores r3 and always does an XCHG */
1211         DISABLE_INTERRUPTS(r17,r19)
1212         l.lwz   r29,0(r4)
1213         l.lwz   r27,0(r5)
1214         l.sw    0(r4),r27
1215         l.sw    0(r5),r29
1216         ENABLE_INTERRUPTS(r17)
1217         l.jr    r9
1218          l.or   r11,r0,r0
1219
1220 /* ============================================================[ EOF ]=== */