3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/init.h>
23 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
33 #include <asm/export.h>
35 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
36 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
37 #define SIMPLE_KERNEL_ADDRESS 1
41 * We need an ITLB miss handler for kernel addresses if:
42 * - Either we have modules
43 * - Or we have not pinned the first 8M
45 #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
46 defined(CONFIG_DEBUG_PAGEALLOC)
47 #define ITLB_MISS_KERNEL 1
51 * Value for the bits that have fixed value in RPN entries.
52 * Also used for tagging DAR for DTLBerror.
54 #define RPN_PATTERN 0x00f0
56 #define PAGE_SHIFT_512K 19
57 #define PAGE_SHIFT_8M 23
64 * This port was done on an MBX board with an 860. Right now I only
65 * support an ELF compressed (zImage) boot from EPPC-Bug because the
66 * code there loads up some registers before calling us:
67 * r3: ptr to board info data
68 * r4: initrd_start or if no initrd then 0
69 * r5: initrd_end - unused if r4 is 0
70 * r6: Start of command line string
71 * r7: End of command line string
73 * I decided to use conditional compilation instead of checking PVR and
74 * adding more processor specific branches around code I don't need.
75 * Since this is an embedded processor, I also appreciate any memory
78 * The MPC8xx does not have any BATs, but it supports large page sizes.
79 * We first initialize the MMU to support 8M byte pages, then load one
80 * entry into each of the instruction and data TLBs to map the first
81 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
82 * the "internal" processor registers before MMU_init is called.
88 mr r31,r3 /* save device tree ptr */
90 /* We have to turn on the MMU right away so we get cache modes
95 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
101 ori r0,r0,MSR_DR|MSR_IR
104 ori r0,r0,start_here@l
106 rfi /* enables MMU */
109 * Exception entry code. This code runs with address translation
110 * turned off, i.e. using physical addresses.
111 * We assume sprg3 has the physical address of the current
112 * task's thread_struct.
114 #define EXCEPTION_PROLOG \
115 mtspr SPRN_SPRG_SCRATCH0, r10; \
116 mtspr SPRN_SPRG_SCRATCH1, r11; \
118 EXCEPTION_PROLOG_1; \
121 #define EXCEPTION_PROLOG_1 \
122 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
123 andi. r11,r11,MSR_PR; \
124 tophys(r11,r1); /* use tophys(r1) if kernel */ \
126 mfspr r11,SPRN_SPRG_THREAD; \
127 lwz r11,THREAD_INFO-THREAD(r11); \
128 addi r11,r11,THREAD_SIZE; \
130 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
133 #define EXCEPTION_PROLOG_2 \
134 stw r10,_CCR(r11); /* save registers */ \
135 stw r12,GPR12(r11); \
137 mfspr r10,SPRN_SPRG_SCRATCH0; \
138 stw r10,GPR10(r11); \
139 mfspr r12,SPRN_SPRG_SCRATCH1; \
140 stw r12,GPR11(r11); \
142 stw r10,_LINK(r11); \
143 mfspr r12,SPRN_SRR0; \
144 mfspr r9,SPRN_SRR1; \
147 tovirt(r1,r11); /* set new kernel sp */ \
148 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
151 SAVE_4GPRS(3, r11); \
155 * Note: code which follows this uses cr0.eq (set if from kernel),
156 * r11, r12 (SRR0), and r9 (SRR1).
158 * Note2: once we have set r1 we are in a position to take exceptions
159 * again, and we could thus set MSR:RI at that point.
165 #define EXCEPTION(n, label, hdlr, xfer) \
169 addi r3,r1,STACK_FRAME_OVERHEAD; \
172 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
174 stw r10,_TRAP(r11); \
182 #define COPY_EE(d, s) rlwimi d,s,0,16,16
185 #define EXC_XFER_STD(n, hdlr) \
186 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
187 ret_from_except_full)
189 #define EXC_XFER_LITE(n, hdlr) \
190 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
193 #define EXC_XFER_EE(n, hdlr) \
194 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
195 ret_from_except_full)
197 #define EXC_XFER_EE_LITE(n, hdlr) \
198 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
202 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
211 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
214 addi r3,r1,STACK_FRAME_OVERHEAD
215 EXC_XFER_STD(0x200, machine_check_exception)
217 /* Data access exception.
218 * This is "never generated" by the MPC8xx.
223 /* Instruction access exception.
224 * This is "never generated" by the MPC8xx.
229 /* External interrupt */
230 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
232 /* Alignment exception */
239 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
242 addi r3,r1,STACK_FRAME_OVERHEAD
243 EXC_XFER_EE(0x600, alignment_exception)
245 /* Program check exception */
246 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
248 /* No FPU on MPC8xx. This exception is not supposed to happen.
250 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
253 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
255 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
256 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
262 EXC_XFER_EE_LITE(0xc00, DoSyscall)
264 /* Single step - not used on 601 */
265 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
266 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
267 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
269 /* On the MPC8xx, this is a software emulation interrupt. It occurs
270 * for all unimplemented and illegal instructions.
272 EXCEPTION(0x1000, SoftEmu, emulation_assist_interrupt, EXC_XFER_STD)
276 * For the MPC8xx, this is a software tablewalk to load the instruction
277 * TLB. The task switch loads the M_TW register with the pointer to the first
279 * If we discover there is no second level table (value is zero) or if there
280 * is an invalid pte, we load that into the TLB, which causes another fault
281 * into the TLB Error interrupt where we can handle such problems.
282 * We have to use the MD_xxx registers for the tablewalk because the
283 * equivalent MI_xxx registers only perform the attribute functions.
286 #ifdef CONFIG_8xx_CPU15
287 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
288 addi tmp, addr, PAGE_SIZE; \
290 addi tmp, addr, -PAGE_SIZE; \
293 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
297 mtspr SPRN_SPRG_SCRATCH0, r10
298 mtspr SPRN_SPRG_SCRATCH1, r11
299 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
300 mtspr SPRN_SPRG_SCRATCH2, r12
303 /* If we are faulting a kernel address, we have to use the
304 * kernel page tables.
306 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
307 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
308 /* Only modules will cause ITLB Misses as we always
309 * pin the first 8MB of kernel memory */
310 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
313 #ifdef ITLB_MISS_KERNEL
314 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
315 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
317 rlwinm r11, r10, 16, 0xfff8
318 cmpli cr0, r11, PAGE_OFFSET@h
319 #ifndef CONFIG_PIN_TLB_TEXT
320 /* It is assumed that kernel code fits into the first 8M page */
322 cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h
326 mfspr r11, SPRN_M_TW /* Get level 1 table */
327 #ifdef ITLB_MISS_KERNEL
328 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
333 #ifndef CONFIG_PIN_TLB_TEXT
334 blt cr7, ITLBMissLinear
336 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
339 /* Insert level 1 index */
340 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
341 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
343 /* Extract level 2 index */
344 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
345 #ifdef CONFIG_HUGETLB_PAGE
347 bt- 28, 10f /* bit 28 = Large page (8M) */
348 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
350 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
351 lwz r10, 0(r10) /* Get the pte */
353 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
356 /* Load the MI_TWC with the attributes for this "segment." */
357 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
359 rlwinm r11, r10, 32-7, _PAGE_PRESENT
361 rlwimi r10, r11, 0, _PAGE_PRESENT
362 li r11, RPN_PATTERN | 0x200
363 /* The Linux PTE won't go exactly into the MMU TLB.
364 * Software indicator bits 20 and 23 must be clear.
365 * Software indicator bits 22, 24, 25, 26, and 27 must be
366 * set. All other Linux PTE bits control the behavior
369 rlwimi r11, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
370 rlwimi r10, r11, 0, 0x0ff0 /* Set 22, 24-27, clear 20,23 */
371 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
373 /* Restore registers */
374 _ENTRY(itlb_miss_exit_1)
375 mfspr r10, SPRN_SPRG_SCRATCH0
376 mfspr r11, SPRN_SPRG_SCRATCH1
377 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
378 mfspr r12, SPRN_SPRG_SCRATCH2
381 #ifdef CONFIG_PERF_EVENTS
382 _ENTRY(itlb_miss_perf)
383 lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
384 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
386 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
388 mfspr r10, SPRN_SPRG_SCRATCH0
389 mfspr r11, SPRN_SPRG_SCRATCH1
390 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
391 mfspr r12, SPRN_SPRG_SCRATCH2
395 #ifdef CONFIG_HUGETLB_PAGE
397 #ifdef CONFIG_PPC_16K_PAGES
398 /* Extract level 2 index */
399 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
400 /* Add level 2 base */
401 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
404 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
406 lwz r10, 0(r10) /* Get the pte */
410 /* Extract level 2 index */
411 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
412 /* Add level 2 base */
413 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
414 lwz r10, 0(r10) /* Get the pte */
420 mtspr SPRN_SPRG_SCRATCH0, r10
421 mtspr SPRN_SPRG_SCRATCH1, r11
422 mtspr SPRN_SPRG_SCRATCH2, r12
425 /* If we are faulting a kernel address, we have to use the
426 * kernel page tables.
428 mfspr r10, SPRN_MD_EPN
429 rlwinm r11, r10, 16, 0xfff8
430 cmpli cr0, r11, PAGE_OFFSET@h
431 mfspr r11, SPRN_M_TW /* Get level 1 table */
433 rlwinm r11, r10, 16, 0xfff8
434 #ifndef CONFIG_PIN_TLB_IMMR
435 cmpli cr0, r11, VIRT_IMMR_BASE@h
438 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
439 #ifndef CONFIG_PIN_TLB_IMMR
443 blt cr7, DTLBMissLinear
444 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
447 /* Insert level 1 index */
448 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
449 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
451 /* We have a pte table, so load fetch the pte from the table.
453 /* Extract level 2 index */
454 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
455 #ifdef CONFIG_HUGETLB_PAGE
457 bt- 28, 10f /* bit 28 = Large page (8M) */
458 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
460 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
461 lwz r10, 0(r10) /* Get the pte */
465 /* Insert the Guarded flag into the TWC from the Linux PTE.
466 * It is bit 27 of both the Linux PTE and the TWC (at least
467 * I got that right :-). It will be better when we can put
468 * this into the Linux pgd/pmd and load it in the operation
471 rlwimi r11, r10, 0, _PAGE_GUARDED
472 mtspr SPRN_MD_TWC, r11
474 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
475 * We also need to know if the insn is a load/store, so:
476 * Clear _PAGE_PRESENT and load that which will
477 * trap into DTLB Error with store bit set accordinly.
479 /* PRESENT=0x1, ACCESSED=0x20
480 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
481 * r10 = (r10 & ~PRESENT) | r11;
483 rlwinm r11, r10, 32-7, _PAGE_PRESENT
485 rlwimi r10, r11, 0, _PAGE_PRESENT
486 /* The Linux PTE won't go exactly into the MMU TLB.
487 * Software indicator bits 24, 25, 26, and 27 must be
488 * set. All other Linux PTE bits control the behavior
492 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
493 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
495 /* Restore registers */
496 mtspr SPRN_DAR, r11 /* Tag DAR */
497 _ENTRY(dtlb_miss_exit_1)
498 mfspr r10, SPRN_SPRG_SCRATCH0
499 mfspr r11, SPRN_SPRG_SCRATCH1
500 mfspr r12, SPRN_SPRG_SCRATCH2
502 #ifdef CONFIG_PERF_EVENTS
503 _ENTRY(dtlb_miss_perf)
504 lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
505 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
507 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
509 mfspr r10, SPRN_SPRG_SCRATCH0
510 mfspr r11, SPRN_SPRG_SCRATCH1
511 mfspr r12, SPRN_SPRG_SCRATCH2
514 #ifdef CONFIG_HUGETLB_PAGE
516 /* Extract level 2 index */
517 #ifdef CONFIG_PPC_16K_PAGES
518 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
519 /* Add level 2 base */
520 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
523 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
525 lwz r10, 0(r10) /* Get the pte */
529 /* Extract level 2 index */
530 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
531 /* Add level 2 base */
532 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
533 lwz r10, 0(r10) /* Get the pte */
537 /* This is an instruction TLB error on the MPC8xx. This could be due
538 * to many reasons, such as executing guarded memory or illegal instruction
539 * addresses. There is nothing to do but handle a big time error fault.
545 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
546 andis. r10,r9,SRR1_ISI_NOPT@h
550 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
551 1: EXC_XFER_LITE(0x400, handle_page_fault)
553 /* This is the data TLB error on the MPC8xx. This could be due to
554 * many reasons, including a dirty update to a pte. We bail out to
555 * a higher level function that can handle it.
559 mtspr SPRN_SPRG_SCRATCH0, r10
560 mtspr SPRN_SPRG_SCRATCH1, r11
564 cmpwi cr0, r11, RPN_PATTERN
565 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
566 DARFixed:/* Return from dcbx instruction bug workaround */
572 andis. r10,r5,DSISR_NOHPTE@h
576 1: li r10,RPN_PATTERN
577 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
578 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
579 EXC_XFER_LITE(0x300, handle_page_fault)
581 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
582 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
583 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
584 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
585 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
586 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
587 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
589 /* On the MPC8xx, these next four traps are used for development
590 * support of breakpoints and such. Someday I will get around to
595 mtspr SPRN_SPRG_SCRATCH0, r10
596 mtspr SPRN_SPRG_SCRATCH1, r11
599 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
600 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
605 addi r3,r1,STACK_FRAME_OVERHEAD
609 EXC_XFER_EE(0x1c00, do_break)
612 mfspr r10, SPRN_SPRG_SCRATCH0
613 mfspr r11, SPRN_SPRG_SCRATCH1
616 #ifdef CONFIG_PERF_EVENTS
618 InstructionBreakpoint:
619 mtspr SPRN_SPRG_SCRATCH0, r10
620 mtspr SPRN_SPRG_SCRATCH1, r11
621 lis r10, (instruction_counter - PAGE_OFFSET)@ha
622 lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10)
624 stw r11, (instruction_counter - PAGE_OFFSET)@l(r10)
627 mtspr SPRN_COUNTA, r10
628 mfspr r10, SPRN_SPRG_SCRATCH0
629 mfspr r11, SPRN_SPRG_SCRATCH1
632 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
634 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
635 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
640 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.
641 * not enough space in the DataStoreTLBMiss area.
645 /* Set 512k byte guarded page and mark it valid */
646 li r10, MD_PS512K | MD_GUARDED | MD_SVALID
647 mtspr SPRN_MD_TWC, r10
648 mfspr r10, SPRN_IMMR /* Get current IMMR */
649 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
650 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
651 _PAGE_PRESENT | _PAGE_NO_CACHE
652 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
655 mtspr SPRN_DAR, r11 /* Tag DAR */
656 _ENTRY(dtlb_miss_exit_2)
657 mfspr r10, SPRN_SPRG_SCRATCH0
658 mfspr r11, SPRN_SPRG_SCRATCH1
659 mfspr r12, SPRN_SPRG_SCRATCH2
664 /* Set 8M byte page and mark it valid */
665 li r11, MD_PS8MEG | MD_SVALID
666 mtspr SPRN_MD_TWC, r11
667 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
668 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
670 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
673 mtspr SPRN_DAR, r11 /* Tag DAR */
674 _ENTRY(dtlb_miss_exit_3)
675 mfspr r10, SPRN_SPRG_SCRATCH0
676 mfspr r11, SPRN_SPRG_SCRATCH1
677 mfspr r12, SPRN_SPRG_SCRATCH2
680 #ifndef CONFIG_PIN_TLB_TEXT
683 /* Set 8M byte page and mark it valid */
684 li r11, MI_PS8MEG | MI_SVALID
685 mtspr SPRN_MI_TWC, r11
686 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
687 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
689 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
691 _ENTRY(itlb_miss_exit_2)
692 mfspr r10, SPRN_SPRG_SCRATCH0
693 mfspr r11, SPRN_SPRG_SCRATCH1
694 mfspr r12, SPRN_SPRG_SCRATCH2
698 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
699 * by decoding the registers used by the dcbx instruction and adding them.
700 * DAR is set to the calculated address.
702 /* define if you don't want to use self modifying code */
703 #define NO_SELF_MODIFYING_CODE
704 FixupDAR:/* Entry point for dcbx workaround. */
705 mtspr SPRN_SPRG_SCRATCH2, r10
706 /* fetch instruction from memory. */
708 rlwinm r11, r10, 16, 0xfff8
709 cmpli cr0, r11, PAGE_OFFSET@h
710 mfspr r11, SPRN_M_TW /* Get level 1 table */
712 rlwinm r11, r10, 16, 0xfff8
714 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
715 /* create physical page address from effective address */
718 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
719 /* Insert level 1 index */
720 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
721 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
723 bt 28,200f /* bit 28 = Large page (8M) */
724 bt 29,202f /* bit 29 = Large page (8M or 512K) */
725 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
726 /* Insert level 2 index */
727 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
728 lwz r11, 0(r11) /* Get the pte */
729 /* concat physical page address(r11) and page offset(r10) */
730 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
732 /* Check if it really is a dcbx instruction. */
733 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
734 * no need to include them here */
735 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
736 rlwinm r10, r10, 0, 21, 5
737 cmpwi cr0, r10, 2028 /* Is dcbz? */
739 cmpwi cr0, r10, 940 /* Is dcbi? */
741 cmpwi cr0, r10, 108 /* Is dcbst? */
742 beq+ 144f /* Fix up store bit! */
743 cmpwi cr0, r10, 172 /* Is dcbf? */
745 cmpwi cr0, r10, 1964 /* Is icbi? */
747 141: mfspr r10,SPRN_SPRG_SCRATCH2
748 b DARFixed /* Nope, go back to normal TLB processing */
750 /* concat physical page address(r11) and page offset(r10) */
752 #ifdef CONFIG_PPC_16K_PAGES
753 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
754 rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
756 rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK
758 lwz r11, 0(r11) /* Get the pte */
759 /* concat physical page address(r11) and page offset(r10) */
760 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
764 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
765 rlwimi r11, r10, 32 - (PAGE_SHIFT_512K - 2), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
766 lwz r11, 0(r11) /* Get the pte */
767 /* concat physical page address(r11) and page offset(r10) */
768 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
771 144: mfspr r10, SPRN_DSISR
772 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
773 mtspr SPRN_DSISR, r10
774 142: /* continue, it was a dcbx, dcbi instruction. */
775 #ifndef NO_SELF_MODIFYING_CODE
776 andis. r10,r11,0x1f /* test if reg RA is r0 */
777 li r10,modified_instr@l
778 dcbtst r0,r10 /* touch for store */
779 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
780 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
782 stw r11,0(r10) /* store add/and instruction */
783 dcbf 0,r10 /* flush new instr. to memory. */
784 icbi 0,r10 /* invalidate instr. cache line */
785 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
786 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
787 isync /* Wait until new instr is loaded from memory */
789 .space 4 /* this is where the add instr. is stored */
791 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
792 143: mtdar r10 /* store faulting EA in DAR */
793 mfspr r10,SPRN_SPRG_SCRATCH2
794 b DARFixed /* Go back to normal TLB handling */
797 mtdar r10 /* save ctr reg in DAR */
798 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
799 addi r10, r10, 150f@l /* add start of table */
800 mtctr r10 /* load ctr with jump address */
801 xor r10, r10, r10 /* sum starts at zero */
802 bctr /* jump into table */
804 add r10, r10, r0 ;b 151f
805 add r10, r10, r1 ;b 151f
806 add r10, r10, r2 ;b 151f
807 add r10, r10, r3 ;b 151f
808 add r10, r10, r4 ;b 151f
809 add r10, r10, r5 ;b 151f
810 add r10, r10, r6 ;b 151f
811 add r10, r10, r7 ;b 151f
812 add r10, r10, r8 ;b 151f
813 add r10, r10, r9 ;b 151f
814 mtctr r11 ;b 154f /* r10 needs special handling */
815 mtctr r11 ;b 153f /* r11 needs special handling */
816 add r10, r10, r12 ;b 151f
817 add r10, r10, r13 ;b 151f
818 add r10, r10, r14 ;b 151f
819 add r10, r10, r15 ;b 151f
820 add r10, r10, r16 ;b 151f
821 add r10, r10, r17 ;b 151f
822 add r10, r10, r18 ;b 151f
823 add r10, r10, r19 ;b 151f
824 add r10, r10, r20 ;b 151f
825 add r10, r10, r21 ;b 151f
826 add r10, r10, r22 ;b 151f
827 add r10, r10, r23 ;b 151f
828 add r10, r10, r24 ;b 151f
829 add r10, r10, r25 ;b 151f
830 add r10, r10, r26 ;b 151f
831 add r10, r10, r27 ;b 151f
832 add r10, r10, r28 ;b 151f
833 add r10, r10, r29 ;b 151f
834 add r10, r10, r30 ;b 151f
837 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
838 beq 152f /* if reg RA is zero, don't add it */
839 addi r11, r11, 150b@l /* add start of table */
840 mtctr r11 /* load ctr with jump address */
841 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
842 bctr /* jump into table */
845 mtctr r11 /* restore ctr reg from DAR */
846 mtdar r10 /* save fault EA to DAR */
847 mfspr r10,SPRN_SPRG_SCRATCH2
848 b DARFixed /* Go back to normal TLB handling */
850 /* special handling for r10,r11 since these are modified already */
851 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
852 add r10, r10, r11 /* add it */
853 mfctr r11 /* restore r11 */
855 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
856 add r10, r10, r11 /* add it */
857 mfctr r11 /* restore r11 */
862 * This is where the main kernel code starts.
867 ori r2,r2,init_task@l
869 /* ptr to phys current thread */
871 addi r4,r4,THREAD /* init task's THREAD */
872 mtspr SPRN_SPRG_THREAD,r4
875 lis r1,init_thread_union@ha
876 addi r1,r1,init_thread_union@l
878 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
880 lis r6, swapper_pg_dir@ha
884 bl early_init /* We have to do this with MMU on */
887 * Decide what sort of machine this is and initialize the MMU.
895 * Go back to running unmapped so we can load up new values
896 * and change to using our exception vectors.
897 * On the 8xx, all we have to do is invalidate the TLB to clear
898 * the old 8M byte TLB mappings and load the page table base register.
900 /* The right way to do this would be to track it down through
901 * init's THREAD like the context switch code does, but this is
902 * easier......until someone changes init's static structures.
907 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
911 /* Load up the kernel context */
913 tlbia /* Clear all TLB entries */
914 sync /* wait for tlbia/tlbie to finish */
916 /* set up the PTE pointers for the Abatron bdiGDB.
918 lis r5, abatron_pteptrs@h
919 ori r5, r5, abatron_pteptrs@l
920 stw r5, 0xf0(0) /* Must match your Abatron config file */
922 lis r6, swapper_pg_dir@h
923 ori r6, r6, swapper_pg_dir@l
926 /* Now turn on the MMU for real! */
928 lis r3,start_kernel@h
929 ori r3,r3,start_kernel@l
932 rfi /* enable MMU and jump to start_kernel */
934 /* Set up the initial MMU state so we can do the first level of
935 * kernel initialization. This maps the first 8 MBytes of memory 1:1
936 * virtual to physical. Also, set the cache mode since that is defined
937 * by TLB entries and perform any additional mapping (like of the IMMR).
938 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
939 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
940 * these mappings is mapped by page tables.
944 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
945 lis r10, MD_RESETVAL@h
946 #ifndef CONFIG_8xx_COPYBACK
947 oris r10, r10, MD_WTDEF@h
949 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
951 tlbia /* Invalidate all TLB entries */
952 #ifdef CONFIG_PIN_TLB_TEXT
956 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
959 #ifdef CONFIG_PIN_TLB_DATA
960 oris r10, r10, MD_RSV4I@h
961 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
964 /* Now map the lower 8 Meg into the ITLB. */
965 lis r8, KERNELBASE@h /* Create vaddr for TLB */
966 ori r8, r8, MI_EVALID /* Mark it valid */
967 mtspr SPRN_MI_EPN, r8
968 li r8, MI_PS8MEG /* Set 8M byte page */
969 ori r8, r8, MI_SVALID /* Make it valid */
970 mtspr SPRN_MI_TWC, r8
971 li r8, MI_BOOTINIT /* Create RPN for address 0 */
972 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
974 lis r8, MI_APG_INIT@h /* Set protection modes */
975 ori r8, r8, MI_APG_INIT@l
977 lis r8, MD_APG_INIT@h
978 ori r8, r8, MD_APG_INIT@l
981 /* Map a 512k page for the IMMR to get the processor
982 * internal registers (among other things).
984 #ifdef CONFIG_PIN_TLB_IMMR
985 oris r10, r10, MD_RSV4I@h
987 mtspr SPRN_MD_CTR, r10
989 mfspr r9, 638 /* Get current IMMR */
990 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
992 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
993 ori r8, r8, MD_EVALID /* Mark it valid */
994 mtspr SPRN_MD_EPN, r8
995 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
996 ori r8, r8, MD_SVALID /* Make it valid */
997 mtspr SPRN_MD_TWC, r8
998 mr r8, r9 /* Create paddr for TLB */
999 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
1000 mtspr SPRN_MD_RPN, r8
1003 /* Since the cache is enabled according to the information we
1004 * just loaded into the TLB, invalidate and enable the caches here.
1005 * We should probably check/set other modes....later.
1007 lis r8, IDC_INVALL@h
1008 mtspr SPRN_IC_CST, r8
1009 mtspr SPRN_DC_CST, r8
1010 lis r8, IDC_ENABLE@h
1011 mtspr SPRN_IC_CST, r8
1012 #ifdef CONFIG_8xx_COPYBACK
1013 mtspr SPRN_DC_CST, r8
1015 /* For a debug option, I left this here to easily enable
1016 * the write through cache mode
1019 mtspr SPRN_DC_CST, r8
1020 lis r8, IDC_ENABLE@h
1021 mtspr SPRN_DC_CST, r8
1023 /* Disable debug mode entry on breakpoints */
1025 #ifdef CONFIG_PERF_EVENTS
1026 rlwinm r8, r8, 0, ~0xc
1028 rlwinm r8, r8, 0, ~0x8
1035 * We put a few things here that have to be page-aligned.
1036 * This stuff goes at the beginning of the data segment,
1037 * which is page-aligned.
1042 .globl empty_zero_page
1046 EXPORT_SYMBOL(empty_zero_page)
1048 .globl swapper_pg_dir
1050 .space PGD_TABLE_SIZE
1052 /* Room for two PTE table poiners, usually the kernel and current user
1053 * pointer to their respective root page table (pgdir).
1058 #ifdef CONFIG_PERF_EVENTS
1059 .globl itlb_miss_counter
1063 .globl dtlb_miss_counter
1067 .globl instruction_counter
1068 instruction_counter: