arch/powerpc/lib/sstep.c

   1 /*
   2  * Single-step support.
   3  *
   4  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/kprobes.h>
  13 #include <linux/ptrace.h>
  14 #include <linux/prefetch.h>
  15 #include <asm/sstep.h>
  16 #include <asm/processor.h>
  17 #include <linux/uaccess.h>
  18 #include <asm/cpu_has_feature.h>
  19 #include <asm/cputable.h>
  20
  21 extern char system_call_common[];
  22
  23 #ifdef CONFIG_PPC64
  24 /* Bits in SRR1 that are copied from MSR */
  25 #define MSR_MASK        0xffffffff87c0ffffUL
  26 #else
  27 #define MSR_MASK        0x87c0ffff
  28 #endif
  29
  30 /* Bits in XER */
  31 #define XER_SO          0x80000000U
  32 #define XER_OV          0x40000000U
  33 #define XER_CA          0x20000000U
  34 #define XER_OV32        0x00080000U
  35 #define XER_CA32        0x00040000U
  36
  37 #ifdef CONFIG_PPC_FPU
  38 /*
  39  * Functions in ldstfp.S
  40  */
  41 extern void get_fpr(int rn, double *p);
  42 extern void put_fpr(int rn, const double *p);
  43 extern void get_vr(int rn, __vector128 *p);
  44 extern void put_vr(int rn, __vector128 *p);
  45 extern void load_vsrn(int vsr, const void *p);
  46 extern void store_vsrn(int vsr, void *p);
  47 extern void conv_sp_to_dp(const float *sp, double *dp);
  48 extern void conv_dp_to_sp(const double *dp, float *sp);
  49 #endif
  50
  51 #ifdef __powerpc64__
  52 /*
  53  * Functions in quad.S
  54  */
  55 extern int do_lq(unsigned long ea, unsigned long *regs);
  56 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  57 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  58 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  59                     unsigned int *crp);
  60 #endif
  61
  62 #ifdef __LITTLE_ENDIAN__
  63 #define IS_LE   1
  64 #define IS_BE   0
  65 #else
  66 #define IS_LE   0
  67 #define IS_BE   1
  68 #endif
  69
  70 /*
  71  * Emulate the truncation of 64 bit values in 32-bit mode.
  72  */
  73 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  74                                                         unsigned long val)
  75 {
  76 #ifdef __powerpc64__
  77         if ((msr & MSR_64BIT) == 0)
  78                 val &= 0xffffffffUL;
  79 #endif
  80         return val;
  81 }
  82
  83 /*
  84  * Determine whether a conditional branch instruction would branch.
  85  */
  86 static nokprobe_inline int branch_taken(unsigned int instr,
  87                                         const struct pt_regs *regs,
  88                                         struct instruction_op *op)
  89 {
  90         unsigned int bo = (instr >> 21) & 0x1f;
  91         unsigned int bi;
  92
  93         if ((bo & 4) == 0) {
  94                 /* decrement counter */
  95                 op->type |= DECCTR;
  96                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  97                         return 0;
  98         }
  99         if ((bo & 0x10) == 0) {
 100                 /* check bit from CR */
 101                 bi = (instr >> 16) & 0x1f;
 102                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 103                         return 0;
 104         }
 105         return 1;
 106 }
 107
 108 static nokprobe_inline long address_ok(struct pt_regs *regs,
 109                                        unsigned long ea, int nb)
 110 {
 111         if (!user_mode(regs))
 112                 return 1;
 113         if (__access_ok(ea, nb, USER_DS))
 114                 return 1;
 115         if (__access_ok(ea, 1, USER_DS))
 116                 /* Access overlaps the end of the user region */
 117                 regs->dar = USER_DS.seg;
 118         else
 119                 regs->dar = ea;
 120         return 0;
 121 }
 122
 123 /*
 124  * Calculate effective address for a D-form instruction
 125  */
 126 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 127                                               const struct pt_regs *regs)
 128 {
 129         int ra;
 130         unsigned long ea;
 131
 132         ra = (instr >> 16) & 0x1f;
 133         ea = (signed short) instr;              /* sign-extend */
 134         if (ra)
 135                 ea += regs->gpr[ra];
 136
 137         return ea;
 138 }
 139
 140 #ifdef __powerpc64__
 141 /*
 142  * Calculate effective address for a DS-form instruction
 143  */
 144 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 145                                                const struct pt_regs *regs)
 146 {
 147         int ra;
 148         unsigned long ea;
 149
 150         ra = (instr >> 16) & 0x1f;
 151         ea = (signed short) (instr & ~3);       /* sign-extend */
 152         if (ra)
 153                 ea += regs->gpr[ra];
 154
 155         return ea;
 156 }
 157
 158 /*
 159  * Calculate effective address for a DQ-form instruction
 160  */
 161 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 162                                                const struct pt_regs *regs)
 163 {
 164         int ra;
 165         unsigned long ea;
 166
 167         ra = (instr >> 16) & 0x1f;
 168         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 169         if (ra)
 170                 ea += regs->gpr[ra];
 171
 172         return ea;
 173 }
 174 #endif /* __powerpc64 */
 175
 176 /*
 177  * Calculate effective address for an X-form instruction
 178  */
 179 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 180                                               const struct pt_regs *regs)
 181 {
 182         int ra, rb;
 183         unsigned long ea;
 184
 185         ra = (instr >> 16) & 0x1f;
 186         rb = (instr >> 11) & 0x1f;
 187         ea = regs->gpr[rb];
 188         if (ra)
 189                 ea += regs->gpr[ra];
 190
 191         return ea;
 192 }
 193
 194 /*
 195  * Return the largest power of 2, not greater than sizeof(unsigned long),
 196  * such that x is a multiple of it.
 197  */
 198 static nokprobe_inline unsigned long max_align(unsigned long x)
 199 {
 200         x |= sizeof(unsigned long);
 201         return x & -x;          /* isolates rightmost bit */
 202 }
 203
 204 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 205 {
 206         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 207 }
 208
 209 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 210 {
 211         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 212                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 213 }
 214
 215 #ifdef __powerpc64__
 216 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 217 {
 218         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 219 }
 220 #endif
 221
 222 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 223 {
 224         switch (nb) {
 225         case 2:
 226                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 227                 break;
 228         case 4:
 229                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 230                 break;
 231 #ifdef __powerpc64__
 232         case 8:
 233                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 234                 break;
 235         case 16: {
 236                 unsigned long *up = (unsigned long *)ptr;
 237                 unsigned long tmp;
 238                 tmp = byterev_8(up[0]);
 239                 up[0] = byterev_8(up[1]);
 240                 up[1] = tmp;
 241                 break;
 242         }
 243 #endif
 244         default:
 245                 WARN_ON_ONCE(1);
 246         }
 247 }
 248
 249 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 250                                             unsigned long ea, int nb,
 251                                             struct pt_regs *regs)
 252 {
 253         int err = 0;
 254         unsigned long x = 0;
 255
 256         switch (nb) {
 257         case 1:
 258                 err = __get_user(x, (unsigned char __user *) ea);
 259                 break;
 260         case 2:
 261                 err = __get_user(x, (unsigned short __user *) ea);
 262                 break;
 263         case 4:
 264                 err = __get_user(x, (unsigned int __user *) ea);
 265                 break;
 266 #ifdef __powerpc64__
 267         case 8:
 268                 err = __get_user(x, (unsigned long __user *) ea);
 269                 break;
 270 #endif
 271         }
 272         if (!err)
 273                 *dest = x;
 274         else
 275                 regs->dar = ea;
 276         return err;
 277 }
 278
 279 /*
 280  * Copy from userspace to a buffer, using the largest possible
 281  * aligned accesses, up to sizeof(long).
 282  */
 283 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
 284                                        struct pt_regs *regs)
 285 {
 286         int err = 0;
 287         int c;
 288
 289         for (; nb > 0; nb -= c) {
 290                 c = max_align(ea);
 291                 if (c > nb)
 292                         c = max_align(nb);
 293                 switch (c) {
 294                 case 1:
 295                         err = __get_user(*dest, (unsigned char __user *) ea);
 296                         break;
 297                 case 2:
 298                         err = __get_user(*(u16 *)dest,
 299                                          (unsigned short __user *) ea);
 300                         break;
 301                 case 4:
 302                         err = __get_user(*(u32 *)dest,
 303                                          (unsigned int __user *) ea);
 304                         break;
 305 #ifdef __powerpc64__
 306                 case 8:
 307                         err = __get_user(*(unsigned long *)dest,
 308                                          (unsigned long __user *) ea);
 309                         break;
 310 #endif
 311                 }
 312                 if (err) {
 313                         regs->dar = ea;
 314                         return err;
 315                 }
 316                 dest += c;
 317                 ea += c;
 318         }
 319         return 0;
 320 }
 321
 322 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 323                                               unsigned long ea, int nb,
 324                                               struct pt_regs *regs)
 325 {
 326         union {
 327                 unsigned long ul;
 328                 u8 b[sizeof(unsigned long)];
 329         } u;
 330         int i;
 331         int err;
 332
 333         u.ul = 0;
 334         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 335         err = copy_mem_in(&u.b[i], ea, nb, regs);
 336         if (!err)
 337                 *dest = u.ul;
 338         return err;
 339 }
 340
 341 /*
 342  * Read memory at address ea for nb bytes, return 0 for success
 343  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 344  * If nb < sizeof(long), the result is right-justified on BE systems.
 345  */
 346 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 347                               struct pt_regs *regs)
 348 {
 349         if (!address_ok(regs, ea, nb))
 350                 return -EFAULT;
 351         if ((ea & (nb - 1)) == 0)
 352                 return read_mem_aligned(dest, ea, nb, regs);
 353         return read_mem_unaligned(dest, ea, nb, regs);
 354 }
 355 NOKPROBE_SYMBOL(read_mem);
 356
 357 static nokprobe_inline int write_mem_aligned(unsigned long val,
 358                                              unsigned long ea, int nb,
 359                                              struct pt_regs *regs)
 360 {
 361         int err = 0;
 362
 363         switch (nb) {
 364         case 1:
 365                 err = __put_user(val, (unsigned char __user *) ea);
 366                 break;
 367         case 2:
 368                 err = __put_user(val, (unsigned short __user *) ea);
 369                 break;
 370         case 4:
 371                 err = __put_user(val, (unsigned int __user *) ea);
 372                 break;
 373 #ifdef __powerpc64__
 374         case 8:
 375                 err = __put_user(val, (unsigned long __user *) ea);
 376                 break;
 377 #endif
 378         }
 379         if (err)
 380                 regs->dar = ea;
 381         return err;
 382 }
 383
 384 /*
 385  * Copy from a buffer to userspace, using the largest possible
 386  * aligned accesses, up to sizeof(long).
 387  */
 388 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
 389                                         struct pt_regs *regs)
 390 {
 391         int err = 0;
 392         int c;
 393
 394         for (; nb > 0; nb -= c) {
 395                 c = max_align(ea);
 396                 if (c > nb)
 397                         c = max_align(nb);
 398                 switch (c) {
 399                 case 1:
 400                         err = __put_user(*dest, (unsigned char __user *) ea);
 401                         break;
 402                 case 2:
 403                         err = __put_user(*(u16 *)dest,
 404                                          (unsigned short __user *) ea);
 405                         break;
 406                 case 4:
 407                         err = __put_user(*(u32 *)dest,
 408                                          (unsigned int __user *) ea);
 409                         break;
 410 #ifdef __powerpc64__
 411                 case 8:
 412                         err = __put_user(*(unsigned long *)dest,
 413                                          (unsigned long __user *) ea);
 414                         break;
 415 #endif
 416                 }
 417                 if (err) {
 418                         regs->dar = ea;
 419                         return err;
 420                 }
 421                 dest += c;
 422                 ea += c;
 423         }
 424         return 0;
 425 }
 426
 427 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 428                                                unsigned long ea, int nb,
 429                                                struct pt_regs *regs)
 430 {
 431         union {
 432                 unsigned long ul;
 433                 u8 b[sizeof(unsigned long)];
 434         } u;
 435         int i;
 436
 437         u.ul = val;
 438         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 439         return copy_mem_out(&u.b[i], ea, nb, regs);
 440 }
 441
 442 /*
 443  * Write memory at address ea for nb bytes, return 0 for success
 444  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 445  */
 446 static int write_mem(unsigned long val, unsigned long ea, int nb,
 447                                struct pt_regs *regs)
 448 {
 449         if (!address_ok(regs, ea, nb))
 450                 return -EFAULT;
 451         if ((ea & (nb - 1)) == 0)
 452                 return write_mem_aligned(val, ea, nb, regs);
 453         return write_mem_unaligned(val, ea, nb, regs);
 454 }
 455 NOKPROBE_SYMBOL(write_mem);
 456
 457 #ifdef CONFIG_PPC_FPU
 458 /*
 459  * These access either the real FP register or the image in the
 460  * thread_struct, depending on regs->msr & MSR_FP.
 461  */
 462 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 463                       struct pt_regs *regs, bool cross_endian)
 464 {
 465         int err, rn, nb;
 466         union {
 467                 int i;
 468                 unsigned int u;
 469                 float f;
 470                 double d[2];
 471                 unsigned long l[2];
 472                 u8 b[2 * sizeof(double)];
 473         } u;
 474
 475         nb = GETSIZE(op->type);
 476         if (!address_ok(regs, ea, nb))
 477                 return -EFAULT;
 478         rn = op->reg;
 479         err = copy_mem_in(u.b, ea, nb, regs);
 480         if (err)
 481                 return err;
 482         if (unlikely(cross_endian)) {
 483                 do_byte_reverse(u.b, min(nb, 8));
 484                 if (nb == 16)
 485                         do_byte_reverse(&u.b[8], 8);
 486         }
 487         preempt_disable();
 488         if (nb == 4) {
 489                 if (op->type & FPCONV)
 490                         conv_sp_to_dp(&u.f, &u.d[0]);
 491                 else if (op->type & SIGNEXT)
 492                         u.l[0] = u.i;
 493                 else
 494                         u.l[0] = u.u;
 495         }
 496         if (regs->msr & MSR_FP)
 497                 put_fpr(rn, &u.d[0]);
 498         else
 499                 current->thread.TS_FPR(rn) = u.l[0];
 500         if (nb == 16) {
 501                 /* lfdp */
 502                 rn |= 1;
 503                 if (regs->msr & MSR_FP)
 504                         put_fpr(rn, &u.d[1]);
 505                 else
 506                         current->thread.TS_FPR(rn) = u.l[1];
 507         }
 508         preempt_enable();
 509         return 0;
 510 }
 511 NOKPROBE_SYMBOL(do_fp_load);
 512
 513 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 514                        struct pt_regs *regs, bool cross_endian)
 515 {
 516         int rn, nb;
 517         union {
 518                 unsigned int u;
 519                 float f;
 520                 double d[2];
 521                 unsigned long l[2];
 522                 u8 b[2 * sizeof(double)];
 523         } u;
 524
 525         nb = GETSIZE(op->type);
 526         if (!address_ok(regs, ea, nb))
 527                 return -EFAULT;
 528         rn = op->reg;
 529         preempt_disable();
 530         if (regs->msr & MSR_FP)
 531                 get_fpr(rn, &u.d[0]);
 532         else
 533                 u.l[0] = current->thread.TS_FPR(rn);
 534         if (nb == 4) {
 535                 if (op->type & FPCONV)
 536                         conv_dp_to_sp(&u.d[0], &u.f);
 537                 else
 538                         u.u = u.l[0];
 539         }
 540         if (nb == 16) {
 541                 rn |= 1;
 542                 if (regs->msr & MSR_FP)
 543                         get_fpr(rn, &u.d[1]);
 544                 else
 545                         u.l[1] = current->thread.TS_FPR(rn);
 546         }
 547         preempt_enable();
 548         if (unlikely(cross_endian)) {
 549                 do_byte_reverse(u.b, min(nb, 8));
 550                 if (nb == 16)
 551                         do_byte_reverse(&u.b[8], 8);
 552         }
 553         return copy_mem_out(u.b, ea, nb, regs);
 554 }
 555 NOKPROBE_SYMBOL(do_fp_store);
 556 #endif
 557
 558 #ifdef CONFIG_ALTIVEC
 559 /* For Altivec/VMX, no need to worry about alignment */
 560 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 561                                        int size, struct pt_regs *regs,
 562                                        bool cross_endian)
 563 {
 564         int err;
 565         union {
 566                 __vector128 v;
 567                 u8 b[sizeof(__vector128)];
 568         } u = {};
 569
 570         if (!address_ok(regs, ea & ~0xfUL, 16))
 571                 return -EFAULT;
 572         /* align to multiple of size */
 573         ea &= ~(size - 1);
 574         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 575         if (err)
 576                 return err;
 577         if (unlikely(cross_endian))
 578                 do_byte_reverse(&u.b[ea & 0xf], size);
 579         preempt_disable();
 580         if (regs->msr & MSR_VEC)
 581                 put_vr(rn, &u.v);
 582         else
 583                 current->thread.vr_state.vr[rn] = u.v;
 584         preempt_enable();
 585         return 0;
 586 }
 587
 588 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 589                                         int size, struct pt_regs *regs,
 590                                         bool cross_endian)
 591 {
 592         union {
 593                 __vector128 v;
 594                 u8 b[sizeof(__vector128)];
 595         } u;
 596
 597         if (!address_ok(regs, ea & ~0xfUL, 16))
 598                 return -EFAULT;
 599         /* align to multiple of size */
 600         ea &= ~(size - 1);
 601
 602         preempt_disable();
 603         if (regs->msr & MSR_VEC)
 604                 get_vr(rn, &u.v);
 605         else
 606                 u.v = current->thread.vr_state.vr[rn];
 607         preempt_enable();
 608         if (unlikely(cross_endian))
 609                 do_byte_reverse(&u.b[ea & 0xf], size);
 610         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 611 }
 612 #endif /* CONFIG_ALTIVEC */
 613
 614 #ifdef __powerpc64__
 615 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 616                                       int reg, bool cross_endian)
 617 {
 618         int err;
 619
 620         if (!address_ok(regs, ea, 16))
 621                 return -EFAULT;
 622         /* if aligned, should be atomic */
 623         if ((ea & 0xf) == 0) {
 624                 err = do_lq(ea, &regs->gpr[reg]);
 625         } else {
 626                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 627                 if (!err)
 628                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 629         }
 630         if (!err && unlikely(cross_endian))
 631                 do_byte_reverse(&regs->gpr[reg], 16);
 632         return err;
 633 }
 634
 635 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 636                                        int reg, bool cross_endian)
 637 {
 638         int err;
 639         unsigned long vals[2];
 640
 641         if (!address_ok(regs, ea, 16))
 642                 return -EFAULT;
 643         vals[0] = regs->gpr[reg];
 644         vals[1] = regs->gpr[reg + 1];
 645         if (unlikely(cross_endian))
 646                 do_byte_reverse(vals, 16);
 647
 648         /* if aligned, should be atomic */
 649         if ((ea & 0xf) == 0)
 650                 return do_stq(ea, vals[0], vals[1]);
 651
 652         err = write_mem(vals[IS_LE], ea, 8, regs);
 653         if (!err)
 654                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 655         return err;
 656 }
 657 #endif /* __powerpc64 */
 658
 659 #ifdef CONFIG_VSX
 660 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 661                       const void *mem, bool rev)
 662 {
 663         int size, read_size;
 664         int i, j;
 665         const unsigned int *wp;
 666         const unsigned short *hp;
 667         const unsigned char *bp;
 668
 669         size = GETSIZE(op->type);
 670         reg->d[0] = reg->d[1] = 0;
 671
 672         switch (op->element_size) {
 673         case 16:
 674                 /* whole vector; lxv[x] or lxvl[l] */
 675                 if (size == 0)
 676                         break;
 677                 memcpy(reg, mem, size);
 678                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 679                         rev = !rev;
 680                 if (rev)
 681                         do_byte_reverse(reg, 16);
 682                 break;
 683         case 8:
 684                 /* scalar loads, lxvd2x, lxvdsx */
 685                 read_size = (size >= 8) ? 8 : size;
 686                 i = IS_LE ? 8 : 8 - read_size;
 687                 memcpy(&reg->b[i], mem, read_size);
 688                 if (rev)
 689                         do_byte_reverse(&reg->b[i], 8);
 690                 if (size < 8) {
 691                         if (op->type & SIGNEXT) {
 692                                 /* size == 4 is the only case here */
 693                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 694                         } else if (op->vsx_flags & VSX_FPCONV) {
 695                                 preempt_disable();
 696                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 697                                               &reg->dp[IS_LE]);
 698                                 preempt_enable();
 699                         }
 700                 } else {
 701                         if (size == 16) {
 702                                 unsigned long v = *(unsigned long *)(mem + 8);
 703                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 704                         } else if (op->vsx_flags & VSX_SPLAT)
 705                                 reg->d[IS_BE] = reg->d[IS_LE];
 706                 }
 707                 break;
 708         case 4:
 709                 /* lxvw4x, lxvwsx */
 710                 wp = mem;
 711                 for (j = 0; j < size / 4; ++j) {
 712                         i = IS_LE ? 3 - j : j;
 713                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 714                 }
 715                 if (op->vsx_flags & VSX_SPLAT) {
 716                         u32 val = reg->w[IS_LE ? 3 : 0];
 717                         for (; j < 4; ++j) {
 718                                 i = IS_LE ? 3 - j : j;
 719                                 reg->w[i] = val;
 720                         }
 721                 }
 722                 break;
 723         case 2:
 724                 /* lxvh8x */
 725                 hp = mem;
 726                 for (j = 0; j < size / 2; ++j) {
 727                         i = IS_LE ? 7 - j : j;
 728                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 729                 }
 730                 break;
 731         case 1:
 732                 /* lxvb16x */
 733                 bp = mem;
 734                 for (j = 0; j < size; ++j) {
 735                         i = IS_LE ? 15 - j : j;
 736                         reg->b[i] = *bp++;
 737                 }
 738                 break;
 739         }
 740 }
 741 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 742 NOKPROBE_SYMBOL(emulate_vsx_load);
 743
 744 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 745                        void *mem, bool rev)
 746 {
 747         int size, write_size;
 748         int i, j;
 749         union vsx_reg buf;
 750         unsigned int *wp;
 751         unsigned short *hp;
 752         unsigned char *bp;
 753
 754         size = GETSIZE(op->type);
 755
 756         switch (op->element_size) {
 757         case 16:
 758                 /* stxv, stxvx, stxvl, stxvll */
 759                 if (size == 0)
 760                         break;
 761                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 762                         rev = !rev;
 763                 if (rev) {
 764                         /* reverse 16 bytes */
 765                         buf.d[0] = byterev_8(reg->d[1]);
 766                         buf.d[1] = byterev_8(reg->d[0]);
 767                         reg = &buf;
 768                 }
 769                 memcpy(mem, reg, size);
 770                 break;
 771         case 8:
 772                 /* scalar stores, stxvd2x */
 773                 write_size = (size >= 8) ? 8 : size;
 774                 i = IS_LE ? 8 : 8 - write_size;
 775                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 776                         buf.d[0] = buf.d[1] = 0;
 777                         preempt_disable();
 778                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 779                         preempt_enable();
 780                         reg = &buf;
 781                 }
 782                 memcpy(mem, &reg->b[i], write_size);
 783                 if (size == 16)
 784                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 785                 if (unlikely(rev)) {
 786                         do_byte_reverse(mem, write_size);
 787                         if (size == 16)
 788                                 do_byte_reverse(mem + 8, 8);
 789                 }
 790                 break;
 791         case 4:
 792                 /* stxvw4x */
 793                 wp = mem;
 794                 for (j = 0; j < size / 4; ++j) {
 795                         i = IS_LE ? 3 - j : j;
 796                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 797                 }
 798                 break;
 799         case 2:
 800                 /* stxvh8x */
 801                 hp = mem;
 802                 for (j = 0; j < size / 2; ++j) {
 803                         i = IS_LE ? 7 - j : j;
 804                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 805                 }
 806                 break;
 807         case 1:
 808                 /* stvxb16x */
 809                 bp = mem;
 810                 for (j = 0; j < size; ++j) {
 811                         i = IS_LE ? 15 - j : j;
 812                         *bp++ = reg->b[i];
 813                 }
 814                 break;
 815         }
 816 }
 817 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 818 NOKPROBE_SYMBOL(emulate_vsx_store);
 819
 820 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 821                                        unsigned long ea, struct pt_regs *regs,
 822                                        bool cross_endian)
 823 {
 824         int reg = op->reg;
 825         u8 mem[16];
 826         union vsx_reg buf;
 827         int size = GETSIZE(op->type);
 828
 829         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 830                 return -EFAULT;
 831
 832         emulate_vsx_load(op, &buf, mem, cross_endian);
 833         preempt_disable();
 834         if (reg < 32) {
 835                 /* FP regs + extensions */
 836                 if (regs->msr & MSR_FP) {
 837                         load_vsrn(reg, &buf);
 838                 } else {
 839                         current->thread.fp_state.fpr[reg][0] = buf.d[0];
 840                         current->thread.fp_state.fpr[reg][1] = buf.d[1];
 841                 }
 842         } else {
 843                 if (regs->msr & MSR_VEC)
 844                         load_vsrn(reg, &buf);
 845                 else
 846                         current->thread.vr_state.vr[reg - 32] = buf.v;
 847         }
 848         preempt_enable();
 849         return 0;
 850 }
 851
 852 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 853                                         unsigned long ea, struct pt_regs *regs,
 854                                         bool cross_endian)
 855 {
 856         int reg = op->reg;
 857         u8 mem[16];
 858         union vsx_reg buf;
 859         int size = GETSIZE(op->type);
 860
 861         if (!address_ok(regs, ea, size))
 862                 return -EFAULT;
 863
 864         preempt_disable();
 865         if (reg < 32) {
 866                 /* FP regs + extensions */
 867                 if (regs->msr & MSR_FP) {
 868                         store_vsrn(reg, &buf);
 869                 } else {
 870                         buf.d[0] = current->thread.fp_state.fpr[reg][0];
 871                         buf.d[1] = current->thread.fp_state.fpr[reg][1];
 872                 }
 873         } else {
 874                 if (regs->msr & MSR_VEC)
 875                         store_vsrn(reg, &buf);
 876                 else
 877                         buf.v = current->thread.vr_state.vr[reg - 32];
 878         }
 879         preempt_enable();
 880         emulate_vsx_store(op, &buf, mem, cross_endian);
 881         return  copy_mem_out(mem, ea, size, regs);
 882 }
 883 #endif /* CONFIG_VSX */
 884
 885 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 886 {
 887         int err;
 888         unsigned long i, size;
 889
 890 #ifdef __powerpc64__
 891         size = ppc64_caches.l1d.block_size;
 892         if (!(regs->msr & MSR_64BIT))
 893                 ea &= 0xffffffffUL;
 894 #else
 895         size = L1_CACHE_BYTES;
 896 #endif
 897         ea &= ~(size - 1);
 898         if (!address_ok(regs, ea, size))
 899                 return -EFAULT;
 900         for (i = 0; i < size; i += sizeof(long)) {
 901                 err = __put_user(0, (unsigned long __user *) (ea + i));
 902                 if (err) {
 903                         regs->dar = ea;
 904                         return err;
 905                 }
 906         }
 907         return 0;
 908 }
 909 NOKPROBE_SYMBOL(emulate_dcbz);
 910
 911 #define __put_user_asmx(x, addr, err, op, cr)           \
 912         __asm__ __volatile__(                           \
 913                 ".machine push\n"                       \
 914                 ".machine power8\n"                     \
 915                 "1:     " op " %2,0,%3\n"               \
 916                 ".machine pop\n"                        \
 917                 "       mfcr    %1\n"                   \
 918                 "2:\n"                                  \
 919                 ".section .fixup,\"ax\"\n"              \
 920                 "3:     li      %0,%4\n"                \
 921                 "       b       2b\n"                   \
 922                 ".previous\n"                           \
 923                 EX_TABLE(1b, 3b)                        \
 924                 : "=r" (err), "=r" (cr)                 \
 925                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
 926
 927 #define __get_user_asmx(x, addr, err, op)               \
 928         __asm__ __volatile__(                           \
 929                 ".machine push\n"                       \
 930                 ".machine power8\n"                     \
 931                 "1:     "op" %1,0,%2\n"                 \
 932                 ".machine pop\n"                        \
 933                 "2:\n"                                  \
 934                 ".section .fixup,\"ax\"\n"              \
 935                 "3:     li      %0,%3\n"                \
 936                 "       b       2b\n"                   \
 937                 ".previous\n"                           \
 938                 EX_TABLE(1b, 3b)                        \
 939                 : "=r" (err), "=r" (x)                  \
 940                 : "r" (addr), "i" (-EFAULT), "0" (err))
 941
 942 #define __cacheop_user_asmx(addr, err, op)              \
 943         __asm__ __volatile__(                           \
 944                 "1:     "op" 0,%1\n"                    \
 945                 "2:\n"                                  \
 946                 ".section .fixup,\"ax\"\n"              \
 947                 "3:     li      %0,%3\n"                \
 948                 "       b       2b\n"                   \
 949                 ".previous\n"                           \
 950                 EX_TABLE(1b, 3b)                        \
 951                 : "=r" (err)                            \
 952                 : "r" (addr), "i" (-EFAULT), "0" (err))
 953
 954 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
 955                                     struct instruction_op *op)
 956 {
 957         long val = op->val;
 958
 959         op->type |= SETCC;
 960         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
 961 #ifdef __powerpc64__
 962         if (!(regs->msr & MSR_64BIT))
 963                 val = (int) val;
 964 #endif
 965         if (val < 0)
 966                 op->ccval |= 0x80000000;
 967         else if (val > 0)
 968                 op->ccval |= 0x40000000;
 969         else
 970                 op->ccval |= 0x20000000;
 971 }
 972
 973 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
 974 {
 975         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
 976                 if (val)
 977                         op->xerval |= XER_CA32;
 978                 else
 979                         op->xerval &= ~XER_CA32;
 980         }
 981 }
 982
 983 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
 984                                      struct instruction_op *op, int rd,
 985                                      unsigned long val1, unsigned long val2,
 986                                      unsigned long carry_in)
 987 {
 988         unsigned long val = val1 + val2;
 989
 990         if (carry_in)
 991                 ++val;
 992         op->type = COMPUTE + SETREG + SETXER;
 993         op->reg = rd;
 994         op->val = val;
 995 #ifdef __powerpc64__
 996         if (!(regs->msr & MSR_64BIT)) {
 997                 val = (unsigned int) val;
 998                 val1 = (unsigned int) val1;
 999         }
1000 #endif
1001         op->xerval = regs->xer;
1002         if (val < val1 || (carry_in && val == val1))
1003                 op->xerval |= XER_CA;
1004         else
1005                 op->xerval &= ~XER_CA;
1006
1007         set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1008                         (carry_in && (unsigned int)val == (unsigned int)val1));
1009 }
1010
1011 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1012                                           struct instruction_op *op,
1013                                           long v1, long v2, int crfld)
1014 {
1015         unsigned int crval, shift;
1016
1017         op->type = COMPUTE + SETCC;
1018         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1019         if (v1 < v2)
1020                 crval |= 8;
1021         else if (v1 > v2)
1022                 crval |= 4;
1023         else
1024                 crval |= 2;
1025         shift = (7 - crfld) * 4;
1026         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1027 }
1028
1029 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1030                                             struct instruction_op *op,
1031                                             unsigned long v1,
1032                                             unsigned long v2, int crfld)
1033 {
1034         unsigned int crval, shift;
1035
1036         op->type = COMPUTE + SETCC;
1037         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1038         if (v1 < v2)
1039                 crval |= 8;
1040         else if (v1 > v2)
1041                 crval |= 4;
1042         else
1043                 crval |= 2;
1044         shift = (7 - crfld) * 4;
1045         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1046 }
1047
1048 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1049                                     struct instruction_op *op,
1050                                     unsigned long v1, unsigned long v2)
1051 {
1052         unsigned long long out_val, mask;
1053         int i;
1054
1055         out_val = 0;
1056         for (i = 0; i < 8; i++) {
1057                 mask = 0xffUL << (i * 8);
1058                 if ((v1 & mask) == (v2 & mask))
1059                         out_val |= mask;
1060         }
1061         op->val = out_val;
1062 }
1063
1064 /*
1065  * The size parameter is used to adjust the equivalent popcnt instruction.
1066  * popcntb = 8, popcntw = 32, popcntd = 64
1067  */
1068 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1069                                       struct instruction_op *op,
1070                                       unsigned long v1, int size)
1071 {
1072         unsigned long long out = v1;
1073
1074         out -= (out >> 1) & 0x5555555555555555ULL;
1075         out = (0x3333333333333333ULL & out) +
1076               (0x3333333333333333ULL & (out >> 2));
1077         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1078
1079         if (size == 8) {        /* popcntb */
1080                 op->val = out;
1081                 return;
1082         }
1083         out += out >> 8;
1084         out += out >> 16;
1085         if (size == 32) {       /* popcntw */
1086                 op->val = out & 0x0000003f0000003fULL;
1087                 return;
1088         }
1089
1090         out = (out + (out >> 32)) & 0x7f;
1091         op->val = out;  /* popcntd */
1092 }
1093
1094 #ifdef CONFIG_PPC64
1095 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1096                                       struct instruction_op *op,
1097                                       unsigned long v1, unsigned long v2)
1098 {
1099         unsigned char perm, idx;
1100         unsigned int i;
1101
1102         perm = 0;
1103         for (i = 0; i < 8; i++) {
1104                 idx = (v1 >> (i * 8)) & 0xff;
1105                 if (idx < 64)
1106                         if (v2 & PPC_BIT(idx))
1107                                 perm |= 1 << i;
1108         }
1109         op->val = perm;
1110 }
1111 #endif /* CONFIG_PPC64 */
1112 /*
1113  * The size parameter adjusts the equivalent prty instruction.
1114  * prtyw = 32, prtyd = 64
1115  */
1116 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1117                                     struct instruction_op *op,
1118                                     unsigned long v, int size)
1119 {
1120         unsigned long long res = v ^ (v >> 8);
1121
1122         res ^= res >> 16;
1123         if (size == 32) {               /* prtyw */
1124                 op->val = res & 0x0000000100000001ULL;
1125                 return;
1126         }
1127
1128         res ^= res >> 32;
1129         op->val = res & 1;      /*prtyd */
1130 }
1131
1132 static nokprobe_inline int trap_compare(long v1, long v2)
1133 {
1134         int ret = 0;
1135
1136         if (v1 < v2)
1137                 ret |= 0x10;
1138         else if (v1 > v2)
1139                 ret |= 0x08;
1140         else
1141                 ret |= 0x04;
1142         if ((unsigned long)v1 < (unsigned long)v2)
1143                 ret |= 0x02;
1144         else if ((unsigned long)v1 > (unsigned long)v2)
1145                 ret |= 0x01;
1146         return ret;
1147 }
1148
1149 /*
1150  * Elements of 32-bit rotate and mask instructions.
1151  */
1152 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1153                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1154 #ifdef __powerpc64__
1155 #define MASK64_L(mb)    (~0UL >> (mb))
1156 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1157 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1158 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1159 #else
1160 #define DATA32(x)       (x)
1161 #endif
1162 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1163
1164 /*
1165  * Decode an instruction, and return information about it in *op
1166  * without changing *regs.
1167  * Integer arithmetic and logical instructions, branches, and barrier
1168  * instructions can be emulated just using the information in *op.
1169  *
1170  * Return value is 1 if the instruction can be emulated just by
1171  * updating *regs with the information in *op, -1 if we need the
1172  * GPRs but *regs doesn't contain the full register set, or 0
1173  * otherwise.
1174  */
1175 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1176                   unsigned int instr)
1177 {
1178         unsigned int opcode, ra, rb, rd, spr, u;
1179         unsigned long int imm;
1180         unsigned long int val, val2;
1181         unsigned int mb, me, sh;
1182         long ival;
1183
1184         op->type = COMPUTE;
1185
1186         opcode = instr >> 26;
1187         switch (opcode) {
1188         case 16:        /* bc */
1189                 op->type = BRANCH;
1190                 imm = (signed short)(instr & 0xfffc);
1191                 if ((instr & 2) == 0)
1192                         imm += regs->nip;
1193                 op->val = truncate_if_32bit(regs->msr, imm);
1194                 if (instr & 1)
1195                         op->type |= SETLK;
1196                 if (branch_taken(instr, regs, op))
1197                         op->type |= BRTAKEN;
1198                 return 1;
1199 #ifdef CONFIG_PPC64
1200         case 17:        /* sc */
1201                 if ((instr & 0xfe2) == 2)
1202                         op->type = SYSCALL;
1203                 else
1204                         op->type = UNKNOWN;
1205                 return 0;
1206 #endif
1207         case 18:        /* b */
1208                 op->type = BRANCH | BRTAKEN;
1209                 imm = instr & 0x03fffffc;
1210                 if (imm & 0x02000000)
1211                         imm -= 0x04000000;
1212                 if ((instr & 2) == 0)
1213                         imm += regs->nip;
1214                 op->val = truncate_if_32bit(regs->msr, imm);
1215                 if (instr & 1)
1216                         op->type |= SETLK;
1217                 return 1;
1218         case 19:
1219                 switch ((instr >> 1) & 0x3ff) {
1220                 case 0:         /* mcrf */
1221                         op->type = COMPUTE + SETCC;
1222                         rd = 7 - ((instr >> 23) & 0x7);
1223                         ra = 7 - ((instr >> 18) & 0x7);
1224                         rd *= 4;
1225                         ra *= 4;
1226                         val = (regs->ccr >> ra) & 0xf;
1227                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1228                         return 1;
1229
1230                 case 16:        /* bclr */
1231                 case 528:       /* bcctr */
1232                         op->type = BRANCH;
1233                         imm = (instr & 0x400)? regs->ctr: regs->link;
1234                         op->val = truncate_if_32bit(regs->msr, imm);
1235                         if (instr & 1)
1236                                 op->type |= SETLK;
1237                         if (branch_taken(instr, regs, op))
1238                                 op->type |= BRTAKEN;
1239                         return 1;
1240
1241                 case 18:        /* rfid, scary */
1242                         if (regs->msr & MSR_PR)
1243                                 goto priv;
1244                         op->type = RFI;
1245                         return 0;
1246
1247                 case 150:       /* isync */
1248                         op->type = BARRIER | BARRIER_ISYNC;
1249                         return 1;
1250
1251                 case 33:        /* crnor */
1252                 case 129:       /* crandc */
1253                 case 193:       /* crxor */
1254                 case 225:       /* crnand */
1255                 case 257:       /* crand */
1256                 case 289:       /* creqv */
1257                 case 417:       /* crorc */
1258                 case 449:       /* cror */
1259                         op->type = COMPUTE + SETCC;
1260                         ra = (instr >> 16) & 0x1f;
1261                         rb = (instr >> 11) & 0x1f;
1262                         rd = (instr >> 21) & 0x1f;
1263                         ra = (regs->ccr >> (31 - ra)) & 1;
1264                         rb = (regs->ccr >> (31 - rb)) & 1;
1265                         val = (instr >> (6 + ra * 2 + rb)) & 1;
1266                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1267                                 (val << (31 - rd));
1268                         return 1;
1269                 }
1270                 break;
1271         case 31:
1272                 switch ((instr >> 1) & 0x3ff) {
1273                 case 598:       /* sync */
1274                         op->type = BARRIER + BARRIER_SYNC;
1275 #ifdef __powerpc64__
1276                         switch ((instr >> 21) & 3) {
1277                         case 1:         /* lwsync */
1278                                 op->type = BARRIER + BARRIER_LWSYNC;
1279                                 break;
1280                         case 2:         /* ptesync */
1281                                 op->type = BARRIER + BARRIER_PTESYNC;
1282                                 break;
1283                         }
1284 #endif
1285                         return 1;
1286
1287                 case 854:       /* eieio */
1288                         op->type = BARRIER + BARRIER_EIEIO;
1289                         return 1;
1290                 }
1291                 break;
1292         }
1293
1294         /* Following cases refer to regs->gpr[], so we need all regs */
1295         if (!FULL_REGS(regs))
1296                 return -1;
1297
1298         rd = (instr >> 21) & 0x1f;
1299         ra = (instr >> 16) & 0x1f;
1300         rb = (instr >> 11) & 0x1f;
1301
1302         switch (opcode) {
1303 #ifdef __powerpc64__
1304         case 2:         /* tdi */
1305                 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1306                         goto trap;
1307                 return 1;
1308 #endif
1309         case 3:         /* twi */
1310                 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1311                         goto trap;
1312                 return 1;
1313
1314         case 7:         /* mulli */
1315                 op->val = regs->gpr[ra] * (short) instr;
1316                 goto compute_done;
1317
1318         case 8:         /* subfic */
1319                 imm = (short) instr;
1320                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1321                 return 1;
1322
1323         case 10:        /* cmpli */
1324                 imm = (unsigned short) instr;
1325                 val = regs->gpr[ra];
1326 #ifdef __powerpc64__
1327                 if ((rd & 1) == 0)
1328                         val = (unsigned int) val;
1329 #endif
1330                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1331                 return 1;
1332
1333         case 11:        /* cmpi */
1334                 imm = (short) instr;
1335                 val = regs->gpr[ra];
1336 #ifdef __powerpc64__
1337                 if ((rd & 1) == 0)
1338                         val = (int) val;
1339 #endif
1340                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1341                 return 1;
1342
1343         case 12:        /* addic */
1344                 imm = (short) instr;
1345                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1346                 return 1;
1347
1348         case 13:        /* addic. */
1349                 imm = (short) instr;
1350                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1351                 set_cr0(regs, op);
1352                 return 1;
1353
1354         case 14:        /* addi */
1355                 imm = (short) instr;
1356                 if (ra)
1357                         imm += regs->gpr[ra];
1358                 op->val = imm;
1359                 goto compute_done;
1360
1361         case 15:        /* addis */
1362                 imm = ((short) instr) << 16;
1363                 if (ra)
1364                         imm += regs->gpr[ra];
1365                 op->val = imm;
1366                 goto compute_done;
1367
1368         case 19:
1369                 if (((instr >> 1) & 0x1f) == 2) {
1370                         /* addpcis */
1371                         imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1372                         imm |= (instr >> 15) & 0x3e;    /* d1 field */
1373                         op->val = regs->nip + (imm << 16) + 4;
1374                         goto compute_done;
1375                 }
1376                 op->type = UNKNOWN;
1377                 return 0;
1378
1379         case 20:        /* rlwimi */
1380                 mb = (instr >> 6) & 0x1f;
1381                 me = (instr >> 1) & 0x1f;
1382                 val = DATA32(regs->gpr[rd]);
1383                 imm = MASK32(mb, me);
1384                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1385                 goto logical_done;
1386
1387         case 21:        /* rlwinm */
1388                 mb = (instr >> 6) & 0x1f;
1389                 me = (instr >> 1) & 0x1f;
1390                 val = DATA32(regs->gpr[rd]);
1391                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1392                 goto logical_done;
1393
1394         case 23:        /* rlwnm */
1395                 mb = (instr >> 6) & 0x1f;
1396                 me = (instr >> 1) & 0x1f;
1397                 rb = regs->gpr[rb] & 0x1f;
1398                 val = DATA32(regs->gpr[rd]);
1399                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1400                 goto logical_done;
1401
1402         case 24:        /* ori */
1403                 op->val = regs->gpr[rd] | (unsigned short) instr;
1404                 goto logical_done_nocc;
1405
1406         case 25:        /* oris */
1407                 imm = (unsigned short) instr;
1408                 op->val = regs->gpr[rd] | (imm << 16);
1409                 goto logical_done_nocc;
1410
1411         case 26:        /* xori */
1412                 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1413                 goto logical_done_nocc;
1414
1415         case 27:        /* xoris */
1416                 imm = (unsigned short) instr;
1417                 op->val = regs->gpr[rd] ^ (imm << 16);
1418                 goto logical_done_nocc;
1419
1420         case 28:        /* andi. */
1421                 op->val = regs->gpr[rd] & (unsigned short) instr;
1422                 set_cr0(regs, op);
1423                 goto logical_done_nocc;
1424
1425         case 29:        /* andis. */
1426                 imm = (unsigned short) instr;
1427                 op->val = regs->gpr[rd] & (imm << 16);
1428                 set_cr0(regs, op);
1429                 goto logical_done_nocc;
1430
1431 #ifdef __powerpc64__
1432         case 30:        /* rld* */
1433                 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1434                 val = regs->gpr[rd];
1435                 if ((instr & 0x10) == 0) {
1436                         sh = rb | ((instr & 2) << 4);
1437                         val = ROTATE(val, sh);
1438                         switch ((instr >> 2) & 3) {
1439                         case 0:         /* rldicl */
1440                                 val &= MASK64_L(mb);
1441                                 break;
1442                         case 1:         /* rldicr */
1443                                 val &= MASK64_R(mb);
1444                                 break;
1445                         case 2:         /* rldic */
1446                                 val &= MASK64(mb, 63 - sh);
1447                                 break;
1448                         case 3:         /* rldimi */
1449                                 imm = MASK64(mb, 63 - sh);
1450                                 val = (regs->gpr[ra] & ~imm) |
1451                                         (val & imm);
1452                         }
1453                         op->val = val;
1454                         goto logical_done;
1455                 } else {
1456                         sh = regs->gpr[rb] & 0x3f;
1457                         val = ROTATE(val, sh);
1458                         switch ((instr >> 1) & 7) {
1459                         case 0:         /* rldcl */
1460                                 op->val = val & MASK64_L(mb);
1461                                 goto logical_done;
1462                         case 1:         /* rldcr */
1463                                 op->val = val & MASK64_R(mb);
1464                                 goto logical_done;
1465                         }
1466                 }
1467 #endif
1468                 op->type = UNKNOWN;     /* illegal instruction */
1469                 return 0;
1470
1471         case 31:
1472                 /* isel occupies 32 minor opcodes */
1473                 if (((instr >> 1) & 0x1f) == 15) {
1474                         mb = (instr >> 6) & 0x1f; /* bc field */
1475                         val = (regs->ccr >> (31 - mb)) & 1;
1476                         val2 = (ra) ? regs->gpr[ra] : 0;
1477
1478                         op->val = (val) ? val2 : regs->gpr[rb];
1479                         goto compute_done;
1480                 }
1481
1482                 switch ((instr >> 1) & 0x3ff) {
1483                 case 4:         /* tw */
1484                         if (rd == 0x1f ||
1485                             (rd & trap_compare((int)regs->gpr[ra],
1486                                                (int)regs->gpr[rb])))
1487                                 goto trap;
1488                         return 1;
1489 #ifdef __powerpc64__
1490                 case 68:        /* td */
1491                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1492                                 goto trap;
1493                         return 1;
1494 #endif
1495                 case 83:        /* mfmsr */
1496                         if (regs->msr & MSR_PR)
1497                                 goto priv;
1498                         op->type = MFMSR;
1499                         op->reg = rd;
1500                         return 0;
1501                 case 146:       /* mtmsr */
1502                         if (regs->msr & MSR_PR)
1503                                 goto priv;
1504                         op->type = MTMSR;
1505                         op->reg = rd;
1506                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1507                         return 0;
1508 #ifdef CONFIG_PPC64
1509                 case 178:       /* mtmsrd */
1510                         if (regs->msr & MSR_PR)
1511                                 goto priv;
1512                         op->type = MTMSR;
1513                         op->reg = rd;
1514                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1515                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1516                         imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1517                         op->val = imm;
1518                         return 0;
1519 #endif
1520
1521                 case 19:        /* mfcr */
1522                         imm = 0xffffffffUL;
1523                         if ((instr >> 20) & 1) {
1524                                 imm = 0xf0000000UL;
1525                                 for (sh = 0; sh < 8; ++sh) {
1526                                         if (instr & (0x80000 >> sh))
1527                                                 break;
1528                                         imm >>= 4;
1529                                 }
1530                         }
1531                         op->val = regs->ccr & imm;
1532                         goto compute_done;
1533
1534                 case 144:       /* mtcrf */
1535                         op->type = COMPUTE + SETCC;
1536                         imm = 0xf0000000UL;
1537                         val = regs->gpr[rd];
1538                         op->ccval = regs->ccr;
1539                         for (sh = 0; sh < 8; ++sh) {
1540                                 if (instr & (0x80000 >> sh))
1541                                         op->ccval = (op->ccval & ~imm) |
1542                                                 (val & imm);
1543                                 imm >>= 4;
1544                         }
1545                         return 1;
1546
1547                 case 339:       /* mfspr */
1548                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1549                         op->type = MFSPR;
1550                         op->reg = rd;
1551                         op->spr = spr;
1552                         if (spr == SPRN_XER || spr == SPRN_LR ||
1553                             spr == SPRN_CTR)
1554                                 return 1;
1555                         return 0;
1556
1557                 case 467:       /* mtspr */
1558                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1559                         op->type = MTSPR;
1560                         op->val = regs->gpr[rd];
1561                         op->spr = spr;
1562                         if (spr == SPRN_XER || spr == SPRN_LR ||
1563                             spr == SPRN_CTR)
1564                                 return 1;
1565                         return 0;
1566
1567 /*
1568  * Compare instructions
1569  */
1570                 case 0: /* cmp */
1571                         val = regs->gpr[ra];
1572                         val2 = regs->gpr[rb];
1573 #ifdef __powerpc64__
1574                         if ((rd & 1) == 0) {
1575                                 /* word (32-bit) compare */
1576                                 val = (int) val;
1577                                 val2 = (int) val2;
1578                         }
1579 #endif
1580                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1581                         return 1;
1582
1583                 case 32:        /* cmpl */
1584                         val = regs->gpr[ra];
1585                         val2 = regs->gpr[rb];
1586 #ifdef __powerpc64__
1587                         if ((rd & 1) == 0) {
1588                                 /* word (32-bit) compare */
1589                                 val = (unsigned int) val;
1590                                 val2 = (unsigned int) val2;
1591                         }
1592 #endif
1593                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1594                         return 1;
1595
1596                 case 508: /* cmpb */
1597                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1598                         goto logical_done_nocc;
1599
1600 /*
1601  * Arithmetic instructions
1602  */
1603                 case 8: /* subfc */
1604                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1605                                        regs->gpr[rb], 1);
1606                         goto arith_done;
1607 #ifdef __powerpc64__
1608                 case 9: /* mulhdu */
1609                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1610                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1611                         goto arith_done;
1612 #endif
1613                 case 10:        /* addc */
1614                         add_with_carry(regs, op, rd, regs->gpr[ra],
1615                                        regs->gpr[rb], 0);
1616                         goto arith_done;
1617
1618                 case 11:        /* mulhwu */
1619                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1620                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1621                         goto arith_done;
1622
1623                 case 40:        /* subf */
1624                         op->val = regs->gpr[rb] - regs->gpr[ra];
1625                         goto arith_done;
1626 #ifdef __powerpc64__
1627                 case 73:        /* mulhd */
1628                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1629                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1630                         goto arith_done;
1631 #endif
1632                 case 75:        /* mulhw */
1633                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1634                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1635                         goto arith_done;
1636
1637                 case 104:       /* neg */
1638                         op->val = -regs->gpr[ra];
1639                         goto arith_done;
1640
1641                 case 136:       /* subfe */
1642                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1643                                        regs->gpr[rb], regs->xer & XER_CA);
1644                         goto arith_done;
1645
1646                 case 138:       /* adde */
1647                         add_with_carry(regs, op, rd, regs->gpr[ra],
1648                                        regs->gpr[rb], regs->xer & XER_CA);
1649                         goto arith_done;
1650
1651                 case 200:       /* subfze */
1652                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1653                                        regs->xer & XER_CA);
1654                         goto arith_done;
1655
1656                 case 202:       /* addze */
1657                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1658                                        regs->xer & XER_CA);
1659                         goto arith_done;
1660
1661                 case 232:       /* subfme */
1662                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1663                                        regs->xer & XER_CA);
1664                         goto arith_done;
1665 #ifdef __powerpc64__
1666                 case 233:       /* mulld */
1667                         op->val = regs->gpr[ra] * regs->gpr[rb];
1668                         goto arith_done;
1669 #endif
1670                 case 234:       /* addme */
1671                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1672                                        regs->xer & XER_CA);
1673                         goto arith_done;
1674
1675                 case 235:       /* mullw */
1676                         op->val = (long)(int) regs->gpr[ra] *
1677                                 (int) regs->gpr[rb];
1678
1679                         goto arith_done;
1680
1681                 case 266:       /* add */
1682                         op->val = regs->gpr[ra] + regs->gpr[rb];
1683                         goto arith_done;
1684 #ifdef __powerpc64__
1685                 case 457:       /* divdu */
1686                         op->val = regs->gpr[ra] / regs->gpr[rb];
1687                         goto arith_done;
1688 #endif
1689                 case 459:       /* divwu */
1690                         op->val = (unsigned int) regs->gpr[ra] /
1691                                 (unsigned int) regs->gpr[rb];
1692                         goto arith_done;
1693 #ifdef __powerpc64__
1694                 case 489:       /* divd */
1695                         op->val = (long int) regs->gpr[ra] /
1696                                 (long int) regs->gpr[rb];
1697                         goto arith_done;
1698 #endif
1699                 case 491:       /* divw */
1700                         op->val = (int) regs->gpr[ra] /
1701                                 (int) regs->gpr[rb];
1702                         goto arith_done;
1703
1704
1705 /*
1706  * Logical instructions
1707  */
1708                 case 26:        /* cntlzw */
1709                         val = (unsigned int) regs->gpr[rd];
1710                         op->val = ( val ? __builtin_clz(val) : 32 );
1711                         goto logical_done;
1712 #ifdef __powerpc64__
1713                 case 58:        /* cntlzd */
1714                         val = regs->gpr[rd];
1715                         op->val = ( val ? __builtin_clzl(val) : 64 );
1716                         goto logical_done;
1717 #endif
1718                 case 28:        /* and */
1719                         op->val = regs->gpr[rd] & regs->gpr[rb];
1720                         goto logical_done;
1721
1722                 case 60:        /* andc */
1723                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1724                         goto logical_done;
1725
1726                 case 122:       /* popcntb */
1727                         do_popcnt(regs, op, regs->gpr[rd], 8);
1728                         goto logical_done_nocc;
1729
1730                 case 124:       /* nor */
1731                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1732                         goto logical_done;
1733
1734                 case 154:       /* prtyw */
1735                         do_prty(regs, op, regs->gpr[rd], 32);
1736                         goto logical_done_nocc;
1737
1738                 case 186:       /* prtyd */
1739                         do_prty(regs, op, regs->gpr[rd], 64);
1740                         goto logical_done_nocc;
1741 #ifdef CONFIG_PPC64
1742                 case 252:       /* bpermd */
1743                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1744                         goto logical_done_nocc;
1745 #endif
1746                 case 284:       /* xor */
1747                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1748                         goto logical_done;
1749
1750                 case 316:       /* xor */
1751                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1752                         goto logical_done;
1753
1754                 case 378:       /* popcntw */
1755                         do_popcnt(regs, op, regs->gpr[rd], 32);
1756                         goto logical_done_nocc;
1757
1758                 case 412:       /* orc */
1759                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1760                         goto logical_done;
1761
1762                 case 444:       /* or */
1763                         op->val = regs->gpr[rd] | regs->gpr[rb];
1764                         goto logical_done;
1765
1766                 case 476:       /* nand */
1767                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1768                         goto logical_done;
1769 #ifdef CONFIG_PPC64
1770                 case 506:       /* popcntd */
1771                         do_popcnt(regs, op, regs->gpr[rd], 64);
1772                         goto logical_done_nocc;
1773 #endif
1774                 case 922:       /* extsh */
1775                         op->val = (signed short) regs->gpr[rd];
1776                         goto logical_done;
1777
1778                 case 954:       /* extsb */
1779                         op->val = (signed char) regs->gpr[rd];
1780                         goto logical_done;
1781 #ifdef __powerpc64__
1782                 case 986:       /* extsw */
1783                         op->val = (signed int) regs->gpr[rd];
1784                         goto logical_done;
1785 #endif
1786
1787 /*
1788  * Shift instructions
1789  */
1790                 case 24:        /* slw */
1791                         sh = regs->gpr[rb] & 0x3f;
1792                         if (sh < 32)
1793                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1794                         else
1795                                 op->val = 0;
1796                         goto logical_done;
1797
1798                 case 536:       /* srw */
1799                         sh = regs->gpr[rb] & 0x3f;
1800                         if (sh < 32)
1801                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1802                         else
1803                                 op->val = 0;
1804                         goto logical_done;
1805
1806                 case 792:       /* sraw */
1807                         op->type = COMPUTE + SETREG + SETXER;
1808                         sh = regs->gpr[rb] & 0x3f;
1809                         ival = (signed int) regs->gpr[rd];
1810                         op->val = ival >> (sh < 32 ? sh : 31);
1811                         op->xerval = regs->xer;
1812                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1813                                 op->xerval |= XER_CA;
1814                         else
1815                                 op->xerval &= ~XER_CA;
1816                         set_ca32(op, op->xerval & XER_CA);
1817                         goto logical_done;
1818
1819                 case 824:       /* srawi */
1820                         op->type = COMPUTE + SETREG + SETXER;
1821                         sh = rb;
1822                         ival = (signed int) regs->gpr[rd];
1823                         op->val = ival >> sh;
1824                         op->xerval = regs->xer;
1825                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1826                                 op->xerval |= XER_CA;
1827                         else
1828                                 op->xerval &= ~XER_CA;
1829                         set_ca32(op, op->xerval & XER_CA);
1830                         goto logical_done;
1831
1832 #ifdef __powerpc64__
1833                 case 27:        /* sld */
1834                         sh = regs->gpr[rb] & 0x7f;
1835                         if (sh < 64)
1836                                 op->val = regs->gpr[rd] << sh;
1837                         else
1838                                 op->val = 0;
1839                         goto logical_done;
1840
1841                 case 539:       /* srd */
1842                         sh = regs->gpr[rb] & 0x7f;
1843                         if (sh < 64)
1844                                 op->val = regs->gpr[rd] >> sh;
1845                         else
1846                                 op->val = 0;
1847                         goto logical_done;
1848
1849                 case 794:       /* srad */
1850                         op->type = COMPUTE + SETREG + SETXER;
1851                         sh = regs->gpr[rb] & 0x7f;
1852                         ival = (signed long int) regs->gpr[rd];
1853                         op->val = ival >> (sh < 64 ? sh : 63);
1854                         op->xerval = regs->xer;
1855                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1856                                 op->xerval |= XER_CA;
1857                         else
1858                                 op->xerval &= ~XER_CA;
1859                         set_ca32(op, op->xerval & XER_CA);
1860                         goto logical_done;
1861
1862                 case 826:       /* sradi with sh_5 = 0 */
1863                 case 827:       /* sradi with sh_5 = 1 */
1864                         op->type = COMPUTE + SETREG + SETXER;
1865                         sh = rb | ((instr & 2) << 4);
1866                         ival = (signed long int) regs->gpr[rd];
1867                         op->val = ival >> sh;
1868                         op->xerval = regs->xer;
1869                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1870                                 op->xerval |= XER_CA;
1871                         else
1872                                 op->xerval &= ~XER_CA;
1873                         set_ca32(op, op->xerval & XER_CA);
1874                         goto logical_done;
1875 #endif /* __powerpc64__ */
1876
1877 /*
1878  * Cache instructions
1879  */
1880                 case 54:        /* dcbst */
1881                         op->type = MKOP(CACHEOP, DCBST, 0);
1882                         op->ea = xform_ea(instr, regs);
1883                         return 0;
1884
1885                 case 86:        /* dcbf */
1886                         op->type = MKOP(CACHEOP, DCBF, 0);
1887                         op->ea = xform_ea(instr, regs);
1888                         return 0;
1889
1890                 case 246:       /* dcbtst */
1891                         op->type = MKOP(CACHEOP, DCBTST, 0);
1892                         op->ea = xform_ea(instr, regs);
1893                         op->reg = rd;
1894                         return 0;
1895
1896                 case 278:       /* dcbt */
1897                         op->type = MKOP(CACHEOP, DCBTST, 0);
1898                         op->ea = xform_ea(instr, regs);
1899                         op->reg = rd;
1900                         return 0;
1901
1902                 case 982:       /* icbi */
1903                         op->type = MKOP(CACHEOP, ICBI, 0);
1904                         op->ea = xform_ea(instr, regs);
1905                         return 0;
1906
1907                 case 1014:      /* dcbz */
1908                         op->type = MKOP(CACHEOP, DCBZ, 0);
1909                         op->ea = xform_ea(instr, regs);
1910                         return 0;
1911                 }
1912                 break;
1913         }
1914
1915 /*
1916  * Loads and stores.
1917  */
1918         op->type = UNKNOWN;
1919         op->update_reg = ra;
1920         op->reg = rd;
1921         op->val = regs->gpr[rd];
1922         u = (instr >> 20) & UPDATE;
1923         op->vsx_flags = 0;
1924
1925         switch (opcode) {
1926         case 31:
1927                 u = instr & UPDATE;
1928                 op->ea = xform_ea(instr, regs);
1929                 switch ((instr >> 1) & 0x3ff) {
1930                 case 20:        /* lwarx */
1931                         op->type = MKOP(LARX, 0, 4);
1932                         break;
1933
1934                 case 150:       /* stwcx. */
1935                         op->type = MKOP(STCX, 0, 4);
1936                         break;
1937
1938 #ifdef __powerpc64__
1939                 case 84:        /* ldarx */
1940                         op->type = MKOP(LARX, 0, 8);
1941                         break;
1942
1943                 case 214:       /* stdcx. */
1944                         op->type = MKOP(STCX, 0, 8);
1945                         break;
1946
1947                 case 52:        /* lbarx */
1948                         op->type = MKOP(LARX, 0, 1);
1949                         break;
1950
1951                 case 694:       /* stbcx. */
1952                         op->type = MKOP(STCX, 0, 1);
1953                         break;
1954
1955                 case 116:       /* lharx */
1956                         op->type = MKOP(LARX, 0, 2);
1957                         break;
1958
1959                 case 726:       /* sthcx. */
1960                         op->type = MKOP(STCX, 0, 2);
1961                         break;
1962
1963                 case 276:       /* lqarx */
1964                         if (!((rd & 1) || rd == ra || rd == rb))
1965                                 op->type = MKOP(LARX, 0, 16);
1966                         break;
1967
1968                 case 182:       /* stqcx. */
1969                         if (!(rd & 1))
1970                                 op->type = MKOP(STCX, 0, 16);
1971                         break;
1972 #endif
1973
1974                 case 23:        /* lwzx */
1975                 case 55:        /* lwzux */
1976                         op->type = MKOP(LOAD, u, 4);
1977                         break;
1978
1979                 case 87:        /* lbzx */
1980                 case 119:       /* lbzux */
1981                         op->type = MKOP(LOAD, u, 1);
1982                         break;
1983
1984 #ifdef CONFIG_ALTIVEC
1985                 /*
1986                  * Note: for the load/store vector element instructions,
1987                  * bits of the EA say which field of the VMX register to use.
1988                  */
1989                 case 7:         /* lvebx */
1990                         op->type = MKOP(LOAD_VMX, 0, 1);
1991                         op->element_size = 1;
1992                         break;
1993
1994                 case 39:        /* lvehx */
1995                         op->type = MKOP(LOAD_VMX, 0, 2);
1996                         op->element_size = 2;
1997                         break;
1998
1999                 case 71:        /* lvewx */
2000                         op->type = MKOP(LOAD_VMX, 0, 4);
2001                         op->element_size = 4;
2002                         break;
2003
2004                 case 103:       /* lvx */
2005                 case 359:       /* lvxl */
2006                         op->type = MKOP(LOAD_VMX, 0, 16);
2007                         op->element_size = 16;
2008                         break;
2009
2010                 case 135:       /* stvebx */
2011                         op->type = MKOP(STORE_VMX, 0, 1);
2012                         op->element_size = 1;
2013                         break;
2014
2015                 case 167:       /* stvehx */
2016                         op->type = MKOP(STORE_VMX, 0, 2);
2017                         op->element_size = 2;
2018                         break;
2019
2020                 case 199:       /* stvewx */
2021                         op->type = MKOP(STORE_VMX, 0, 4);
2022                         op->element_size = 4;
2023                         break;
2024
2025                 case 231:       /* stvx */
2026                 case 487:       /* stvxl */
2027                         op->type = MKOP(STORE_VMX, 0, 16);
2028                         break;
2029 #endif /* CONFIG_ALTIVEC */
2030
2031 #ifdef __powerpc64__
2032                 case 21:        /* ldx */
2033                 case 53:        /* ldux */
2034                         op->type = MKOP(LOAD, u, 8);
2035                         break;
2036
2037                 case 149:       /* stdx */
2038                 case 181:       /* stdux */
2039                         op->type = MKOP(STORE, u, 8);
2040                         break;
2041 #endif
2042
2043                 case 151:       /* stwx */
2044                 case 183:       /* stwux */
2045                         op->type = MKOP(STORE, u, 4);
2046                         break;
2047
2048                 case 215:       /* stbx */
2049                 case 247:       /* stbux */
2050                         op->type = MKOP(STORE, u, 1);
2051                         break;
2052
2053                 case 279:       /* lhzx */
2054                 case 311:       /* lhzux */
2055                         op->type = MKOP(LOAD, u, 2);
2056                         break;
2057
2058 #ifdef __powerpc64__
2059                 case 341:       /* lwax */
2060                 case 373:       /* lwaux */
2061                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2062                         break;
2063 #endif
2064
2065                 case 343:       /* lhax */
2066                 case 375:       /* lhaux */
2067                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2068                         break;
2069
2070                 case 407:       /* sthx */
2071                 case 439:       /* sthux */
2072                         op->type = MKOP(STORE, u, 2);
2073                         break;
2074
2075 #ifdef __powerpc64__
2076                 case 532:       /* ldbrx */
2077                         op->type = MKOP(LOAD, BYTEREV, 8);
2078                         break;
2079
2080 #endif
2081                 case 533:       /* lswx */
2082                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2083                         break;
2084
2085                 case 534:       /* lwbrx */
2086                         op->type = MKOP(LOAD, BYTEREV, 4);
2087                         break;
2088
2089                 case 597:       /* lswi */
2090                         if (rb == 0)
2091                                 rb = 32;        /* # bytes to load */
2092                         op->type = MKOP(LOAD_MULTI, 0, rb);
2093                         op->ea = ra ? regs->gpr[ra] : 0;
2094                         break;
2095
2096 #ifdef CONFIG_PPC_FPU
2097                 case 535:       /* lfsx */
2098                 case 567:       /* lfsux */
2099                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2100                         break;
2101
2102                 case 599:       /* lfdx */
2103                 case 631:       /* lfdux */
2104                         op->type = MKOP(LOAD_FP, u, 8);
2105                         break;
2106
2107                 case 663:       /* stfsx */
2108                 case 695:       /* stfsux */
2109                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2110                         break;
2111
2112                 case 727:       /* stfdx */
2113                 case 759:       /* stfdux */
2114                         op->type = MKOP(STORE_FP, u, 8);
2115                         break;
2116
2117 #ifdef __powerpc64__
2118                 case 791:       /* lfdpx */
2119                         op->type = MKOP(LOAD_FP, 0, 16);
2120                         break;
2121
2122                 case 855:       /* lfiwax */
2123                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2124                         break;
2125
2126                 case 887:       /* lfiwzx */
2127                         op->type = MKOP(LOAD_FP, 0, 4);
2128                         break;
2129
2130                 case 919:       /* stfdpx */
2131                         op->type = MKOP(STORE_FP, 0, 16);
2132                         break;
2133
2134                 case 983:       /* stfiwx */
2135                         op->type = MKOP(STORE_FP, 0, 4);
2136                         break;
2137 #endif /* __powerpc64 */
2138 #endif /* CONFIG_PPC_FPU */
2139
2140 #ifdef __powerpc64__
2141                 case 660:       /* stdbrx */
2142                         op->type = MKOP(STORE, BYTEREV, 8);
2143                         op->val = byterev_8(regs->gpr[rd]);
2144                         break;
2145
2146 #endif
2147                 case 661:       /* stswx */
2148                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2149                         break;
2150
2151                 case 662:       /* stwbrx */
2152                         op->type = MKOP(STORE, BYTEREV, 4);
2153                         op->val = byterev_4(regs->gpr[rd]);
2154                         break;
2155
2156                 case 725:       /* stswi */
2157                         if (rb == 0)
2158                                 rb = 32;        /* # bytes to store */
2159                         op->type = MKOP(STORE_MULTI, 0, rb);
2160                         op->ea = ra ? regs->gpr[ra] : 0;
2161                         break;
2162
2163                 case 790:       /* lhbrx */
2164                         op->type = MKOP(LOAD, BYTEREV, 2);
2165                         break;
2166
2167                 case 918:       /* sthbrx */
2168                         op->type = MKOP(STORE, BYTEREV, 2);
2169                         op->val = byterev_2(regs->gpr[rd]);
2170                         break;
2171
2172 #ifdef CONFIG_VSX
2173                 case 12:        /* lxsiwzx */
2174                         op->reg = rd | ((instr & 1) << 5);
2175                         op->type = MKOP(LOAD_VSX, 0, 4);
2176                         op->element_size = 8;
2177                         break;
2178
2179                 case 76:        /* lxsiwax */
2180                         op->reg = rd | ((instr & 1) << 5);
2181                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2182                         op->element_size = 8;
2183                         break;
2184
2185                 case 140:       /* stxsiwx */
2186                         op->reg = rd | ((instr & 1) << 5);
2187                         op->type = MKOP(STORE_VSX, 0, 4);
2188                         op->element_size = 8;
2189                         break;
2190
2191                 case 268:       /* lxvx */
2192                         op->reg = rd | ((instr & 1) << 5);
2193                         op->type = MKOP(LOAD_VSX, 0, 16);
2194                         op->element_size = 16;
2195                         op->vsx_flags = VSX_CHECK_VEC;
2196                         break;
2197
2198                 case 269:       /* lxvl */
2199                 case 301: {     /* lxvll */
2200                         int nb;
2201                         op->reg = rd | ((instr & 1) << 5);
2202                         op->ea = ra ? regs->gpr[ra] : 0;
2203                         nb = regs->gpr[rb] & 0xff;
2204                         if (nb > 16)
2205                                 nb = 16;
2206                         op->type = MKOP(LOAD_VSX, 0, nb);
2207                         op->element_size = 16;
2208                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2209                                 VSX_CHECK_VEC;
2210                         break;
2211                 }
2212                 case 332:       /* lxvdsx */
2213                         op->reg = rd | ((instr & 1) << 5);
2214                         op->type = MKOP(LOAD_VSX, 0, 8);
2215                         op->element_size = 8;
2216                         op->vsx_flags = VSX_SPLAT;
2217                         break;
2218
2219                 case 364:       /* lxvwsx */
2220                         op->reg = rd | ((instr & 1) << 5);
2221                         op->type = MKOP(LOAD_VSX, 0, 4);
2222                         op->element_size = 4;
2223                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2224                         break;
2225
2226                 case 396:       /* stxvx */
2227                         op->reg = rd | ((instr & 1) << 5);
2228                         op->type = MKOP(STORE_VSX, 0, 16);
2229                         op->element_size = 16;
2230                         op->vsx_flags = VSX_CHECK_VEC;
2231                         break;
2232
2233                 case 397:       /* stxvl */
2234                 case 429: {     /* stxvll */
2235                         int nb;
2236                         op->reg = rd | ((instr & 1) << 5);
2237                         op->ea = ra ? regs->gpr[ra] : 0;
2238                         nb = regs->gpr[rb] & 0xff;
2239                         if (nb > 16)
2240                                 nb = 16;
2241                         op->type = MKOP(STORE_VSX, 0, nb);
2242                         op->element_size = 16;
2243                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2244                                 VSX_CHECK_VEC;
2245                         break;
2246                 }
2247                 case 524:       /* lxsspx */
2248                         op->reg = rd | ((instr & 1) << 5);
2249                         op->type = MKOP(LOAD_VSX, 0, 4);
2250                         op->element_size = 8;
2251                         op->vsx_flags = VSX_FPCONV;
2252                         break;
2253
2254                 case 588:       /* lxsdx */
2255                         op->reg = rd | ((instr & 1) << 5);
2256                         op->type = MKOP(LOAD_VSX, 0, 8);
2257                         op->element_size = 8;
2258                         break;
2259
2260                 case 652:       /* stxsspx */
2261                         op->reg = rd | ((instr & 1) << 5);
2262                         op->type = MKOP(STORE_VSX, 0, 4);
2263                         op->element_size = 8;
2264                         op->vsx_flags = VSX_FPCONV;
2265                         break;
2266
2267                 case 716:       /* stxsdx */
2268                         op->reg = rd | ((instr & 1) << 5);
2269                         op->type = MKOP(STORE_VSX, 0, 8);
2270                         op->element_size = 8;
2271                         break;
2272
2273                 case 780:       /* lxvw4x */
2274                         op->reg = rd | ((instr & 1) << 5);
2275                         op->type = MKOP(LOAD_VSX, 0, 16);
2276                         op->element_size = 4;
2277                         break;
2278
2279                 case 781:       /* lxsibzx */
2280                         op->reg = rd | ((instr & 1) << 5);
2281                         op->type = MKOP(LOAD_VSX, 0, 1);
2282                         op->element_size = 8;
2283                         op->vsx_flags = VSX_CHECK_VEC;
2284                         break;
2285
2286                 case 812:       /* lxvh8x */
2287                         op->reg = rd | ((instr & 1) << 5);
2288                         op->type = MKOP(LOAD_VSX, 0, 16);
2289                         op->element_size = 2;
2290                         op->vsx_flags = VSX_CHECK_VEC;
2291                         break;
2292
2293                 case 813:       /* lxsihzx */
2294                         op->reg = rd | ((instr & 1) << 5);
2295                         op->type = MKOP(LOAD_VSX, 0, 2);
2296                         op->element_size = 8;
2297                         op->vsx_flags = VSX_CHECK_VEC;
2298                         break;
2299
2300                 case 844:       /* lxvd2x */
2301                         op->reg = rd | ((instr & 1) << 5);
2302                         op->type = MKOP(LOAD_VSX, 0, 16);
2303                         op->element_size = 8;
2304                         break;
2305
2306                 case 876:       /* lxvb16x */
2307                         op->reg = rd | ((instr & 1) << 5);
2308                         op->type = MKOP(LOAD_VSX, 0, 16);
2309                         op->element_size = 1;
2310                         op->vsx_flags = VSX_CHECK_VEC;
2311                         break;
2312
2313                 case 908:       /* stxvw4x */
2314                         op->reg = rd | ((instr & 1) << 5);
2315                         op->type = MKOP(STORE_VSX, 0, 16);
2316                         op->element_size = 4;
2317                         break;
2318
2319                 case 909:       /* stxsibx */
2320                         op->reg = rd | ((instr & 1) << 5);
2321                         op->type = MKOP(STORE_VSX, 0, 1);
2322                         op->element_size = 8;
2323                         op->vsx_flags = VSX_CHECK_VEC;
2324                         break;
2325
2326                 case 940:       /* stxvh8x */
2327                         op->reg = rd | ((instr & 1) << 5);
2328                         op->type = MKOP(STORE_VSX, 0, 16);
2329                         op->element_size = 2;
2330                         op->vsx_flags = VSX_CHECK_VEC;
2331                         break;
2332
2333                 case 941:       /* stxsihx */
2334                         op->reg = rd | ((instr & 1) << 5);
2335                         op->type = MKOP(STORE_VSX, 0, 2);
2336                         op->element_size = 8;
2337                         op->vsx_flags = VSX_CHECK_VEC;
2338                         break;
2339
2340                 case 972:       /* stxvd2x */
2341                         op->reg = rd | ((instr & 1) << 5);
2342                         op->type = MKOP(STORE_VSX, 0, 16);
2343                         op->element_size = 8;
2344                         break;
2345
2346                 case 1004:      /* stxvb16x */
2347                         op->reg = rd | ((instr & 1) << 5);
2348                         op->type = MKOP(STORE_VSX, 0, 16);
2349                         op->element_size = 1;
2350                         op->vsx_flags = VSX_CHECK_VEC;
2351                         break;
2352
2353 #endif /* CONFIG_VSX */
2354                 }
2355                 break;
2356
2357         case 32:        /* lwz */
2358         case 33:        /* lwzu */
2359                 op->type = MKOP(LOAD, u, 4);
2360                 op->ea = dform_ea(instr, regs);
2361                 break;
2362
2363         case 34:        /* lbz */
2364         case 35:        /* lbzu */
2365                 op->type = MKOP(LOAD, u, 1);
2366                 op->ea = dform_ea(instr, regs);
2367                 break;
2368
2369         case 36:        /* stw */
2370         case 37:        /* stwu */
2371                 op->type = MKOP(STORE, u, 4);
2372                 op->ea = dform_ea(instr, regs);
2373                 break;
2374
2375         case 38:        /* stb */
2376         case 39:        /* stbu */
2377                 op->type = MKOP(STORE, u, 1);
2378                 op->ea = dform_ea(instr, regs);
2379                 break;
2380
2381         case 40:        /* lhz */
2382         case 41:        /* lhzu */
2383                 op->type = MKOP(LOAD, u, 2);
2384                 op->ea = dform_ea(instr, regs);
2385                 break;
2386
2387         case 42:        /* lha */
2388         case 43:        /* lhau */
2389                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2390                 op->ea = dform_ea(instr, regs);
2391                 break;
2392
2393         case 44:        /* sth */
2394         case 45:        /* sthu */
2395                 op->type = MKOP(STORE, u, 2);
2396                 op->ea = dform_ea(instr, regs);
2397                 break;
2398
2399         case 46:        /* lmw */
2400                 if (ra >= rd)
2401                         break;          /* invalid form, ra in range to load */
2402                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2403                 op->ea = dform_ea(instr, regs);
2404                 break;
2405
2406         case 47:        /* stmw */
2407                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2408                 op->ea = dform_ea(instr, regs);
2409                 break;
2410
2411 #ifdef CONFIG_PPC_FPU
2412         case 48:        /* lfs */
2413         case 49:        /* lfsu */
2414                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2415                 op->ea = dform_ea(instr, regs);
2416                 break;
2417
2418         case 50:        /* lfd */
2419         case 51:        /* lfdu */
2420                 op->type = MKOP(LOAD_FP, u, 8);
2421                 op->ea = dform_ea(instr, regs);
2422                 break;
2423
2424         case 52:        /* stfs */
2425         case 53:        /* stfsu */
2426                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2427                 op->ea = dform_ea(instr, regs);
2428                 break;
2429
2430         case 54:        /* stfd */
2431         case 55:        /* stfdu */
2432                 op->type = MKOP(STORE_FP, u, 8);
2433                 op->ea = dform_ea(instr, regs);
2434                 break;
2435 #endif
2436
2437 #ifdef __powerpc64__
2438         case 56:        /* lq */
2439                 if (!((rd & 1) || (rd == ra)))
2440                         op->type = MKOP(LOAD, 0, 16);
2441                 op->ea = dqform_ea(instr, regs);
2442                 break;
2443 #endif
2444
2445 #ifdef CONFIG_VSX
2446         case 57:        /* lfdp, lxsd, lxssp */
2447                 op->ea = dsform_ea(instr, regs);
2448                 switch (instr & 3) {
2449                 case 0:         /* lfdp */
2450                         if (rd & 1)
2451                                 break;          /* reg must be even */
2452                         op->type = MKOP(LOAD_FP, 0, 16);
2453                         break;
2454                 case 2:         /* lxsd */
2455                         op->reg = rd + 32;
2456                         op->type = MKOP(LOAD_VSX, 0, 8);
2457                         op->element_size = 8;
2458                         op->vsx_flags = VSX_CHECK_VEC;
2459                         break;
2460                 case 3:         /* lxssp */
2461                         op->reg = rd + 32;
2462                         op->type = MKOP(LOAD_VSX, 0, 4);
2463                         op->element_size = 8;
2464                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2465                         break;
2466                 }
2467                 break;
2468 #endif /* CONFIG_VSX */
2469
2470 #ifdef __powerpc64__
2471         case 58:        /* ld[u], lwa */
2472                 op->ea = dsform_ea(instr, regs);
2473                 switch (instr & 3) {
2474                 case 0:         /* ld */
2475                         op->type = MKOP(LOAD, 0, 8);
2476                         break;
2477                 case 1:         /* ldu */
2478                         op->type = MKOP(LOAD, UPDATE, 8);
2479                         break;
2480                 case 2:         /* lwa */
2481                         op->type = MKOP(LOAD, SIGNEXT, 4);
2482                         break;
2483                 }
2484                 break;
2485 #endif
2486
2487 #ifdef CONFIG_VSX
2488         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2489                 switch (instr & 7) {
2490                 case 0:         /* stfdp with LSB of DS field = 0 */
2491                 case 4:         /* stfdp with LSB of DS field = 1 */
2492                         op->ea = dsform_ea(instr, regs);
2493                         op->type = MKOP(STORE_FP, 0, 16);
2494                         break;
2495
2496                 case 1:         /* lxv */
2497                         op->ea = dqform_ea(instr, regs);
2498                         if (instr & 8)
2499                                 op->reg = rd + 32;
2500                         op->type = MKOP(LOAD_VSX, 0, 16);
2501                         op->element_size = 16;
2502                         op->vsx_flags = VSX_CHECK_VEC;
2503                         break;
2504
2505                 case 2:         /* stxsd with LSB of DS field = 0 */
2506                 case 6:         /* stxsd with LSB of DS field = 1 */
2507                         op->ea = dsform_ea(instr, regs);
2508                         op->reg = rd + 32;
2509                         op->type = MKOP(STORE_VSX, 0, 8);
2510                         op->element_size = 8;
2511                         op->vsx_flags = VSX_CHECK_VEC;
2512                         break;
2513
2514                 case 3:         /* stxssp with LSB of DS field = 0 */
2515                 case 7:         /* stxssp with LSB of DS field = 1 */
2516                         op->ea = dsform_ea(instr, regs);
2517                         op->reg = rd + 32;
2518                         op->type = MKOP(STORE_VSX, 0, 4);
2519                         op->element_size = 8;
2520                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2521                         break;
2522
2523                 case 5:         /* stxv */
2524                         op->ea = dqform_ea(instr, regs);
2525                         if (instr & 8)
2526                                 op->reg = rd + 32;
2527                         op->type = MKOP(STORE_VSX, 0, 16);
2528                         op->element_size = 16;
2529                         op->vsx_flags = VSX_CHECK_VEC;
2530                         break;
2531                 }
2532                 break;
2533 #endif /* CONFIG_VSX */
2534
2535 #ifdef __powerpc64__
2536         case 62:        /* std[u] */
2537                 op->ea = dsform_ea(instr, regs);
2538                 switch (instr & 3) {
2539                 case 0:         /* std */
2540                         op->type = MKOP(STORE, 0, 8);
2541                         break;
2542                 case 1:         /* stdu */
2543                         op->type = MKOP(STORE, UPDATE, 8);
2544                         break;
2545                 case 2:         /* stq */
2546                         if (!(rd & 1))
2547                                 op->type = MKOP(STORE, 0, 16);
2548                         break;
2549                 }
2550                 break;
2551 #endif /* __powerpc64__ */
2552
2553         }
2554
2555 #ifdef CONFIG_VSX
2556         if ((GETTYPE(op->type) == LOAD_VSX ||
2557              GETTYPE(op->type) == STORE_VSX) &&
2558             !cpu_has_feature(CPU_FTR_VSX)) {
2559                 return -1;
2560         }
2561 #endif /* CONFIG_VSX */
2562
2563         return 0;
2564
2565  logical_done:
2566         if (instr & 1)
2567                 set_cr0(regs, op);
2568  logical_done_nocc:
2569         op->reg = ra;
2570         op->type |= SETREG;
2571         return 1;
2572
2573  arith_done:
2574         if (instr & 1)
2575                 set_cr0(regs, op);
2576  compute_done:
2577         op->reg = rd;
2578         op->type |= SETREG;
2579         return 1;
2580
2581  priv:
2582         op->type = INTERRUPT | 0x700;
2583         op->val = SRR1_PROGPRIV;
2584         return 0;
2585
2586  trap:
2587         op->type = INTERRUPT | 0x700;
2588         op->val = SRR1_PROGTRAP;
2589         return 0;
2590 }
2591 EXPORT_SYMBOL_GPL(analyse_instr);
2592 NOKPROBE_SYMBOL(analyse_instr);
2593
2594 /*
2595  * For PPC32 we always use stwu with r1 to change the stack pointer.
2596  * So this emulated store may corrupt the exception frame, now we
2597  * have to provide the exception frame trampoline, which is pushed
2598  * below the kprobed function stack. So we only update gpr[1] but
2599  * don't emulate the real store operation. We will do real store
2600  * operation safely in exception return code by checking this flag.
2601  */
2602 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2603 {
2604 #ifdef CONFIG_PPC32
2605         /*
2606          * Check if we will touch kernel stack overflow
2607          */
2608         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2609                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2610                 return -EINVAL;
2611         }
2612 #endif /* CONFIG_PPC32 */
2613         /*
2614          * Check if we already set since that means we'll
2615          * lose the previous value.
2616          */
2617         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2618         set_thread_flag(TIF_EMULATE_STACK_STORE);
2619         return 0;
2620 }
2621
2622 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2623 {
2624         switch (size) {
2625         case 2:
2626                 *valp = (signed short) *valp;
2627                 break;
2628         case 4:
2629                 *valp = (signed int) *valp;
2630                 break;
2631         }
2632 }
2633
2634 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2635 {
2636         switch (size) {
2637         case 2:
2638                 *valp = byterev_2(*valp);
2639                 break;
2640         case 4:
2641                 *valp = byterev_4(*valp);
2642                 break;
2643 #ifdef __powerpc64__
2644         case 8:
2645                 *valp = byterev_8(*valp);
2646                 break;
2647 #endif
2648         }
2649 }
2650
2651 /*
2652  * Emulate an instruction that can be executed just by updating
2653  * fields in *regs.
2654  */
2655 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2656 {
2657         unsigned long next_pc;
2658
2659         next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2660         switch (GETTYPE(op->type)) {
2661         case COMPUTE:
2662                 if (op->type & SETREG)
2663                         regs->gpr[op->reg] = op->val;
2664                 if (op->type & SETCC)
2665                         regs->ccr = op->ccval;
2666                 if (op->type & SETXER)
2667                         regs->xer = op->xerval;
2668                 break;
2669
2670         case BRANCH:
2671                 if (op->type & SETLK)
2672                         regs->link = next_pc;
2673                 if (op->type & BRTAKEN)
2674                         next_pc = op->val;
2675                 if (op->type & DECCTR)
2676                         --regs->ctr;
2677                 break;
2678
2679         case BARRIER:
2680                 switch (op->type & BARRIER_MASK) {
2681                 case BARRIER_SYNC:
2682                         mb();
2683                         break;
2684                 case BARRIER_ISYNC:
2685                         isync();
2686                         break;
2687                 case BARRIER_EIEIO:
2688                         eieio();
2689                         break;
2690 #ifdef CONFIG_PPC64
2691                 case BARRIER_LWSYNC:
2692                         asm volatile("lwsync" : : : "memory");
2693                         break;
2694                 case BARRIER_PTESYNC:
2695                         asm volatile("ptesync" : : : "memory");
2696                         break;
2697 #endif
2698                 }
2699                 break;
2700
2701         case MFSPR:
2702                 switch (op->spr) {
2703                 case SPRN_XER:
2704                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2705                         break;
2706                 case SPRN_LR:
2707                         regs->gpr[op->reg] = regs->link;
2708                         break;
2709                 case SPRN_CTR:
2710                         regs->gpr[op->reg] = regs->ctr;
2711                         break;
2712                 default:
2713                         WARN_ON_ONCE(1);
2714                 }
2715                 break;
2716
2717         case MTSPR:
2718                 switch (op->spr) {
2719                 case SPRN_XER:
2720                         regs->xer = op->val & 0xffffffffUL;
2721                         break;
2722                 case SPRN_LR:
2723                         regs->link = op->val;
2724                         break;
2725                 case SPRN_CTR:
2726                         regs->ctr = op->val;
2727                         break;
2728                 default:
2729                         WARN_ON_ONCE(1);
2730                 }
2731                 break;
2732
2733         default:
2734                 WARN_ON_ONCE(1);
2735         }
2736         regs->nip = next_pc;
2737 }
2738 NOKPROBE_SYMBOL(emulate_update_regs);
2739
2740 /*
2741  * Emulate a previously-analysed load or store instruction.
2742  * Return values are:
2743  * 0 = instruction emulated successfully
2744  * -EFAULT = address out of range or access faulted (regs->dar
2745  *           contains the faulting address)
2746  * -EACCES = misaligned access, instruction requires alignment
2747  * -EINVAL = unknown operation in *op
2748  */
2749 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
2750 {
2751         int err, size, type;
2752         int i, rd, nb;
2753         unsigned int cr;
2754         unsigned long val;
2755         unsigned long ea;
2756         bool cross_endian;
2757
2758         err = 0;
2759         size = GETSIZE(op->type);
2760         type = GETTYPE(op->type);
2761         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
2762         ea = truncate_if_32bit(regs->msr, op->ea);
2763
2764         switch (type) {
2765         case LARX:
2766                 if (ea & (size - 1))
2767                         return -EACCES;         /* can't handle misaligned */
2768                 if (!address_ok(regs, ea, size))
2769                         return -EFAULT;
2770                 err = 0;
2771                 val = 0;
2772                 switch (size) {
2773 #ifdef __powerpc64__
2774                 case 1:
2775                         __get_user_asmx(val, ea, err, "lbarx");
2776                         break;
2777                 case 2:
2778                         __get_user_asmx(val, ea, err, "lharx");
2779                         break;
2780 #endif
2781                 case 4:
2782                         __get_user_asmx(val, ea, err, "lwarx");
2783                         break;
2784 #ifdef __powerpc64__
2785                 case 8:
2786                         __get_user_asmx(val, ea, err, "ldarx");
2787                         break;
2788                 case 16:
2789                         err = do_lqarx(ea, &regs->gpr[op->reg]);
2790                         break;
2791 #endif
2792                 default:
2793                         return -EINVAL;
2794                 }
2795                 if (err) {
2796                         regs->dar = ea;
2797                         break;
2798                 }
2799                 if (size < 16)
2800                         regs->gpr[op->reg] = val;
2801                 break;
2802
2803         case STCX:
2804                 if (ea & (size - 1))
2805                         return -EACCES;         /* can't handle misaligned */
2806                 if (!address_ok(regs, ea, size))
2807                         return -EFAULT;
2808                 err = 0;
2809                 switch (size) {
2810 #ifdef __powerpc64__
2811                 case 1:
2812                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2813                         break;
2814                 case 2:
2815                         __put_user_asmx(op->val, ea, err, "sthcx.", cr);
2816                         break;
2817 #endif
2818                 case 4:
2819                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
2820                         break;
2821 #ifdef __powerpc64__
2822                 case 8:
2823                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
2824                         break;
2825                 case 16:
2826                         err = do_stqcx(ea, regs->gpr[op->reg],
2827                                        regs->gpr[op->reg + 1], &cr);
2828                         break;
2829 #endif
2830                 default:
2831                         return -EINVAL;
2832                 }
2833                 if (!err)
2834                         regs->ccr = (regs->ccr & 0x0fffffff) |
2835                                 (cr & 0xe0000000) |
2836                                 ((regs->xer >> 3) & 0x10000000);
2837                 else
2838                         regs->dar = ea;
2839                 break;
2840
2841         case LOAD:
2842 #ifdef __powerpc64__
2843                 if (size == 16) {
2844                         err = emulate_lq(regs, ea, op->reg, cross_endian);
2845                         break;
2846                 }
2847 #endif
2848                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
2849                 if (!err) {
2850                         if (op->type & SIGNEXT)
2851                                 do_signext(&regs->gpr[op->reg], size);
2852                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
2853                                 do_byterev(&regs->gpr[op->reg], size);
2854                 }
2855                 break;
2856
2857 #ifdef CONFIG_PPC_FPU
2858         case LOAD_FP:
2859                 /*
2860                  * If the instruction is in userspace, we can emulate it even
2861                  * if the VMX state is not live, because we have the state
2862                  * stored in the thread_struct.  If the instruction is in
2863                  * the kernel, we must not touch the state in the thread_struct.
2864                  */
2865                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2866                         return 0;
2867                 err = do_fp_load(op, ea, regs, cross_endian);
2868                 break;
2869 #endif
2870 #ifdef CONFIG_ALTIVEC
2871         case LOAD_VMX:
2872                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2873                         return 0;
2874                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
2875                 break;
2876 #endif
2877 #ifdef CONFIG_VSX
2878         case LOAD_VSX: {
2879                 unsigned long msrbit = MSR_VSX;
2880
2881                 /*
2882                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2883                  * when the target of the instruction is a vector register.
2884                  */
2885                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2886                         msrbit = MSR_VEC;
2887                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2888                         return 0;
2889                 err = do_vsx_load(op, ea, regs, cross_endian);
2890                 break;
2891         }
2892 #endif
2893         case LOAD_MULTI:
2894                 if (!address_ok(regs, ea, size))
2895                         return -EFAULT;
2896                 rd = op->reg;
2897                 for (i = 0; i < size; i += 4) {
2898                         unsigned int v32 = 0;
2899
2900                         nb = size - i;
2901                         if (nb > 4)
2902                                 nb = 4;
2903                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
2904                         if (err)
2905                                 break;
2906                         if (unlikely(cross_endian))
2907                                 v32 = byterev_4(v32);
2908                         regs->gpr[rd] = v32;
2909                         ea += 4;
2910                         /* reg number wraps from 31 to 0 for lsw[ix] */
2911                         rd = (rd + 1) & 0x1f;
2912                 }
2913                 break;
2914
2915         case STORE:
2916 #ifdef __powerpc64__
2917                 if (size == 16) {
2918                         err = emulate_stq(regs, ea, op->reg, cross_endian);
2919                         break;
2920                 }
2921 #endif
2922                 if ((op->type & UPDATE) && size == sizeof(long) &&
2923                     op->reg == 1 && op->update_reg == 1 &&
2924                     !(regs->msr & MSR_PR) &&
2925                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
2926                         err = handle_stack_update(ea, regs);
2927                         break;
2928                 }
2929                 if (unlikely(cross_endian))
2930                         do_byterev(&op->val, size);
2931                 err = write_mem(op->val, ea, size, regs);
2932                 break;
2933
2934 #ifdef CONFIG_PPC_FPU
2935         case STORE_FP:
2936                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2937                         return 0;
2938                 err = do_fp_store(op, ea, regs, cross_endian);
2939                 break;
2940 #endif
2941 #ifdef CONFIG_ALTIVEC
2942         case STORE_VMX:
2943                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2944                         return 0;
2945                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
2946                 break;
2947 #endif
2948 #ifdef CONFIG_VSX
2949         case STORE_VSX: {
2950                 unsigned long msrbit = MSR_VSX;
2951
2952                 /*
2953                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2954                  * when the target of the instruction is a vector register.
2955                  */
2956                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2957                         msrbit = MSR_VEC;
2958                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2959                         return 0;
2960                 err = do_vsx_store(op, ea, regs, cross_endian);
2961                 break;
2962         }
2963 #endif
2964         case STORE_MULTI:
2965                 if (!address_ok(regs, ea, size))
2966                         return -EFAULT;
2967                 rd = op->reg;
2968                 for (i = 0; i < size; i += 4) {
2969                         unsigned int v32 = regs->gpr[rd];
2970
2971                         nb = size - i;
2972                         if (nb > 4)
2973                                 nb = 4;
2974                         if (unlikely(cross_endian))
2975                                 v32 = byterev_4(v32);
2976                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
2977                         if (err)
2978                                 break;
2979                         ea += 4;
2980                         /* reg number wraps from 31 to 0 for stsw[ix] */
2981                         rd = (rd + 1) & 0x1f;
2982                 }
2983                 break;
2984
2985         default:
2986                 return -EINVAL;
2987         }
2988
2989         if (err)
2990                 return err;
2991
2992         if (op->type & UPDATE)
2993                 regs->gpr[op->update_reg] = op->ea;
2994
2995         return 0;
2996 }
2997 NOKPROBE_SYMBOL(emulate_loadstore);
2998
2999 /*
3000  * Emulate instructions that cause a transfer of control,
3001  * loads and stores, and a few other instructions.
3002  * Returns 1 if the step was emulated, 0 if not,
3003  * or -1 if the instruction is one that should not be stepped,
3004  * such as an rfid, or a mtmsrd that would clear MSR_RI.
3005  */
3006 int emulate_step(struct pt_regs *regs, unsigned int instr)
3007 {
3008         struct instruction_op op;
3009         int r, err, type;
3010         unsigned long val;
3011         unsigned long ea;
3012
3013         r = analyse_instr(&op, regs, instr);
3014         if (r < 0)
3015                 return r;
3016         if (r > 0) {
3017                 emulate_update_regs(regs, &op);
3018                 return 1;
3019         }
3020
3021         err = 0;
3022         type = GETTYPE(op.type);
3023
3024         if (OP_IS_LOAD_STORE(type)) {
3025                 err = emulate_loadstore(regs, &op);
3026                 if (err)
3027                         return 0;
3028                 goto instr_done;
3029         }
3030
3031         switch (type) {
3032         case CACHEOP:
3033                 ea = truncate_if_32bit(regs->msr, op.ea);
3034                 if (!address_ok(regs, ea, 8))
3035                         return 0;
3036                 switch (op.type & CACHEOP_MASK) {
3037                 case DCBST:
3038                         __cacheop_user_asmx(ea, err, "dcbst");
3039                         break;
3040                 case DCBF:
3041                         __cacheop_user_asmx(ea, err, "dcbf");
3042                         break;
3043                 case DCBTST:
3044                         if (op.reg == 0)
3045                                 prefetchw((void *) ea);
3046                         break;
3047                 case DCBT:
3048                         if (op.reg == 0)
3049                                 prefetch((void *) ea);
3050                         break;
3051                 case ICBI:
3052                         __cacheop_user_asmx(ea, err, "icbi");
3053                         break;
3054                 case DCBZ:
3055                         err = emulate_dcbz(ea, regs);
3056                         break;
3057                 }
3058                 if (err) {
3059                         regs->dar = ea;
3060                         return 0;
3061                 }
3062                 goto instr_done;
3063
3064         case MFMSR:
3065                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3066                 goto instr_done;
3067
3068         case MTMSR:
3069                 val = regs->gpr[op.reg];
3070                 if ((val & MSR_RI) == 0)
3071                         /* can't step mtmsr[d] that would clear MSR_RI */
3072                         return -1;
3073                 /* here op.val is the mask of bits to change */
3074                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3075                 goto instr_done;
3076
3077 #ifdef CONFIG_PPC64
3078         case SYSCALL:   /* sc */
3079                 /*
3080                  * N.B. this uses knowledge about how the syscall
3081                  * entry code works.  If that is changed, this will
3082                  * need to be changed also.
3083                  */
3084                 if (regs->gpr[0] == 0x1ebe &&
3085                     cpu_has_feature(CPU_FTR_REAL_LE)) {
3086                         regs->msr ^= MSR_LE;
3087                         goto instr_done;
3088                 }
3089                 regs->gpr[9] = regs->gpr[13];
3090                 regs->gpr[10] = MSR_KERNEL;
3091                 regs->gpr[11] = regs->nip + 4;
3092                 regs->gpr[12] = regs->msr & MSR_MASK;
3093                 regs->gpr[13] = (unsigned long) get_paca();
3094                 regs->nip = (unsigned long) &system_call_common;
3095                 regs->msr = MSR_KERNEL;
3096                 return 1;
3097
3098         case RFI:
3099                 return -1;
3100 #endif
3101         }
3102         return 0;
3103
3104  instr_done:
3105         regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3106         return 1;
3107 }
3108 NOKPROBE_SYMBOL(emulate_step);