2 * Low-level SLB routines
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
6 * Based on earlier C version:
7 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
8 * Copyright (c) 2001 Dave Engebretsen
9 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <asm/processor.h>
18 #include <asm/ppc_asm.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/cputable.h>
23 #include <asm/pgtable.h>
24 #include <asm/firmware.h>
26 /* void slb_allocate_realmode(unsigned long ea);
28 * Create an SLB entry for the given EA (user or kernel).
29 * r3 = faulting address, r13 = PACA
30 * r9, r10, r11 are clobbered by this function
31 * No other registers are examined or changed.
33 _GLOBAL(slb_allocate_realmode)
35 * check for bad kernel/user address
36 * (ea & ~REGION_MASK) >= PGTABLE_RANGE
38 rldicr. r9,r3,4,(63 - PGTABLE_EADDR_SIZE - 4)
41 srdi r9,r3,60 /* get region */
42 srdi r10,r3,SID_SHIFT /* get esid */
43 cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
45 /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
46 blt cr7,0f /* user or kernel? */
48 /* kernel address: proto-VSID = ESID */
49 /* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
50 * this code will generate the protoVSID 0xfffffffff for the
51 * top segment. That's ok, the scramble below will translate
52 * it to VSID 0, which is reserved as a bad VSID - one which
53 * will never have any pages in it. */
55 /* Check if hitting the linear mapping or some other kernel space
59 /* Linear mapping encoding bits, the "li" instruction below will
60 * be patched by the kernel at boot
62 .globl slb_miss_kernel_load_linear
63 slb_miss_kernel_load_linear:
66 * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
69 addis r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha
70 addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l
75 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
79 #ifdef CONFIG_SPARSEMEM_VMEMMAP
80 /* Check virtual memmap region. To be patches at kernel boot */
83 .globl slb_miss_kernel_load_vmemmap
84 slb_miss_kernel_load_vmemmap:
88 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
90 /* vmalloc mapping gets the encoding from the PACA as the mapping
91 * can be demoted from 64K -> 4K dynamically on some machines
94 cmpldi r11,(VMALLOC_SIZE >> 28) - 1
96 lhz r11,PACAVMALLOCSLLP(r13)
100 .globl slb_miss_kernel_load_io
101 slb_miss_kernel_load_io:
105 * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
108 addis r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha
109 addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l
113 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
117 * For userspace addresses, make sure this is region 0.
122 /* when using slices, we extract the psize off the slice bitmaps
123 * and then we need to get the sllp encoding off the mmu_psize_defs
126 * XXX This is a bit inefficient especially for the normal case,
127 * so we should try to implement a fast path for the standard page
128 * size using the old sllp value so we avoid the array. We cannot
129 * really do dynamic patching unfortunately as processes might flip
130 * between 4k and 64k standard page size
132 #ifdef CONFIG_PPC_MM_SLICES
135 /* below SLICE_LOW_TOP */
139 * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
141 srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
142 addi r9,r11,PACAHIGHSLICEPSIZE
143 lbzx r9,r13,r9 /* r9 is hpsizes[r11] */
144 /* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
145 rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
151 * r9 is get_paca()->context.low_slices_psize, r11 is index
153 ld r9,PACALOWSLICESPSIZE(r13)
156 sldi r11,r11,2 /* index * 4 */
157 /* Extract the psize and multiply to get an array offset */
160 mulli r9,r9,MMUPSIZEDEFSIZE
162 /* Now get to the array and obtain the sllp
165 ld r11,mmu_psize_defs@got(r11)
167 ld r11,MMUPSIZESLLP(r11)
168 ori r11,r11,SLB_VSID_USER
170 /* paca context sllp already contains the SLB_VSID_USER bits */
171 lhz r11,PACACONTEXTSLLP(r13)
172 #endif /* CONFIG_PPC_MM_SLICES */
174 ld r9,PACACONTEXTID(r13)
177 bge slb_finish_load_1T
178 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
183 * It's possible the bad EA is too large to fit in the SLB cache, which
184 * would mean we'd fail to invalidate it on context switch. So mark the
185 * SLB cache as full so we force a full flush. We also set cr7+eq to
186 * mark the address as a kernel address, so slb_finish_load() skips
187 * trying to insert it into the SLB cache.
189 li r9,SLB_CACHE_ENTRIES + 1
190 sth r9,PACASLBCACHEPTR(r13)
192 li r10,0 /* BAD_VSID */
193 li r9,0 /* BAD_VSID */
194 li r11,SLB_VSID_USER /* flags don't much matter */
199 /* void slb_allocate_user(unsigned long ea);
201 * Create an SLB entry for the given EA (user or kernel).
202 * r3 = faulting address, r13 = PACA
203 * r9, r10, r11 are clobbered by this function
204 * No other registers are examined or changed.
206 * It is called with translation enabled in order to be able to walk the
207 * page tables. This is not currently used.
209 _GLOBAL(slb_allocate_user)
210 /* r3 = faulting address */
211 srdi r10,r3,28 /* get esid */
213 crset 4*cr7+lt /* set "user" flag for later */
215 /* check if we fit in the range covered by the pagetables*/
216 srdi. r9,r3,PGTABLE_EADDR_SIZE
217 crnot 4*cr0+eq,4*cr0+eq
220 /* now we need to get to the page tables in order to get the page
221 * size encoding from the PMD. In the future, we'll be able to deal
222 * with 1T segments too by getting the encoding from the PGD instead
227 rlwinm r11,r10,8,25,28
228 ldx r9,r9,r11 /* get pgd_t */
231 rlwinm r11,r10,3,17,28
232 ldx r9,r9,r11 /* get pmd_t */
236 /* build vsid flags */
237 andi. r11,r9,SLB_VSID_LLP
238 ori r11,r11,SLB_VSID_USER
240 /* get context to calculate proto-VSID */
241 ld r9,PACACONTEXTID(r13)
242 /* fall through slb_finish_load */
244 #endif /* __DISABLED__ */
248 * Finish loading of an SLB entry and return
250 * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
253 rldimi r10,r9,ESID_BITS,0
254 ASM_VSID_SCRAMBLE(r10,r9,256M)
256 * bits above VSID_BITS_256M need to be ignored from r10
257 * also combine VSID and flags
259 rldimi r11,r10,SLB_VSID_SHIFT,(64 - (SLB_VSID_SHIFT + VSID_BITS_256M))
261 /* r3 = EA, r11 = VSID data */
263 * Find a slot, round robin. Previously we tried to find a
264 * free slot first but that took too long. Unfortunately we
265 * dont have any LRU information to help us choose a slot.
268 7: ld r10,PACASTABRR(r13)
270 /* This gets soft patched on boot. */
271 .globl slb_compare_rr_to_size
272 slb_compare_rr_to_size:
276 li r10,SLB_NUM_BOLTED
279 std r10,PACASTABRR(r13)
282 rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */
283 oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
285 /* r3 = ESID data, r11 = VSID data */
288 * No need for an isync before or after this slbmte. The exception
289 * we enter with and the rfid we exit with are context synchronizing.
293 /* we're done for kernel addresses */
294 crclr 4*cr0+eq /* set result to "success" */
297 /* Update the slb cache */
298 lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
299 cmpldi r3,SLB_CACHE_ENTRIES
302 /* still room in the slb cache */
303 sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
304 srdi r10,r10,28 /* get the 36 bits of the ESID */
305 add r11,r11,r13 /* r11 = (u32 *)paca + offset */
306 stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
307 addi r3,r3,1 /* offset++ */
309 1: /* offset >= SLB_CACHE_ENTRIES */
310 li r3,SLB_CACHE_ENTRIES+1
312 sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
313 crclr 4*cr0+eq /* set result to "success" */
317 * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
319 * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
322 srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
323 rldimi r10,r9,ESID_BITS_1T,0
324 ASM_VSID_SCRAMBLE(r10,r9,1T)
326 * bits above VSID_BITS_1T need to be ignored from r10
327 * also combine VSID and flags
329 rldimi r11,r10,SLB_VSID_SHIFT_1T,(64 - (SLB_VSID_SHIFT_1T + VSID_BITS_1T))
330 li r10,MMU_SEGSIZE_1T
331 rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
333 /* r3 = EA, r11 = VSID data */
334 clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */