arch/powerpc/perf/imc-pmu.c

   1 /*
   2  * In-Memory Collection (IMC) Performance Monitor counter support.
   3  *
   4  * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
   5  *           (C) 2017 Anju T Sudhakar, IBM Corporation.
   6  *           (C) 2017 Hemant K Shaw, IBM Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or later version.
  12  */
  13 #include <linux/perf_event.h>
  14 #include <linux/slab.h>
  15 #include <asm/opal.h>
  16 #include <asm/imc-pmu.h>
  17 #include <asm/cputhreads.h>
  18 #include <asm/smp.h>
  19 #include <linux/string.h>
  20
  21 /* Nest IMC data structures and variables */
  22
  23 /*
  24  * Used to avoid races in counting the nest-pmu units during hotplug
  25  * register and unregister
  26  */
  27 static DEFINE_MUTEX(nest_init_lock);
  28 static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
  29 static struct imc_pmu **per_nest_pmu_arr;
  30 static cpumask_t nest_imc_cpumask;
  31 struct imc_pmu_ref *nest_imc_refc;
  32 static int nest_pmus;
  33
  34 /* Core IMC data structures and variables */
  35
  36 static cpumask_t core_imc_cpumask;
  37 struct imc_pmu_ref *core_imc_refc;
  38 static struct imc_pmu *core_imc_pmu;
  39
  40 /* Thread IMC data structures and variables */
  41
  42 static DEFINE_PER_CPU(u64 *, thread_imc_mem);
  43 static struct imc_pmu *thread_imc_pmu;
  44 static int thread_imc_mem_size;
  45
  46 struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
  47 {
  48         return container_of(event->pmu, struct imc_pmu, pmu);
  49 }
  50
  51 PMU_FORMAT_ATTR(event, "config:0-40");
  52 PMU_FORMAT_ATTR(offset, "config:0-31");
  53 PMU_FORMAT_ATTR(rvalue, "config:32");
  54 PMU_FORMAT_ATTR(mode, "config:33-40");
  55 static struct attribute *imc_format_attrs[] = {
  56         &format_attr_event.attr,
  57         &format_attr_offset.attr,
  58         &format_attr_rvalue.attr,
  59         &format_attr_mode.attr,
  60         NULL,
  61 };
  62
  63 static struct attribute_group imc_format_group = {
  64         .name = "format",
  65         .attrs = imc_format_attrs,
  66 };
  67
  68 /* Get the cpumask printed to a buffer "buf" */
  69 static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
  70                                         struct device_attribute *attr,
  71                                         char *buf)
  72 {
  73         struct pmu *pmu = dev_get_drvdata(dev);
  74         struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
  75         cpumask_t *active_mask;
  76
  77         switch(imc_pmu->domain){
  78         case IMC_DOMAIN_NEST:
  79                 active_mask = &nest_imc_cpumask;
  80                 break;
  81         case IMC_DOMAIN_CORE:
  82                 active_mask = &core_imc_cpumask;
  83                 break;
  84         default:
  85                 return 0;
  86         }
  87
  88         return cpumap_print_to_pagebuf(true, buf, active_mask);
  89 }
  90
  91 static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
  92
  93 static struct attribute *imc_pmu_cpumask_attrs[] = {
  94         &dev_attr_cpumask.attr,
  95         NULL,
  96 };
  97
  98 static struct attribute_group imc_pmu_cpumask_attr_group = {
  99         .attrs = imc_pmu_cpumask_attrs,
 100 };
 101
 102 /* device_str_attr_create : Populate event "name" and string "str" in attribute */
 103 static struct attribute *device_str_attr_create(const char *name, const char *str)
 104 {
 105         struct perf_pmu_events_attr *attr;
 106
 107         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
 108         if (!attr)
 109                 return NULL;
 110         sysfs_attr_init(&attr->attr.attr);
 111
 112         attr->event_str = str;
 113         attr->attr.attr.name = name;
 114         attr->attr.attr.mode = 0444;
 115         attr->attr.show = perf_event_sysfs_show;
 116
 117         return &attr->attr.attr;
 118 }
 119
 120 static int imc_parse_event(struct device_node *np, const char *scale,
 121                                   const char *unit, const char *prefix,
 122                                   u32 base, struct imc_events *event)
 123 {
 124         const char *s;
 125         u32 reg;
 126
 127         if (of_property_read_u32(np, "reg", &reg))
 128                 goto error;
 129         /* Add the base_reg value to the "reg" */
 130         event->value = base + reg;
 131
 132         if (of_property_read_string(np, "event-name", &s))
 133                 goto error;
 134
 135         event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
 136         if (!event->name)
 137                 goto error;
 138
 139         if (of_property_read_string(np, "scale", &s))
 140                 s = scale;
 141
 142         if (s) {
 143                 event->scale = kstrdup(s, GFP_KERNEL);
 144                 if (!event->scale)
 145                         goto error;
 146         }
 147
 148         if (of_property_read_string(np, "unit", &s))
 149                 s = unit;
 150
 151         if (s) {
 152                 event->unit = kstrdup(s, GFP_KERNEL);
 153                 if (!event->unit)
 154                         goto error;
 155         }
 156
 157         return 0;
 158 error:
 159         kfree(event->unit);
 160         kfree(event->scale);
 161         kfree(event->name);
 162         return -EINVAL;
 163 }
 164
 165 /*
 166  * imc_free_events: Function to cleanup the events list, having
 167  *                  "nr_entries".
 168  */
 169 static void imc_free_events(struct imc_events *events, int nr_entries)
 170 {
 171         int i;
 172
 173         /* Nothing to clean, return */
 174         if (!events)
 175                 return;
 176         for (i = 0; i < nr_entries; i++) {
 177                 kfree(events[i].unit);
 178                 kfree(events[i].scale);
 179                 kfree(events[i].name);
 180         }
 181
 182         kfree(events);
 183 }
 184
 185 /*
 186  * update_events_in_group: Update the "events" information in an attr_group
 187  *                         and assign the attr_group to the pmu "pmu".
 188  */
 189 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
 190 {
 191         struct attribute_group *attr_group;
 192         struct attribute **attrs, *dev_str;
 193         struct device_node *np, *pmu_events;
 194         u32 handle, base_reg;
 195         int i = 0, j = 0, ct, ret;
 196         const char *prefix, *g_scale, *g_unit;
 197         const char *ev_val_str, *ev_scale_str, *ev_unit_str;
 198
 199         if (!of_property_read_u32(node, "events", &handle))
 200                 pmu_events = of_find_node_by_phandle(handle);
 201         else
 202                 return 0;
 203
 204         /* Did not find any node with a given phandle */
 205         if (!pmu_events)
 206                 return 0;
 207
 208         /* Get a count of number of child nodes */
 209         ct = of_get_child_count(pmu_events);
 210
 211         /* Get the event prefix */
 212         if (of_property_read_string(node, "events-prefix", &prefix))
 213                 return 0;
 214
 215         /* Get a global unit and scale data if available */
 216         if (of_property_read_string(node, "scale", &g_scale))
 217                 g_scale = NULL;
 218
 219         if (of_property_read_string(node, "unit", &g_unit))
 220                 g_unit = NULL;
 221
 222         /* "reg" property gives out the base offset of the counters data */
 223         of_property_read_u32(node, "reg", &base_reg);
 224
 225         /* Allocate memory for the events */
 226         pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
 227         if (!pmu->events)
 228                 return -ENOMEM;
 229
 230         ct = 0;
 231         /* Parse the events and update the struct */
 232         for_each_child_of_node(pmu_events, np) {
 233                 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
 234                 if (!ret)
 235                         ct++;
 236         }
 237
 238         /* Allocate memory for attribute group */
 239         attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
 240         if (!attr_group) {
 241                 imc_free_events(pmu->events, ct);
 242                 return -ENOMEM;
 243         }
 244
 245         /*
 246          * Allocate memory for attributes.
 247          * Since we have count of events for this pmu, we also allocate
 248          * memory for the scale and unit attribute for now.
 249          * "ct" has the total event structs added from the events-parent node.
 250          * So allocate three times the "ct" (this includes event, event_scale and
 251          * event_unit).
 252          */
 253         attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
 254         if (!attrs) {
 255                 kfree(attr_group);
 256                 imc_free_events(pmu->events, ct);
 257                 return -ENOMEM;
 258         }
 259
 260         attr_group->name = "events";
 261         attr_group->attrs = attrs;
 262         do {
 263                 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
 264                 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
 265                 if (!dev_str)
 266                         continue;
 267
 268                 attrs[j++] = dev_str;
 269                 if (pmu->events[i].scale) {
 270                         ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
 271                         dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
 272                         if (!dev_str)
 273                                 continue;
 274
 275                         attrs[j++] = dev_str;
 276                 }
 277
 278                 if (pmu->events[i].unit) {
 279                         ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
 280                         dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
 281                         if (!dev_str)
 282                                 continue;
 283
 284                         attrs[j++] = dev_str;
 285                 }
 286         } while (++i < ct);
 287
 288         /* Save the event attribute */
 289         pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
 290
 291         return 0;
 292 }
 293
 294 /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
 295 static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
 296 {
 297         return per_cpu(local_nest_imc_refc, cpu);
 298 }
 299
 300 static void nest_change_cpu_context(int old_cpu, int new_cpu)
 301 {
 302         struct imc_pmu **pn = per_nest_pmu_arr;
 303
 304         if (old_cpu < 0 || new_cpu < 0)
 305                 return;
 306
 307         while (*pn) {
 308                 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
 309                 pn++;
 310         }
 311 }
 312
 313 static int ppc_nest_imc_cpu_offline(unsigned int cpu)
 314 {
 315         int nid, target = -1;
 316         const struct cpumask *l_cpumask;
 317         struct imc_pmu_ref *ref;
 318
 319         /*
 320          * Check in the designated list for this cpu. Dont bother
 321          * if not one of them.
 322          */
 323         if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
 324                 return 0;
 325
 326         /*
 327          * Check whether nest_imc is registered. We could end up here if the
 328          * cpuhotplug callback registration fails. i.e, callback invokes the
 329          * offline path for all successfully registered nodes. At this stage,
 330          * nest_imc pmu will not be registered and we should return here.
 331          *
 332          * We return with a zero since this is not an offline failure. And
 333          * cpuhp_setup_state() returns the actual failure reason to the caller,
 334          * which in turn will call the cleanup routine.
 335          */
 336         if (!nest_pmus)
 337                 return 0;
 338
 339         /*
 340          * Now that this cpu is one of the designated,
 341          * find a next cpu a) which is online and b) in same chip.
 342          */
 343         nid = cpu_to_node(cpu);
 344         l_cpumask = cpumask_of_node(nid);
 345         target = cpumask_any_but(l_cpumask, cpu);
 346
 347         /*
 348          * Update the cpumask with the target cpu and
 349          * migrate the context if needed
 350          */
 351         if (target >= 0 && target < nr_cpu_ids) {
 352                 cpumask_set_cpu(target, &nest_imc_cpumask);
 353                 nest_change_cpu_context(cpu, target);
 354         } else {
 355                 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
 356                                        get_hard_smp_processor_id(cpu));
 357                 /*
 358                  * If this is the last cpu in this chip then, skip the reference
 359                  * count mutex lock and make the reference count on this chip zero.
 360                  */
 361                 ref = get_nest_pmu_ref(cpu);
 362                 if (!ref)
 363                         return -EINVAL;
 364
 365                 ref->refc = 0;
 366         }
 367         return 0;
 368 }
 369
 370 static int ppc_nest_imc_cpu_online(unsigned int cpu)
 371 {
 372         const struct cpumask *l_cpumask;
 373         static struct cpumask tmp_mask;
 374         int res;
 375
 376         /* Get the cpumask of this node */
 377         l_cpumask = cpumask_of_node(cpu_to_node(cpu));
 378
 379         /*
 380          * If this is not the first online CPU on this node, then
 381          * just return.
 382          */
 383         if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
 384                 return 0;
 385
 386         /*
 387          * If this is the first online cpu on this node
 388          * disable the nest counters by making an OPAL call.
 389          */
 390         res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
 391                                      get_hard_smp_processor_id(cpu));
 392         if (res)
 393                 return res;
 394
 395         /* Make this CPU the designated target for counter collection */
 396         cpumask_set_cpu(cpu, &nest_imc_cpumask);
 397         return 0;
 398 }
 399
 400 static int nest_pmu_cpumask_init(void)
 401 {
 402         return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
 403                                  "perf/powerpc/imc:online",
 404                                  ppc_nest_imc_cpu_online,
 405                                  ppc_nest_imc_cpu_offline);
 406 }
 407
 408 static void nest_imc_counters_release(struct perf_event *event)
 409 {
 410         int rc, node_id;
 411         struct imc_pmu_ref *ref;
 412
 413         if (event->cpu < 0)
 414                 return;
 415
 416         node_id = cpu_to_node(event->cpu);
 417
 418         /*
 419          * See if we need to disable the nest PMU.
 420          * If no events are currently in use, then we have to take a
 421          * mutex to ensure that we don't race with another task doing
 422          * enable or disable the nest counters.
 423          */
 424         ref = get_nest_pmu_ref(event->cpu);
 425         if (!ref)
 426                 return;
 427
 428         /* Take the mutex lock for this node and then decrement the reference count */
 429         mutex_lock(&ref->lock);
 430         if (ref->refc == 0) {
 431                 /*
 432                  * The scenario where this is true is, when perf session is
 433                  * started, followed by offlining of all cpus in a given node.
 434                  *
 435                  * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
 436                  * function set the ref->count to zero, if the cpu which is
 437                  * about to offline is the last cpu in a given node and make
 438                  * an OPAL call to disable the engine in that node.
 439                  *
 440                  */
 441                 mutex_unlock(&ref->lock);
 442                 return;
 443         }
 444         ref->refc--;
 445         if (ref->refc == 0) {
 446                 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
 447                                             get_hard_smp_processor_id(event->cpu));
 448                 if (rc) {
 449                         mutex_unlock(&ref->lock);
 450                         pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
 451                         return;
 452                 }
 453         } else if (ref->refc < 0) {
 454                 WARN(1, "nest-imc: Invalid event reference count\n");
 455                 ref->refc = 0;
 456         }
 457         mutex_unlock(&ref->lock);
 458 }
 459
 460 static int nest_imc_event_init(struct perf_event *event)
 461 {
 462         int chip_id, rc, node_id;
 463         u32 l_config, config = event->attr.config;
 464         struct imc_mem_info *pcni;
 465         struct imc_pmu *pmu;
 466         struct imc_pmu_ref *ref;
 467         bool flag = false;
 468
 469         if (event->attr.type != event->pmu->type)
 470                 return -ENOENT;
 471
 472         /* Sampling not supported */
 473         if (event->hw.sample_period)
 474                 return -EINVAL;
 475
 476         /* unsupported modes and filters */
 477         if (event->attr.exclude_user   ||
 478             event->attr.exclude_kernel ||
 479             event->attr.exclude_hv     ||
 480             event->attr.exclude_idle   ||
 481             event->attr.exclude_host   ||
 482             event->attr.exclude_guest)
 483                 return -EINVAL;
 484
 485         if (event->cpu < 0)
 486                 return -EINVAL;
 487
 488         pmu = imc_event_to_pmu(event);
 489
 490         /* Sanity check for config (event offset) */
 491         if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
 492                 return -EINVAL;
 493
 494         /*
 495          * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
 496          * Get the base memory addresss for this cpu.
 497          */
 498         chip_id = cpu_to_chip_id(event->cpu);
 499
 500         /* Return, if chip_id is not valid */
 501         if (chip_id < 0)
 502                 return -ENODEV;
 503
 504         pcni = pmu->mem_info;
 505         do {
 506                 if (pcni->id == chip_id) {
 507                         flag = true;
 508                         break;
 509                 }
 510                 pcni++;
 511         } while (pcni->vbase != 0);
 512
 513         if (!flag)
 514                 return -ENODEV;
 515
 516         /*
 517          * Add the event offset to the base address.
 518          */
 519         l_config = config & IMC_EVENT_OFFSET_MASK;
 520         event->hw.event_base = (u64)pcni->vbase + l_config;
 521         node_id = cpu_to_node(event->cpu);
 522
 523         /*
 524          * Get the imc_pmu_ref struct for this node.
 525          * Take the mutex lock and then increment the count of nest pmu events
 526          * inited.
 527          */
 528         ref = get_nest_pmu_ref(event->cpu);
 529         if (!ref)
 530                 return -EINVAL;
 531
 532         mutex_lock(&ref->lock);
 533         if (ref->refc == 0) {
 534                 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
 535                                              get_hard_smp_processor_id(event->cpu));
 536                 if (rc) {
 537                         mutex_unlock(&ref->lock);
 538                         pr_err("nest-imc: Unable to start the counters for node %d\n",
 539                                                                         node_id);
 540                         return rc;
 541                 }
 542         }
 543         ++ref->refc;
 544         mutex_unlock(&ref->lock);
 545
 546         event->destroy = nest_imc_counters_release;
 547         return 0;
 548 }
 549
 550 /*
 551  * core_imc_mem_init : Initializes memory for the current core.
 552  *
 553  * Uses alloc_pages_node() and uses the returned address as an argument to
 554  * an opal call to configure the pdbar. The address sent as an argument is
 555  * converted to physical address before the opal call is made. This is the
 556  * base address at which the core imc counters are populated.
 557  */
 558 static int core_imc_mem_init(int cpu, int size)
 559 {
 560         int nid, rc = 0, core_id = (cpu / threads_per_core);
 561         struct imc_mem_info *mem_info;
 562
 563         /*
 564          * alloc_pages_node() will allocate memory for core in the
 565          * local node only.
 566          */
 567         nid = cpu_to_node(cpu);
 568         mem_info = &core_imc_pmu->mem_info[core_id];
 569         mem_info->id = core_id;
 570
 571         /* We need only vbase for core counters */
 572         mem_info->vbase = page_address(alloc_pages_node(nid,
 573                                           GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
 574                                           __GFP_NOWARN, get_order(size)));
 575         if (!mem_info->vbase)
 576                 return -ENOMEM;
 577
 578         /* Init the mutex */
 579         core_imc_refc[core_id].id = core_id;
 580         mutex_init(&core_imc_refc[core_id].lock);
 581
 582         rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
 583                                 __pa((void *)mem_info->vbase),
 584                                 get_hard_smp_processor_id(cpu));
 585         if (rc) {
 586                 free_pages((u64)mem_info->vbase, get_order(size));
 587                 mem_info->vbase = NULL;
 588         }
 589
 590         return rc;
 591 }
 592
 593 static bool is_core_imc_mem_inited(int cpu)
 594 {
 595         struct imc_mem_info *mem_info;
 596         int core_id = (cpu / threads_per_core);
 597
 598         mem_info = &core_imc_pmu->mem_info[core_id];
 599         if (!mem_info->vbase)
 600                 return false;
 601
 602         return true;
 603 }
 604
 605 static int ppc_core_imc_cpu_online(unsigned int cpu)
 606 {
 607         const struct cpumask *l_cpumask;
 608         static struct cpumask tmp_mask;
 609         int ret = 0;
 610
 611         /* Get the cpumask for this core */
 612         l_cpumask = cpu_sibling_mask(cpu);
 613
 614         /* If a cpu for this core is already set, then, don't do anything */
 615         if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
 616                 return 0;
 617
 618         if (!is_core_imc_mem_inited(cpu)) {
 619                 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
 620                 if (ret) {
 621                         pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
 622                         return ret;
 623                 }
 624         }
 625
 626         /* set the cpu in the mask */
 627         cpumask_set_cpu(cpu, &core_imc_cpumask);
 628         return 0;
 629 }
 630
 631 static int ppc_core_imc_cpu_offline(unsigned int cpu)
 632 {
 633         unsigned int core_id;
 634         int ncpu;
 635         struct imc_pmu_ref *ref;
 636
 637         /*
 638          * clear this cpu out of the mask, if not present in the mask,
 639          * don't bother doing anything.
 640          */
 641         if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
 642                 return 0;
 643
 644         /*
 645          * Check whether core_imc is registered. We could end up here
 646          * if the cpuhotplug callback registration fails. i.e, callback
 647          * invokes the offline path for all sucessfully registered cpus.
 648          * At this stage, core_imc pmu will not be registered and we
 649          * should return here.
 650          *
 651          * We return with a zero since this is not an offline failure.
 652          * And cpuhp_setup_state() returns the actual failure reason
 653          * to the caller, which inturn will call the cleanup routine.
 654          */
 655         if (!core_imc_pmu->pmu.event_init)
 656                 return 0;
 657
 658         /* Find any online cpu in that core except the current "cpu" */
 659         ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
 660
 661         if (ncpu >= 0 && ncpu < nr_cpu_ids) {
 662                 cpumask_set_cpu(ncpu, &core_imc_cpumask);
 663                 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
 664         } else {
 665                 /*
 666                  * If this is the last cpu in this core then, skip taking refernce
 667                  * count mutex lock for this core and directly zero "refc" for
 668                  * this core.
 669                  */
 670                 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
 671                                        get_hard_smp_processor_id(cpu));
 672                 core_id = cpu / threads_per_core;
 673                 ref = &core_imc_refc[core_id];
 674                 if (!ref)
 675                         return -EINVAL;
 676
 677                 ref->refc = 0;
 678         }
 679         return 0;
 680 }
 681
 682 static int core_imc_pmu_cpumask_init(void)
 683 {
 684         return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
 685                                  "perf/powerpc/imc_core:online",
 686                                  ppc_core_imc_cpu_online,
 687                                  ppc_core_imc_cpu_offline);
 688 }
 689
 690 static void core_imc_counters_release(struct perf_event *event)
 691 {
 692         int rc, core_id;
 693         struct imc_pmu_ref *ref;
 694
 695         if (event->cpu < 0)
 696                 return;
 697         /*
 698          * See if we need to disable the IMC PMU.
 699          * If no events are currently in use, then we have to take a
 700          * mutex to ensure that we don't race with another task doing
 701          * enable or disable the core counters.
 702          */
 703         core_id = event->cpu / threads_per_core;
 704
 705         /* Take the mutex lock and decrement the refernce count for this core */
 706         ref = &core_imc_refc[core_id];
 707         if (!ref)
 708                 return;
 709
 710         mutex_lock(&ref->lock);
 711         if (ref->refc == 0) {
 712                 /*
 713                  * The scenario where this is true is, when perf session is
 714                  * started, followed by offlining of all cpus in a given core.
 715                  *
 716                  * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
 717                  * function set the ref->count to zero, if the cpu which is
 718                  * about to offline is the last cpu in a given core and make
 719                  * an OPAL call to disable the engine in that core.
 720                  *
 721                  */
 722                 mutex_unlock(&ref->lock);
 723                 return;
 724         }
 725         ref->refc--;
 726         if (ref->refc == 0) {
 727                 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
 728                                             get_hard_smp_processor_id(event->cpu));
 729                 if (rc) {
 730                         mutex_unlock(&ref->lock);
 731                         pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
 732                         return;
 733                 }
 734         } else if (ref->refc < 0) {
 735                 WARN(1, "core-imc: Invalid event reference count\n");
 736                 ref->refc = 0;
 737         }
 738         mutex_unlock(&ref->lock);
 739 }
 740
 741 static int core_imc_event_init(struct perf_event *event)
 742 {
 743         int core_id, rc;
 744         u64 config = event->attr.config;
 745         struct imc_mem_info *pcmi;
 746         struct imc_pmu *pmu;
 747         struct imc_pmu_ref *ref;
 748
 749         if (event->attr.type != event->pmu->type)
 750                 return -ENOENT;
 751
 752         /* Sampling not supported */
 753         if (event->hw.sample_period)
 754                 return -EINVAL;
 755
 756         /* unsupported modes and filters */
 757         if (event->attr.exclude_user   ||
 758             event->attr.exclude_kernel ||
 759             event->attr.exclude_hv     ||
 760             event->attr.exclude_idle   ||
 761             event->attr.exclude_host   ||
 762             event->attr.exclude_guest)
 763                 return -EINVAL;
 764
 765         if (event->cpu < 0)
 766                 return -EINVAL;
 767
 768         event->hw.idx = -1;
 769         pmu = imc_event_to_pmu(event);
 770
 771         /* Sanity check for config (event offset) */
 772         if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
 773                 return -EINVAL;
 774
 775         if (!is_core_imc_mem_inited(event->cpu))
 776                 return -ENODEV;
 777
 778         core_id = event->cpu / threads_per_core;
 779         pcmi = &core_imc_pmu->mem_info[core_id];
 780         if ((!pcmi->vbase))
 781                 return -ENODEV;
 782
 783         /* Get the core_imc mutex for this core */
 784         ref = &core_imc_refc[core_id];
 785         if (!ref)
 786                 return -EINVAL;
 787
 788         /*
 789          * Core pmu units are enabled only when it is used.
 790          * See if this is triggered for the first time.
 791          * If yes, take the mutex lock and enable the core counters.
 792          * If not, just increment the count in core_imc_refc struct.
 793          */
 794         mutex_lock(&ref->lock);
 795         if (ref->refc == 0) {
 796                 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
 797                                              get_hard_smp_processor_id(event->cpu));
 798                 if (rc) {
 799                         mutex_unlock(&ref->lock);
 800                         pr_err("core-imc: Unable to start the counters for core %d\n",
 801                                                                         core_id);
 802                         return rc;
 803                 }
 804         }
 805         ++ref->refc;
 806         mutex_unlock(&ref->lock);
 807
 808         event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
 809         event->destroy = core_imc_counters_release;
 810         return 0;
 811 }
 812
 813 /*
 814  * Allocates a page of memory for each of the online cpus, and write the
 815  * physical base address of that page to the LDBAR for that cpu.
 816  *
 817  * LDBAR Register Layout:
 818  *
 819  *  0          4         8         12        16        20        24        28
 820  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
 821  *   | |       [   ]    [                   Counter Address [8:50]
 822  *   | * Mode    |
 823  *   |           * PB Scope
 824  *   * Enable/Disable
 825  *
 826  *  32        36        40        44        48        52        56        60
 827  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
 828  *           Counter Address [8:50]              ]
 829  *
 830  */
 831 static int thread_imc_mem_alloc(int cpu_id, int size)
 832 {
 833         u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, cpu_id);
 834         int nid = cpu_to_node(cpu_id);
 835
 836         if (!local_mem) {
 837                 /*
 838                  * This case could happen only once at start, since we dont
 839                  * free the memory in cpu offline path.
 840                  */
 841                 local_mem = page_address(alloc_pages_node(nid,
 842                                   GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
 843                                   __GFP_NOWARN, get_order(size)));
 844                 if (!local_mem)
 845                         return -ENOMEM;
 846
 847                 per_cpu(thread_imc_mem, cpu_id) = local_mem;
 848         }
 849
 850         ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
 851
 852         mtspr(SPRN_LDBAR, ldbar_value);
 853         return 0;
 854 }
 855
 856 static int ppc_thread_imc_cpu_online(unsigned int cpu)
 857 {
 858         return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
 859 }
 860
 861 static int ppc_thread_imc_cpu_offline(unsigned int cpu)
 862 {
 863         mtspr(SPRN_LDBAR, 0);
 864         return 0;
 865 }
 866
 867 static int thread_imc_cpu_init(void)
 868 {
 869         return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
 870                           "perf/powerpc/imc_thread:online",
 871                           ppc_thread_imc_cpu_online,
 872                           ppc_thread_imc_cpu_offline);
 873 }
 874
 875 static int thread_imc_event_init(struct perf_event *event)
 876 {
 877         u32 config = event->attr.config;
 878         struct task_struct *target;
 879         struct imc_pmu *pmu;
 880
 881         if (event->attr.type != event->pmu->type)
 882                 return -ENOENT;
 883
 884         /* Sampling not supported */
 885         if (event->hw.sample_period)
 886                 return -EINVAL;
 887
 888         event->hw.idx = -1;
 889         pmu = imc_event_to_pmu(event);
 890
 891         /* Sanity check for config offset */
 892         if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
 893                 return -EINVAL;
 894
 895         target = event->hw.target;
 896         if (!target)
 897                 return -EINVAL;
 898
 899         event->pmu->task_ctx_nr = perf_sw_context;
 900         return 0;
 901 }
 902
 903 static bool is_thread_imc_pmu(struct perf_event *event)
 904 {
 905         if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
 906                 return true;
 907
 908         return false;
 909 }
 910
 911 static u64 * get_event_base_addr(struct perf_event *event)
 912 {
 913         u64 addr;
 914
 915         if (is_thread_imc_pmu(event)) {
 916                 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
 917                 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
 918         }
 919
 920         return (u64 *)event->hw.event_base;
 921 }
 922
 923 static void thread_imc_pmu_start_txn(struct pmu *pmu,
 924                                      unsigned int txn_flags)
 925 {
 926         if (txn_flags & ~PERF_PMU_TXN_ADD)
 927                 return;
 928         perf_pmu_disable(pmu);
 929 }
 930
 931 static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
 932 {
 933         perf_pmu_enable(pmu);
 934 }
 935
 936 static int thread_imc_pmu_commit_txn(struct pmu *pmu)
 937 {
 938         perf_pmu_enable(pmu);
 939         return 0;
 940 }
 941
 942 static u64 imc_read_counter(struct perf_event *event)
 943 {
 944         u64 *addr, data;
 945
 946         /*
 947          * In-Memory Collection (IMC) counters are free flowing counters.
 948          * So we take a snapshot of the counter value on enable and save it
 949          * to calculate the delta at later stage to present the event counter
 950          * value.
 951          */
 952         addr = get_event_base_addr(event);
 953         data = be64_to_cpu(READ_ONCE(*addr));
 954         local64_set(&event->hw.prev_count, data);
 955
 956         return data;
 957 }
 958
 959 static void imc_event_update(struct perf_event *event)
 960 {
 961         u64 counter_prev, counter_new, final_count;
 962
 963         counter_prev = local64_read(&event->hw.prev_count);
 964         counter_new = imc_read_counter(event);
 965         final_count = counter_new - counter_prev;
 966
 967         /* Update the delta to the event count */
 968         local64_add(final_count, &event->count);
 969 }
 970
 971 static void imc_event_start(struct perf_event *event, int flags)
 972 {
 973         /*
 974          * In Memory Counters are free flowing counters. HW or the microcode
 975          * keeps adding to the counter offset in memory. To get event
 976          * counter value, we snapshot the value here and we calculate
 977          * delta at later point.
 978          */
 979         imc_read_counter(event);
 980 }
 981
 982 static void imc_event_stop(struct perf_event *event, int flags)
 983 {
 984         /*
 985          * Take a snapshot and calculate the delta and update
 986          * the event counter values.
 987          */
 988         imc_event_update(event);
 989 }
 990
 991 static int imc_event_add(struct perf_event *event, int flags)
 992 {
 993         if (flags & PERF_EF_START)
 994                 imc_event_start(event, flags);
 995
 996         return 0;
 997 }
 998
 999 static int thread_imc_event_add(struct perf_event *event, int flags)
1000 {
1001         int core_id;
1002         struct imc_pmu_ref *ref;
1003
1004         if (flags & PERF_EF_START)
1005                 imc_event_start(event, flags);
1006
1007         if (!is_core_imc_mem_inited(smp_processor_id()))
1008                 return -EINVAL;
1009
1010         core_id = smp_processor_id() / threads_per_core;
1011         /*
1012          * imc pmus are enabled only when it is used.
1013          * See if this is triggered for the first time.
1014          * If yes, take the mutex lock and enable the counters.
1015          * If not, just increment the count in ref count struct.
1016          */
1017         ref = &core_imc_refc[core_id];
1018         if (!ref)
1019                 return -EINVAL;
1020
1021         mutex_lock(&ref->lock);
1022         if (ref->refc == 0) {
1023                 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1024                     get_hard_smp_processor_id(smp_processor_id()))) {
1025                         mutex_unlock(&ref->lock);
1026                         pr_err("thread-imc: Unable to start the counter\
1027                                 for core %d\n", core_id);
1028                         return -EINVAL;
1029                 }
1030         }
1031         ++ref->refc;
1032         mutex_unlock(&ref->lock);
1033         return 0;
1034 }
1035
1036 static void thread_imc_event_del(struct perf_event *event, int flags)
1037 {
1038
1039         int core_id;
1040         struct imc_pmu_ref *ref;
1041
1042         /*
1043          * Take a snapshot and calculate the delta and update
1044          * the event counter values.
1045          */
1046         imc_event_update(event);
1047
1048         core_id = smp_processor_id() / threads_per_core;
1049         ref = &core_imc_refc[core_id];
1050
1051         mutex_lock(&ref->lock);
1052         ref->refc--;
1053         if (ref->refc == 0) {
1054                 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1055                     get_hard_smp_processor_id(smp_processor_id()))) {
1056                         mutex_unlock(&ref->lock);
1057                         pr_err("thread-imc: Unable to stop the counters\
1058                                 for core %d\n", core_id);
1059                         return;
1060                 }
1061         } else if (ref->refc < 0) {
1062                 ref->refc = 0;
1063         }
1064         mutex_unlock(&ref->lock);
1065 }
1066
1067 /* update_pmu_ops : Populate the appropriate operations for "pmu" */
1068 static int update_pmu_ops(struct imc_pmu *pmu)
1069 {
1070         pmu->pmu.task_ctx_nr = perf_invalid_context;
1071         pmu->pmu.add = imc_event_add;
1072         pmu->pmu.del = imc_event_stop;
1073         pmu->pmu.start = imc_event_start;
1074         pmu->pmu.stop = imc_event_stop;
1075         pmu->pmu.read = imc_event_update;
1076         pmu->pmu.attr_groups = pmu->attr_groups;
1077         pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1078
1079         switch (pmu->domain) {
1080         case IMC_DOMAIN_NEST:
1081                 pmu->pmu.event_init = nest_imc_event_init;
1082                 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1083                 break;
1084         case IMC_DOMAIN_CORE:
1085                 pmu->pmu.event_init = core_imc_event_init;
1086                 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1087                 break;
1088         case IMC_DOMAIN_THREAD:
1089                 pmu->pmu.event_init = thread_imc_event_init;
1090                 pmu->pmu.add = thread_imc_event_add;
1091                 pmu->pmu.del = thread_imc_event_del;
1092                 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1093                 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1094                 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1095                 break;
1096         default:
1097                 break;
1098         }
1099
1100         return 0;
1101 }
1102
1103 /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1104 static int init_nest_pmu_ref(void)
1105 {
1106         int nid, i, cpu;
1107
1108         nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1109                                                                 GFP_KERNEL);
1110
1111         if (!nest_imc_refc)
1112                 return -ENOMEM;
1113
1114         i = 0;
1115         for_each_node(nid) {
1116                 /*
1117                  * Mutex lock to avoid races while tracking the number of
1118                  * sessions using the chip's nest pmu units.
1119                  */
1120                 mutex_init(&nest_imc_refc[i].lock);
1121
1122                 /*
1123                  * Loop to init the "id" with the node_id. Variable "i" initialized to
1124                  * 0 and will be used as index to the array. "i" will not go off the
1125                  * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1126                  * nodes only.
1127                  */
1128                 nest_imc_refc[i++].id = nid;
1129         }
1130
1131         /*
1132          * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1133          * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1134          */
1135         for_each_possible_cpu(cpu) {
1136                 nid = cpu_to_node(cpu);
1137                 for (i = 0; i < num_possible_nodes(); i++) {
1138                         if (nest_imc_refc[i].id == nid) {
1139                                 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1140                                 break;
1141                         }
1142                 }
1143         }
1144         return 0;
1145 }
1146
1147 static void cleanup_all_core_imc_memory(void)
1148 {
1149         int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1150         struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1151         int size = core_imc_pmu->counter_mem_size;
1152
1153         /* mem_info will never be NULL */
1154         for (i = 0; i < nr_cores; i++) {
1155                 if (ptr[i].vbase)
1156                         free_pages((u64)ptr[i].vbase, get_order(size));
1157         }
1158
1159         kfree(ptr);
1160         kfree(core_imc_refc);
1161 }
1162
1163 static void thread_imc_ldbar_disable(void *dummy)
1164 {
1165         /*
1166          * By Zeroing LDBAR, we disable thread-imc
1167          * updates.
1168          */
1169         mtspr(SPRN_LDBAR, 0);
1170 }
1171
1172 void thread_imc_disable(void)
1173 {
1174         on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1175 }
1176
1177 static void cleanup_all_thread_imc_memory(void)
1178 {
1179         int i, order = get_order(thread_imc_mem_size);
1180
1181         for_each_online_cpu(i) {
1182                 if (per_cpu(thread_imc_mem, i))
1183                         free_pages((u64)per_cpu(thread_imc_mem, i), order);
1184
1185         }
1186 }
1187
1188 /* Function to free the attr_groups which are dynamically allocated */
1189 static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1190 {
1191         if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1192                 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1193         kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1194 }
1195
1196 /*
1197  * Common function to unregister cpu hotplug callback and
1198  * free the memory.
1199  * TODO: Need to handle pmu unregistering, which will be
1200  * done in followup series.
1201  */
1202 static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1203 {
1204         if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1205                 mutex_lock(&nest_init_lock);
1206                 if (nest_pmus == 1) {
1207                         cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1208                         kfree(nest_imc_refc);
1209                         kfree(per_nest_pmu_arr);
1210                         per_nest_pmu_arr = NULL;
1211                 }
1212
1213                 if (nest_pmus > 0)
1214                         nest_pmus--;
1215                 mutex_unlock(&nest_init_lock);
1216         }
1217
1218         /* Free core_imc memory */
1219         if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1220                 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1221                 cleanup_all_core_imc_memory();
1222         }
1223
1224         /* Free thread_imc memory */
1225         if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1226                 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1227                 cleanup_all_thread_imc_memory();
1228         }
1229 }
1230
1231 /*
1232  * Function to unregister thread-imc if core-imc
1233  * is not registered.
1234  */
1235 void unregister_thread_imc(void)
1236 {
1237         imc_common_cpuhp_mem_free(thread_imc_pmu);
1238         imc_common_mem_free(thread_imc_pmu);
1239         perf_pmu_unregister(&thread_imc_pmu->pmu);
1240 }
1241
1242 /*
1243  * imc_mem_init : Function to support memory allocation for core imc.
1244  */
1245 static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1246                                                                 int pmu_index)
1247 {
1248         const char *s;
1249         int nr_cores, cpu, res = -ENOMEM;
1250
1251         if (of_property_read_string(parent, "name", &s))
1252                 return -ENODEV;
1253
1254         switch (pmu_ptr->domain) {
1255         case IMC_DOMAIN_NEST:
1256                 /* Update the pmu name */
1257                 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1258                 if (!pmu_ptr->pmu.name)
1259                         goto err;
1260
1261                 /* Needed for hotplug/migration */
1262                 if (!per_nest_pmu_arr) {
1263                         per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1264                                                 sizeof(struct imc_pmu *),
1265                                                 GFP_KERNEL);
1266                         if (!per_nest_pmu_arr)
1267                                 goto err;
1268                 }
1269                 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1270                 break;
1271         case IMC_DOMAIN_CORE:
1272                 /* Update the pmu name */
1273                 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1274                 if (!pmu_ptr->pmu.name)
1275                         goto err;
1276
1277                 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1278                 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1279                                                                 GFP_KERNEL);
1280
1281                 if (!pmu_ptr->mem_info)
1282                         goto err;
1283
1284                 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1285                                                                 GFP_KERNEL);
1286
1287                 if (!core_imc_refc) {
1288                         kfree(pmu_ptr->mem_info);
1289                         goto err;
1290                 }
1291
1292                 core_imc_pmu = pmu_ptr;
1293                 break;
1294         case IMC_DOMAIN_THREAD:
1295                 /* Update the pmu name */
1296                 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1297                 if (!pmu_ptr->pmu.name)
1298                         goto err;
1299
1300                 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1301                 for_each_online_cpu(cpu) {
1302                         res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1303                         if (res) {
1304                                 cleanup_all_thread_imc_memory();
1305                                 goto err;
1306                         }
1307                 }
1308
1309                 thread_imc_pmu = pmu_ptr;
1310                 break;
1311         default:
1312                 return -EINVAL;
1313         }
1314
1315         return 0;
1316 err:
1317         return res;
1318 }
1319
1320 /*
1321  * init_imc_pmu : Setup and register the IMC pmu device.
1322  *
1323  * @parent:     Device tree unit node
1324  * @pmu_ptr:    memory allocated for this pmu
1325  * @pmu_idx:    Count of nest pmc registered
1326  *
1327  * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1328  * Handles failure cases and accordingly frees memory.
1329  */
1330 int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1331 {
1332         int ret;
1333
1334         ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1335         if (ret)
1336                 goto err_free_mem;
1337
1338         switch (pmu_ptr->domain) {
1339         case IMC_DOMAIN_NEST:
1340                 /*
1341                 * Nest imc pmu need only one cpu per chip, we initialize the
1342                 * cpumask for the first nest imc pmu and use the same for the
1343                 * rest. To handle the cpuhotplug callback unregister, we track
1344                 * the number of nest pmus in "nest_pmus".
1345                 */
1346                 mutex_lock(&nest_init_lock);
1347                 if (nest_pmus == 0) {
1348                         ret = init_nest_pmu_ref();
1349                         if (ret) {
1350                                 mutex_unlock(&nest_init_lock);
1351                                 kfree(per_nest_pmu_arr);
1352                                 per_nest_pmu_arr = NULL;
1353                                 goto err_free_mem;
1354                         }
1355                         /* Register for cpu hotplug notification. */
1356                         ret = nest_pmu_cpumask_init();
1357                         if (ret) {
1358                                 mutex_unlock(&nest_init_lock);
1359                                 kfree(nest_imc_refc);
1360                                 kfree(per_nest_pmu_arr);
1361                                 per_nest_pmu_arr = NULL;
1362                                 goto err_free_mem;
1363                         }
1364                 }
1365                 nest_pmus++;
1366                 mutex_unlock(&nest_init_lock);
1367                 break;
1368         case IMC_DOMAIN_CORE:
1369                 ret = core_imc_pmu_cpumask_init();
1370                 if (ret) {
1371                         cleanup_all_core_imc_memory();
1372                         goto err_free_mem;
1373                 }
1374
1375                 break;
1376         case IMC_DOMAIN_THREAD:
1377                 ret = thread_imc_cpu_init();
1378                 if (ret) {
1379                         cleanup_all_thread_imc_memory();
1380                         goto err_free_mem;
1381                 }
1382
1383                 break;
1384         default:
1385                 return  -EINVAL;        /* Unknown domain */
1386         }
1387
1388         ret = update_events_in_group(parent, pmu_ptr);
1389         if (ret)
1390                 goto err_free_cpuhp_mem;
1391
1392         ret = update_pmu_ops(pmu_ptr);
1393         if (ret)
1394                 goto err_free_cpuhp_mem;
1395
1396         ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1397         if (ret)
1398                 goto err_free_cpuhp_mem;
1399
1400         pr_info("%s performance monitor hardware support registered\n",
1401                                                         pmu_ptr->pmu.name);
1402
1403         return 0;
1404
1405 err_free_cpuhp_mem:
1406         imc_common_cpuhp_mem_free(pmu_ptr);
1407 err_free_mem:
1408         imc_common_mem_free(pmu_ptr);
1409         return ret;
1410 }