arch/powerpc/platforms/powernv/opal-imc.c

   1 /*
   2  * OPAL IMC interface detection driver
   3  * Supported on POWERNV platform
   4  *
   5  * Copyright    (C) 2017 Madhavan Srinivasan, IBM Corporation.
   6  *              (C) 2017 Anju T Sudhakar, IBM Corporation.
   7  *              (C) 2017 Hemant K Shaw, IBM Corporation.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or later version.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/crash_dump.h>
  20 #include <asm/opal.h>
  21 #include <asm/io.h>
  22 #include <asm/imc-pmu.h>
  23 #include <asm/cputhreads.h>
  24
  25 /*
  26  * imc_get_mem_addr_nest: Function to get nest counter memory region
  27  * for each chip
  28  */
  29 static int imc_get_mem_addr_nest(struct device_node *node,
  30                                  struct imc_pmu *pmu_ptr,
  31                                  u32 offset)
  32 {
  33         int nr_chips = 0, i;
  34         u64 *base_addr_arr, baddr;
  35         u32 *chipid_arr;
  36
  37         nr_chips = of_property_count_u32_elems(node, "chip-id");
  38         if (nr_chips <= 0)
  39                 return -ENODEV;
  40
  41         base_addr_arr = kcalloc(nr_chips, sizeof(u64), GFP_KERNEL);
  42         if (!base_addr_arr)
  43                 return -ENOMEM;
  44
  45         chipid_arr = kcalloc(nr_chips, sizeof(u32), GFP_KERNEL);
  46         if (!chipid_arr)
  47                 return -ENOMEM;
  48
  49         if (of_property_read_u32_array(node, "chip-id", chipid_arr, nr_chips))
  50                 goto error;
  51
  52         if (of_property_read_u64_array(node, "base-addr", base_addr_arr,
  53                                                                 nr_chips))
  54                 goto error;
  55
  56         pmu_ptr->mem_info = kcalloc(nr_chips, sizeof(struct imc_mem_info),
  57                                                                 GFP_KERNEL);
  58         if (!pmu_ptr->mem_info)
  59                 goto error;
  60
  61         for (i = 0; i < nr_chips; i++) {
  62                 pmu_ptr->mem_info[i].id = chipid_arr[i];
  63                 baddr = base_addr_arr[i] + offset;
  64                 pmu_ptr->mem_info[i].vbase = phys_to_virt(baddr);
  65         }
  66
  67         pmu_ptr->imc_counter_mmaped = true;
  68         kfree(base_addr_arr);
  69         kfree(chipid_arr);
  70         return 0;
  71
  72 error:
  73         kfree(pmu_ptr->mem_info);
  74         kfree(base_addr_arr);
  75         kfree(chipid_arr);
  76         return -1;
  77 }
  78
  79 /*
  80  * imc_pmu_create : Takes the parent device which is the pmu unit, pmu_index
  81  *                  and domain as the inputs.
  82  * Allocates memory for the struct imc_pmu, sets up its domain, size and offsets
  83  */
  84 static int imc_pmu_create(struct device_node *parent, int pmu_index, int domain)
  85 {
  86         int ret = 0;
  87         struct imc_pmu *pmu_ptr;
  88         u32 offset;
  89
  90         /* Return for unknown domain */
  91         if (domain < 0)
  92                 return -EINVAL;
  93
  94         /* memory for pmu */
  95         pmu_ptr = kzalloc(sizeof(struct imc_pmu), GFP_KERNEL);
  96         if (!pmu_ptr)
  97                 return -ENOMEM;
  98
  99         /* Set the domain */
 100         pmu_ptr->domain = domain;
 101
 102         ret = of_property_read_u32(parent, "size", &pmu_ptr->counter_mem_size);
 103         if (ret) {
 104                 ret = -EINVAL;
 105                 goto free_pmu;
 106         }
 107
 108         if (!of_property_read_u32(parent, "offset", &offset)) {
 109                 if (imc_get_mem_addr_nest(parent, pmu_ptr, offset)) {
 110                         ret = -EINVAL;
 111                         goto free_pmu;
 112                 }
 113         }
 114
 115         /* Function to register IMC pmu */
 116         ret = init_imc_pmu(parent, pmu_ptr, pmu_index);
 117         if (ret)
 118                 pr_err("IMC PMU %s Register failed\n", pmu_ptr->pmu.name);
 119
 120         return 0;
 121
 122 free_pmu:
 123         kfree(pmu_ptr);
 124         return ret;
 125 }
 126
 127 static void disable_nest_pmu_counters(void)
 128 {
 129         int nid, cpu;
 130         const struct cpumask *l_cpumask;
 131
 132         get_online_cpus();
 133         for_each_node_with_cpus(nid) {
 134                 l_cpumask = cpumask_of_node(nid);
 135                 cpu = cpumask_first_and(l_cpumask, cpu_online_mask);
 136                 if (cpu >= nr_cpu_ids)
 137                         continue;
 138                 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
 139                                        get_hard_smp_processor_id(cpu));
 140         }
 141         put_online_cpus();
 142 }
 143
 144 static void disable_core_pmu_counters(void)
 145 {
 146         cpumask_t cores_map;
 147         int cpu, rc;
 148
 149         get_online_cpus();
 150         /* Disable the IMC Core functions */
 151         cores_map = cpu_online_cores_map();
 152         for_each_cpu(cpu, &cores_map) {
 153                 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
 154                                             get_hard_smp_processor_id(cpu));
 155                 if (rc)
 156                         pr_err("%s: Failed to stop Core (cpu = %d)\n",
 157                                 __FUNCTION__, cpu);
 158         }
 159         put_online_cpus();
 160 }
 161
 162 int get_max_nest_dev(void)
 163 {
 164         struct device_node *node;
 165         u32 pmu_units = 0, type;
 166
 167         for_each_compatible_node(node, NULL, IMC_DTB_UNIT_COMPAT) {
 168                 if (of_property_read_u32(node, "type", &type))
 169                         continue;
 170
 171                 if (type == IMC_TYPE_CHIP)
 172                         pmu_units++;
 173         }
 174
 175         return pmu_units;
 176 }
 177
 178 static int opal_imc_counters_probe(struct platform_device *pdev)
 179 {
 180         struct device_node *imc_dev = pdev->dev.of_node;
 181         int pmu_count = 0, domain;
 182         u32 type;
 183
 184         /*
 185          * Check whether this is kdump kernel. If yes, force the engines to
 186          * stop and return.
 187          */
 188         if (is_kdump_kernel()) {
 189                 disable_nest_pmu_counters();
 190                 disable_core_pmu_counters();
 191                 return -ENODEV;
 192         }
 193
 194         for_each_compatible_node(imc_dev, NULL, IMC_DTB_UNIT_COMPAT) {
 195                 if (of_property_read_u32(imc_dev, "type", &type)) {
 196                         pr_warn("IMC Device without type property\n");
 197                         continue;
 198                 }
 199
 200                 switch (type) {
 201                 case IMC_TYPE_CHIP:
 202                         domain = IMC_DOMAIN_NEST;
 203                         break;
 204                 case IMC_TYPE_CORE:
 205                         domain =IMC_DOMAIN_CORE;
 206                         break;
 207                 case IMC_TYPE_THREAD:
 208                         domain = IMC_DOMAIN_THREAD;
 209                         break;
 210                 default:
 211                         pr_warn("IMC Unknown Device type \n");
 212                         domain = -1;
 213                         break;
 214                 }
 215
 216                 if (!imc_pmu_create(imc_dev, pmu_count, domain)) {
 217                         if (domain == IMC_DOMAIN_NEST)
 218                                 pmu_count++;
 219                 }
 220         }
 221
 222         return 0;
 223 }
 224
 225 static void opal_imc_counters_shutdown(struct platform_device *pdev)
 226 {
 227         /*
 228          * Function only stops the engines which is bare minimum.
 229          * TODO: Need to handle proper memory cleanup and pmu
 230          * unregister.
 231          */
 232         disable_nest_pmu_counters();
 233         disable_core_pmu_counters();
 234 }
 235
 236 static const struct of_device_id opal_imc_match[] = {
 237         { .compatible = IMC_DTB_COMPAT },
 238         {},
 239 };
 240
 241 static struct platform_driver opal_imc_driver = {
 242         .driver = {
 243                 .name = "opal-imc-counters",
 244                 .of_match_table = opal_imc_match,
 245         },
 246         .probe = opal_imc_counters_probe,
 247         .shutdown = opal_imc_counters_shutdown,
 248 };
 249
 250 builtin_platform_driver(opal_imc_driver);