arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  52 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  54
  55 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  56 #define POWERNV_IOMMU_MAX_LEVELS        5
  57
  58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
  59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  60
  61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  62                             const char *fmt, ...)
  63 {
  64         struct va_format vaf;
  65         va_list args;
  66         char pfix[32];
  67
  68         va_start(args, fmt);
  69
  70         vaf.fmt = fmt;
  71         vaf.va = &args;
  72
  73         if (pe->flags & PNV_IODA_PE_DEV)
  74                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  75         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  76                 sprintf(pfix, "%04x:%02x     ",
  77                         pci_domain_nr(pe->pbus), pe->pbus->number);
  78 #ifdef CONFIG_PCI_IOV
  79         else if (pe->flags & PNV_IODA_PE_VF)
  80                 sprintf(pfix, "%04x:%02x:%2x.%d",
  81                         pci_domain_nr(pe->parent_dev->bus),
  82                         (pe->rid & 0xff00) >> 8,
  83                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  84 #endif /* CONFIG_PCI_IOV*/
  85
  86         printk("%spci %s: [PE# %.3d] %pV",
  87                level, pfix, pe->pe_number, &vaf);
  88
  89         va_end(args);
  90 }
  91
  92 static bool pnv_iommu_bypass_disabled __read_mostly;
  93
  94 static int __init iommu_setup(char *str)
  95 {
  96         if (!str)
  97                 return -EINVAL;
  98
  99         while (*str) {
 100                 if (!strncmp(str, "nobypass", 8)) {
 101                         pnv_iommu_bypass_disabled = true;
 102                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 103                         break;
 104                 }
 105                 str += strcspn(str, ",");
 106                 if (*str == ',')
 107                         str++;
 108         }
 109
 110         return 0;
 111 }
 112 early_param("iommu", iommu_setup);
 113
 114 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
 115 {
 116         /*
 117          * WARNING: We cannot rely on the resource flags. The Linux PCI
 118          * allocation code sometimes decides to put a 64-bit prefetchable
 119          * BAR in the 32-bit window, so we have to compare the addresses.
 120          *
 121          * For simplicity we only test resource start.
 122          */
 123         return (r->start >= phb->ioda.m64_base &&
 124                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
 125 }
 126
 127 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
 128 {
 129         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 130
 131         return (resource_flags & flags) == flags;
 132 }
 133
 134 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 135 {
 136         s64 rc;
 137
 138         phb->ioda.pe_array[pe_no].phb = phb;
 139         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 140
 141         /*
 142          * Clear the PE frozen state as it might be put into frozen state
 143          * in the last PCI remove path. It's not harmful to do so when the
 144          * PE is already in unfrozen state.
 145          */
 146         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 147                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 148         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
 149                 pr_warn("%s: Error %lld unfreezing PHB#%d-PE#%d\n",
 150                         __func__, rc, phb->hose->global_number, pe_no);
 151
 152         return &phb->ioda.pe_array[pe_no];
 153 }
 154
 155 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 156 {
 157         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 158                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 159                         __func__, pe_no, phb->hose->global_number);
 160                 return;
 161         }
 162
 163         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 164                 pr_debug("%s: PE %d was reserved on PHB#%x\n",
 165                          __func__, pe_no, phb->hose->global_number);
 166
 167         pnv_ioda_init_pe(phb, pe_no);
 168 }
 169
 170 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 171 {
 172         long pe;
 173
 174         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 175                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 176                         return pnv_ioda_init_pe(phb, pe);
 177         }
 178
 179         return NULL;
 180 }
 181
 182 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 183 {
 184         struct pnv_phb *phb = pe->phb;
 185         unsigned int pe_num = pe->pe_number;
 186
 187         WARN_ON(pe->pdev);
 188
 189         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 190         clear_bit(pe_num, phb->ioda.pe_alloc);
 191 }
 192
 193 /* The default M64 BAR is shared by all PEs */
 194 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 195 {
 196         const char *desc;
 197         struct resource *r;
 198         s64 rc;
 199
 200         /* Configure the default M64 BAR */
 201         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 202                                          OPAL_M64_WINDOW_TYPE,
 203                                          phb->ioda.m64_bar_idx,
 204                                          phb->ioda.m64_base,
 205                                          0, /* unused */
 206                                          phb->ioda.m64_size);
 207         if (rc != OPAL_SUCCESS) {
 208                 desc = "configuring";
 209                 goto fail;
 210         }
 211
 212         /* Enable the default M64 BAR */
 213         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 214                                       OPAL_M64_WINDOW_TYPE,
 215                                       phb->ioda.m64_bar_idx,
 216                                       OPAL_ENABLE_M64_SPLIT);
 217         if (rc != OPAL_SUCCESS) {
 218                 desc = "enabling";
 219                 goto fail;
 220         }
 221
 222         /*
 223          * Exclude the segments for reserved and root bus PE, which
 224          * are first or last two PEs.
 225          */
 226         r = &phb->hose->mem_resources[1];
 227         if (phb->ioda.reserved_pe_idx == 0)
 228                 r->start += (2 * phb->ioda.m64_segsize);
 229         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 230                 r->end -= (2 * phb->ioda.m64_segsize);
 231         else
 232                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 233                         phb->ioda.reserved_pe_idx);
 234
 235         return 0;
 236
 237 fail:
 238         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 239                 rc, desc, phb->ioda.m64_bar_idx);
 240         opal_pci_phb_mmio_enable(phb->opal_id,
 241                                  OPAL_M64_WINDOW_TYPE,
 242                                  phb->ioda.m64_bar_idx,
 243                                  OPAL_DISABLE_M64);
 244         return -EIO;
 245 }
 246
 247 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 248                                          unsigned long *pe_bitmap)
 249 {
 250         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 251         struct pnv_phb *phb = hose->private_data;
 252         struct resource *r;
 253         resource_size_t base, sgsz, start, end;
 254         int segno, i;
 255
 256         base = phb->ioda.m64_base;
 257         sgsz = phb->ioda.m64_segsize;
 258         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 259                 r = &pdev->resource[i];
 260                 if (!r->parent || !pnv_pci_is_m64(phb, r))
 261                         continue;
 262
 263                 start = _ALIGN_DOWN(r->start - base, sgsz);
 264                 end = _ALIGN_UP(r->end - base, sgsz);
 265                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 266                         if (pe_bitmap)
 267                                 set_bit(segno, pe_bitmap);
 268                         else
 269                                 pnv_ioda_reserve_pe(phb, segno);
 270                 }
 271         }
 272 }
 273
 274 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 275 {
 276         struct resource *r;
 277         int index;
 278
 279         /*
 280          * There are 16 M64 BARs, each of which has 8 segments. So
 281          * there are as many M64 segments as the maximum number of
 282          * PEs, which is 128.
 283          */
 284         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 285                 unsigned long base, segsz = phb->ioda.m64_segsize;
 286                 int64_t rc;
 287
 288                 base = phb->ioda.m64_base +
 289                        index * PNV_IODA1_M64_SEGS * segsz;
 290                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 291                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 292                                 PNV_IODA1_M64_SEGS * segsz);
 293                 if (rc != OPAL_SUCCESS) {
 294                         pr_warn("  Error %lld setting M64 PHB#%d-BAR#%d\n",
 295                                 rc, phb->hose->global_number, index);
 296                         goto fail;
 297                 }
 298
 299                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 300                                 OPAL_M64_WINDOW_TYPE, index,
 301                                 OPAL_ENABLE_M64_SPLIT);
 302                 if (rc != OPAL_SUCCESS) {
 303                         pr_warn("  Error %lld enabling M64 PHB#%d-BAR#%d\n",
 304                                 rc, phb->hose->global_number, index);
 305                         goto fail;
 306                 }
 307         }
 308
 309         /*
 310          * Exclude the segments for reserved and root bus PE, which
 311          * are first or last two PEs.
 312          */
 313         r = &phb->hose->mem_resources[1];
 314         if (phb->ioda.reserved_pe_idx == 0)
 315                 r->start += (2 * phb->ioda.m64_segsize);
 316         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 317                 r->end -= (2 * phb->ioda.m64_segsize);
 318         else
 319                 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
 320                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 321
 322         return 0;
 323
 324 fail:
 325         for ( ; index >= 0; index--)
 326                 opal_pci_phb_mmio_enable(phb->opal_id,
 327                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 328
 329         return -EIO;
 330 }
 331
 332 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 333                                     unsigned long *pe_bitmap,
 334                                     bool all)
 335 {
 336         struct pci_dev *pdev;
 337
 338         list_for_each_entry(pdev, &bus->devices, bus_list) {
 339                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 340
 341                 if (all && pdev->subordinate)
 342                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 343                                                 pe_bitmap, all);
 344         }
 345 }
 346
 347 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 348 {
 349         struct pci_controller *hose = pci_bus_to_host(bus);
 350         struct pnv_phb *phb = hose->private_data;
 351         struct pnv_ioda_pe *master_pe, *pe;
 352         unsigned long size, *pe_alloc;
 353         int i;
 354
 355         /* Root bus shouldn't use M64 */
 356         if (pci_is_root_bus(bus))
 357                 return NULL;
 358
 359         /* Allocate bitmap */
 360         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 361         pe_alloc = kzalloc(size, GFP_KERNEL);
 362         if (!pe_alloc) {
 363                 pr_warn("%s: Out of memory !\n",
 364                         __func__);
 365                 return NULL;
 366         }
 367
 368         /* Figure out reserved PE numbers by the PE */
 369         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 370
 371         /*
 372          * the current bus might not own M64 window and that's all
 373          * contributed by its child buses. For the case, we needn't
 374          * pick M64 dependent PE#.
 375          */
 376         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 377                 kfree(pe_alloc);
 378                 return NULL;
 379         }
 380
 381         /*
 382          * Figure out the master PE and put all slave PEs to master
 383          * PE's list to form compound PE.
 384          */
 385         master_pe = NULL;
 386         i = -1;
 387         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 388                 phb->ioda.total_pe_num) {
 389                 pe = &phb->ioda.pe_array[i];
 390
 391                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 392                 if (!master_pe) {
 393                         pe->flags |= PNV_IODA_PE_MASTER;
 394                         INIT_LIST_HEAD(&pe->slaves);
 395                         master_pe = pe;
 396                 } else {
 397                         pe->flags |= PNV_IODA_PE_SLAVE;
 398                         pe->master = master_pe;
 399                         list_add_tail(&pe->list, &master_pe->slaves);
 400                 }
 401
 402                 /*
 403                  * P7IOC supports M64DT, which helps mapping M64 segment
 404                  * to one particular PE#. However, PHB3 has fixed mapping
 405                  * between M64 segment and PE#. In order to have same logic
 406                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 407                  * segment and PE# on P7IOC.
 408                  */
 409                 if (phb->type == PNV_PHB_IODA1) {
 410                         int64_t rc;
 411
 412                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 413                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 414                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 415                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 416                         if (rc != OPAL_SUCCESS)
 417                                 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
 418                                         __func__, rc, phb->hose->global_number,
 419                                         pe->pe_number);
 420                 }
 421         }
 422
 423         kfree(pe_alloc);
 424         return master_pe;
 425 }
 426
 427 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 428 {
 429         struct pci_controller *hose = phb->hose;
 430         struct device_node *dn = hose->dn;
 431         struct resource *res;
 432         u32 m64_range[2], i;
 433         const __be32 *r;
 434         u64 pci_addr;
 435
 436         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 437                 pr_info("  Not support M64 window\n");
 438                 return;
 439         }
 440
 441         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 442                 pr_info("  Firmware too old to support M64 window\n");
 443                 return;
 444         }
 445
 446         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 447         if (!r) {
 448                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 449                         dn->full_name);
 450                 return;
 451         }
 452
 453         /*
 454          * Find the available M64 BAR range and pickup the last one for
 455          * covering the whole 64-bits space. We support only one range.
 456          */
 457         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 458                                        m64_range, 2)) {
 459                 /* In absence of the property, assume 0..15 */
 460                 m64_range[0] = 0;
 461                 m64_range[1] = 16;
 462         }
 463         /* We only support 64 bits in our allocator */
 464         if (m64_range[1] > 63) {
 465                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 466                         __func__, m64_range[1], phb->hose->global_number);
 467                 m64_range[1] = 63;
 468         }
 469         /* Empty range, no m64 */
 470         if (m64_range[1] <= m64_range[0]) {
 471                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 472                         __func__, phb->hose->global_number);
 473                 return;
 474         }
 475
 476         /* Configure M64 informations */
 477         res = &hose->mem_resources[1];
 478         res->name = dn->full_name;
 479         res->start = of_translate_address(dn, r + 2);
 480         res->end = res->start + of_read_number(r + 4, 2) - 1;
 481         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 482         pci_addr = of_read_number(r, 2);
 483         hose->mem_offset[1] = res->start - pci_addr;
 484
 485         phb->ioda.m64_size = resource_size(res);
 486         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 487         phb->ioda.m64_base = pci_addr;
 488
 489         /* This lines up nicely with the display from processing OF ranges */
 490         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 491                 res->start, res->end, pci_addr, m64_range[0],
 492                 m64_range[0] + m64_range[1] - 1);
 493
 494         /* Mark all M64 used up by default */
 495         phb->ioda.m64_bar_alloc = (unsigned long)-1;
 496
 497         /* Use last M64 BAR to cover M64 window */
 498         m64_range[1]--;
 499         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 500
 501         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 502
 503         /* Mark remaining ones free */
 504         for (i = m64_range[0]; i < m64_range[1]; i++)
 505                 clear_bit(i, &phb->ioda.m64_bar_alloc);
 506
 507         /*
 508          * Setup init functions for M64 based on IODA version, IODA3 uses
 509          * the IODA2 code.
 510          */
 511         if (phb->type == PNV_PHB_IODA1)
 512                 phb->init_m64 = pnv_ioda1_init_m64;
 513         else
 514                 phb->init_m64 = pnv_ioda2_init_m64;
 515         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
 516         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
 517 }
 518
 519 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 520 {
 521         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 522         struct pnv_ioda_pe *slave;
 523         s64 rc;
 524
 525         /* Fetch master PE */
 526         if (pe->flags & PNV_IODA_PE_SLAVE) {
 527                 pe = pe->master;
 528                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 529                         return;
 530
 531                 pe_no = pe->pe_number;
 532         }
 533
 534         /* Freeze master PE */
 535         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 536                                      pe_no,
 537                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 538         if (rc != OPAL_SUCCESS) {
 539                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 540                         __func__, rc, phb->hose->global_number, pe_no);
 541                 return;
 542         }
 543
 544         /* Freeze slave PEs */
 545         if (!(pe->flags & PNV_IODA_PE_MASTER))
 546                 return;
 547
 548         list_for_each_entry(slave, &pe->slaves, list) {
 549                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 550                                              slave->pe_number,
 551                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 552                 if (rc != OPAL_SUCCESS)
 553                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 554                                 __func__, rc, phb->hose->global_number,
 555                                 slave->pe_number);
 556         }
 557 }
 558
 559 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 560 {
 561         struct pnv_ioda_pe *pe, *slave;
 562         s64 rc;
 563
 564         /* Find master PE */
 565         pe = &phb->ioda.pe_array[pe_no];
 566         if (pe->flags & PNV_IODA_PE_SLAVE) {
 567                 pe = pe->master;
 568                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 569                 pe_no = pe->pe_number;
 570         }
 571
 572         /* Clear frozen state for master PE */
 573         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 574         if (rc != OPAL_SUCCESS) {
 575                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 576                         __func__, rc, opt, phb->hose->global_number, pe_no);
 577                 return -EIO;
 578         }
 579
 580         if (!(pe->flags & PNV_IODA_PE_MASTER))
 581                 return 0;
 582
 583         /* Clear frozen state for slave PEs */
 584         list_for_each_entry(slave, &pe->slaves, list) {
 585                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 586                                              slave->pe_number,
 587                                              opt);
 588                 if (rc != OPAL_SUCCESS) {
 589                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 590                                 __func__, rc, opt, phb->hose->global_number,
 591                                 slave->pe_number);
 592                         return -EIO;
 593                 }
 594         }
 595
 596         return 0;
 597 }
 598
 599 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 600 {
 601         struct pnv_ioda_pe *slave, *pe;
 602         u8 fstate = 0, state;
 603         __be16 pcierr = 0;
 604         s64 rc;
 605
 606         /* Sanity check on PE number */
 607         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 608                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 609
 610         /*
 611          * Fetch the master PE and the PE instance might be
 612          * not initialized yet.
 613          */
 614         pe = &phb->ioda.pe_array[pe_no];
 615         if (pe->flags & PNV_IODA_PE_SLAVE) {
 616                 pe = pe->master;
 617                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 618                 pe_no = pe->pe_number;
 619         }
 620
 621         /* Check the master PE */
 622         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 623                                         &state, &pcierr, NULL);
 624         if (rc != OPAL_SUCCESS) {
 625                 pr_warn("%s: Failure %lld getting "
 626                         "PHB#%x-PE#%x state\n",
 627                         __func__, rc,
 628                         phb->hose->global_number, pe_no);
 629                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 630         }
 631
 632         /* Check the slave PE */
 633         if (!(pe->flags & PNV_IODA_PE_MASTER))
 634                 return state;
 635
 636         list_for_each_entry(slave, &pe->slaves, list) {
 637                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 638                                                 slave->pe_number,
 639                                                 &fstate,
 640                                                 &pcierr,
 641                                                 NULL);
 642                 if (rc != OPAL_SUCCESS) {
 643                         pr_warn("%s: Failure %lld getting "
 644                                 "PHB#%x-PE#%x state\n",
 645                                 __func__, rc,
 646                                 phb->hose->global_number, slave->pe_number);
 647                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 648                 }
 649
 650                 /*
 651                  * Override the result based on the ascending
 652                  * priority.
 653                  */
 654                 if (fstate > state)
 655                         state = fstate;
 656         }
 657
 658         return state;
 659 }
 660
 661 /* Currently those 2 are only used when MSIs are enabled, this will change
 662  * but in the meantime, we need to protect them to avoid warnings
 663  */
 664 #ifdef CONFIG_PCI_MSI
 665 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 666 {
 667         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 668         struct pnv_phb *phb = hose->private_data;
 669         struct pci_dn *pdn = pci_get_pdn(dev);
 670
 671         if (!pdn)
 672                 return NULL;
 673         if (pdn->pe_number == IODA_INVALID_PE)
 674                 return NULL;
 675         return &phb->ioda.pe_array[pdn->pe_number];
 676 }
 677 #endif /* CONFIG_PCI_MSI */
 678
 679 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 680                                   struct pnv_ioda_pe *parent,
 681                                   struct pnv_ioda_pe *child,
 682                                   bool is_add)
 683 {
 684         const char *desc = is_add ? "adding" : "removing";
 685         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 686                               OPAL_REMOVE_PE_FROM_DOMAIN;
 687         struct pnv_ioda_pe *slave;
 688         long rc;
 689
 690         /* Parent PE affects child PE */
 691         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 692                                 child->pe_number, op);
 693         if (rc != OPAL_SUCCESS) {
 694                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 695                         rc, desc);
 696                 return -ENXIO;
 697         }
 698
 699         if (!(child->flags & PNV_IODA_PE_MASTER))
 700                 return 0;
 701
 702         /* Compound case: parent PE affects slave PEs */
 703         list_for_each_entry(slave, &child->slaves, list) {
 704                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 705                                         slave->pe_number, op);
 706                 if (rc != OPAL_SUCCESS) {
 707                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 708                                 rc, desc);
 709                         return -ENXIO;
 710                 }
 711         }
 712
 713         return 0;
 714 }
 715
 716 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 717                               struct pnv_ioda_pe *pe,
 718                               bool is_add)
 719 {
 720         struct pnv_ioda_pe *slave;
 721         struct pci_dev *pdev = NULL;
 722         int ret;
 723
 724         /*
 725          * Clear PE frozen state. If it's master PE, we need
 726          * clear slave PE frozen state as well.
 727          */
 728         if (is_add) {
 729                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 730                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 731                 if (pe->flags & PNV_IODA_PE_MASTER) {
 732                         list_for_each_entry(slave, &pe->slaves, list)
 733                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 734                                                           slave->pe_number,
 735                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 736                 }
 737         }
 738
 739         /*
 740          * Associate PE in PELT. We need add the PE into the
 741          * corresponding PELT-V as well. Otherwise, the error
 742          * originated from the PE might contribute to other
 743          * PEs.
 744          */
 745         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 746         if (ret)
 747                 return ret;
 748
 749         /* For compound PEs, any one affects all of them */
 750         if (pe->flags & PNV_IODA_PE_MASTER) {
 751                 list_for_each_entry(slave, &pe->slaves, list) {
 752                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 753                         if (ret)
 754                                 return ret;
 755                 }
 756         }
 757
 758         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 759                 pdev = pe->pbus->self;
 760         else if (pe->flags & PNV_IODA_PE_DEV)
 761                 pdev = pe->pdev->bus->self;
 762 #ifdef CONFIG_PCI_IOV
 763         else if (pe->flags & PNV_IODA_PE_VF)
 764                 pdev = pe->parent_dev;
 765 #endif /* CONFIG_PCI_IOV */
 766         while (pdev) {
 767                 struct pci_dn *pdn = pci_get_pdn(pdev);
 768                 struct pnv_ioda_pe *parent;
 769
 770                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 771                         parent = &phb->ioda.pe_array[pdn->pe_number];
 772                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 773                         if (ret)
 774                                 return ret;
 775                 }
 776
 777                 pdev = pdev->bus->self;
 778         }
 779
 780         return 0;
 781 }
 782
 783 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 784 {
 785         struct pci_dev *parent;
 786         uint8_t bcomp, dcomp, fcomp;
 787         int64_t rc;
 788         long rid_end, rid;
 789
 790         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 791         if (pe->pbus) {
 792                 int count;
 793
 794                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 795                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 796                 parent = pe->pbus->self;
 797                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 798                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 799                 else
 800                         count = 1;
 801
 802                 switch(count) {
 803                 case  1: bcomp = OpalPciBusAll;         break;
 804                 case  2: bcomp = OpalPciBus7Bits;       break;
 805                 case  4: bcomp = OpalPciBus6Bits;       break;
 806                 case  8: bcomp = OpalPciBus5Bits;       break;
 807                 case 16: bcomp = OpalPciBus4Bits;       break;
 808                 case 32: bcomp = OpalPciBus3Bits;       break;
 809                 default:
 810                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 811                                 count);
 812                         /* Do an exact match only */
 813                         bcomp = OpalPciBusAll;
 814                 }
 815                 rid_end = pe->rid + (count << 8);
 816         } else {
 817 #ifdef CONFIG_PCI_IOV
 818                 if (pe->flags & PNV_IODA_PE_VF)
 819                         parent = pe->parent_dev;
 820                 else
 821 #endif
 822                         parent = pe->pdev->bus->self;
 823                 bcomp = OpalPciBusAll;
 824                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 825                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 826                 rid_end = pe->rid + 1;
 827         }
 828
 829         /* Clear the reverse map */
 830         for (rid = pe->rid; rid < rid_end; rid++)
 831                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 832
 833         /* Release from all parents PELT-V */
 834         while (parent) {
 835                 struct pci_dn *pdn = pci_get_pdn(parent);
 836                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 837                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 838                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 839                         /* XXX What to do in case of error ? */
 840                 }
 841                 parent = parent->bus->self;
 842         }
 843
 844         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 845                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 846
 847         /* Disassociate PE in PELT */
 848         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 849                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 850         if (rc)
 851                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 852         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 853                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 854         if (rc)
 855                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 856
 857         pe->pbus = NULL;
 858         pe->pdev = NULL;
 859 #ifdef CONFIG_PCI_IOV
 860         pe->parent_dev = NULL;
 861 #endif
 862
 863         return 0;
 864 }
 865
 866 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 867 {
 868         struct pci_dev *parent;
 869         uint8_t bcomp, dcomp, fcomp;
 870         long rc, rid_end, rid;
 871
 872         /* Bus validation ? */
 873         if (pe->pbus) {
 874                 int count;
 875
 876                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 877                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 878                 parent = pe->pbus->self;
 879                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 880                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 881                 else
 882                         count = 1;
 883
 884                 switch(count) {
 885                 case  1: bcomp = OpalPciBusAll;         break;
 886                 case  2: bcomp = OpalPciBus7Bits;       break;
 887                 case  4: bcomp = OpalPciBus6Bits;       break;
 888                 case  8: bcomp = OpalPciBus5Bits;       break;
 889                 case 16: bcomp = OpalPciBus4Bits;       break;
 890                 case 32: bcomp = OpalPciBus3Bits;       break;
 891                 default:
 892                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 893                                 count);
 894                         /* Do an exact match only */
 895                         bcomp = OpalPciBusAll;
 896                 }
 897                 rid_end = pe->rid + (count << 8);
 898         } else {
 899 #ifdef CONFIG_PCI_IOV
 900                 if (pe->flags & PNV_IODA_PE_VF)
 901                         parent = pe->parent_dev;
 902                 else
 903 #endif /* CONFIG_PCI_IOV */
 904                         parent = pe->pdev->bus->self;
 905                 bcomp = OpalPciBusAll;
 906                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 907                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 908                 rid_end = pe->rid + 1;
 909         }
 910
 911         /*
 912          * Associate PE in PELT. We need add the PE into the
 913          * corresponding PELT-V as well. Otherwise, the error
 914          * originated from the PE might contribute to other
 915          * PEs.
 916          */
 917         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 918                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 919         if (rc) {
 920                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 921                 return -ENXIO;
 922         }
 923
 924         /*
 925          * Configure PELTV. NPUs don't have a PELTV table so skip
 926          * configuration on them.
 927          */
 928         if (phb->type != PNV_PHB_NPU)
 929                 pnv_ioda_set_peltv(phb, pe, true);
 930
 931         /* Setup reverse map */
 932         for (rid = pe->rid; rid < rid_end; rid++)
 933                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 934
 935         /* Setup one MVTs on IODA1 */
 936         if (phb->type != PNV_PHB_IODA1) {
 937                 pe->mve_number = 0;
 938                 goto out;
 939         }
 940
 941         pe->mve_number = pe->pe_number;
 942         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 943         if (rc != OPAL_SUCCESS) {
 944                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 945                        rc, pe->mve_number);
 946                 pe->mve_number = -1;
 947         } else {
 948                 rc = opal_pci_set_mve_enable(phb->opal_id,
 949                                              pe->mve_number, OPAL_ENABLE_MVE);
 950                 if (rc) {
 951                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 952                                rc, pe->mve_number);
 953                         pe->mve_number = -1;
 954                 }
 955         }
 956
 957 out:
 958         return 0;
 959 }
 960
 961 #ifdef CONFIG_PCI_IOV
 962 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 963 {
 964         struct pci_dn *pdn = pci_get_pdn(dev);
 965         int i;
 966         struct resource *res, res2;
 967         resource_size_t size;
 968         u16 num_vfs;
 969
 970         if (!dev->is_physfn)
 971                 return -EINVAL;
 972
 973         /*
 974          * "offset" is in VFs.  The M64 windows are sized so that when they
 975          * are segmented, each segment is the same size as the IOV BAR.
 976          * Each segment is in a separate PE, and the high order bits of the
 977          * address are the PE number.  Therefore, each VF's BAR is in a
 978          * separate PE, and changing the IOV BAR start address changes the
 979          * range of PEs the VFs are in.
 980          */
 981         num_vfs = pdn->num_vfs;
 982         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 983                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 984                 if (!res->flags || !res->parent)
 985                         continue;
 986
 987                 /*
 988                  * The actual IOV BAR range is determined by the start address
 989                  * and the actual size for num_vfs VFs BAR.  This check is to
 990                  * make sure that after shifting, the range will not overlap
 991                  * with another device.
 992                  */
 993                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 994                 res2.flags = res->flags;
 995                 res2.start = res->start + (size * offset);
 996                 res2.end = res2.start + (size * num_vfs) - 1;
 997
 998                 if (res2.end > res->end) {
 999                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1000                                 i, &res2, res, num_vfs, offset);
1001                         return -EBUSY;
1002                 }
1003         }
1004
1005         /*
1006          * After doing so, there would be a "hole" in the /proc/iomem when
1007          * offset is a positive value. It looks like the device return some
1008          * mmio back to the system, which actually no one could use it.
1009          */
1010         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1011                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1012                 if (!res->flags || !res->parent)
1013                         continue;
1014
1015                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1016                 res2 = *res;
1017                 res->start += size * offset;
1018
1019                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1020                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1021                          num_vfs, offset);
1022                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1023         }
1024         return 0;
1025 }
1026 #endif /* CONFIG_PCI_IOV */
1027
1028 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1029 {
1030         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1031         struct pnv_phb *phb = hose->private_data;
1032         struct pci_dn *pdn = pci_get_pdn(dev);
1033         struct pnv_ioda_pe *pe;
1034
1035         if (!pdn) {
1036                 pr_err("%s: Device tree node not associated properly\n",
1037                            pci_name(dev));
1038                 return NULL;
1039         }
1040         if (pdn->pe_number != IODA_INVALID_PE)
1041                 return NULL;
1042
1043         pe = pnv_ioda_alloc_pe(phb);
1044         if (!pe) {
1045                 pr_warning("%s: Not enough PE# available, disabling device\n",
1046                            pci_name(dev));
1047                 return NULL;
1048         }
1049
1050         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1051          * pointer in the PE data structure, both should be destroyed at the
1052          * same time. However, this needs to be looked at more closely again
1053          * once we actually start removing things (Hotplug, SR-IOV, ...)
1054          *
1055          * At some point we want to remove the PDN completely anyways
1056          */
1057         pci_dev_get(dev);
1058         pdn->pcidev = dev;
1059         pdn->pe_number = pe->pe_number;
1060         pe->flags = PNV_IODA_PE_DEV;
1061         pe->pdev = dev;
1062         pe->pbus = NULL;
1063         pe->mve_number = -1;
1064         pe->rid = dev->bus->number << 8 | pdn->devfn;
1065
1066         pe_info(pe, "Associated device to PE\n");
1067
1068         if (pnv_ioda_configure_pe(phb, pe)) {
1069                 /* XXX What do we do here ? */
1070                 pnv_ioda_free_pe(pe);
1071                 pdn->pe_number = IODA_INVALID_PE;
1072                 pe->pdev = NULL;
1073                 pci_dev_put(dev);
1074                 return NULL;
1075         }
1076
1077         /* Put PE to the list */
1078         list_add_tail(&pe->list, &phb->ioda.pe_list);
1079
1080         return pe;
1081 }
1082
1083 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1084 {
1085         struct pci_dev *dev;
1086
1087         list_for_each_entry(dev, &bus->devices, bus_list) {
1088                 struct pci_dn *pdn = pci_get_pdn(dev);
1089
1090                 if (pdn == NULL) {
1091                         pr_warn("%s: No device node associated with device !\n",
1092                                 pci_name(dev));
1093                         continue;
1094                 }
1095
1096                 /*
1097                  * In partial hotplug case, the PCI device might be still
1098                  * associated with the PE and needn't attach it to the PE
1099                  * again.
1100                  */
1101                 if (pdn->pe_number != IODA_INVALID_PE)
1102                         continue;
1103
1104                 pe->device_count++;
1105                 pdn->pcidev = dev;
1106                 pdn->pe_number = pe->pe_number;
1107                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1108                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1109         }
1110 }
1111
1112 /*
1113  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1114  * single PCI bus. Another one that contains the primary PCI bus and its
1115  * subordinate PCI devices and buses. The second type of PE is normally
1116  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1117  */
1118 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1119 {
1120         struct pci_controller *hose = pci_bus_to_host(bus);
1121         struct pnv_phb *phb = hose->private_data;
1122         struct pnv_ioda_pe *pe = NULL;
1123         unsigned int pe_num;
1124
1125         /*
1126          * In partial hotplug case, the PE instance might be still alive.
1127          * We should reuse it instead of allocating a new one.
1128          */
1129         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1130         if (pe_num != IODA_INVALID_PE) {
1131                 pe = &phb->ioda.pe_array[pe_num];
1132                 pnv_ioda_setup_same_PE(bus, pe);
1133                 return NULL;
1134         }
1135
1136         /* PE number for root bus should have been reserved */
1137         if (pci_is_root_bus(bus) &&
1138             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1139                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1140
1141         /* Check if PE is determined by M64 */
1142         if (!pe && phb->pick_m64_pe)
1143                 pe = phb->pick_m64_pe(bus, all);
1144
1145         /* The PE number isn't pinned by M64 */
1146         if (!pe)
1147                 pe = pnv_ioda_alloc_pe(phb);
1148
1149         if (!pe) {
1150                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1151                         __func__, pci_domain_nr(bus), bus->number);
1152                 return NULL;
1153         }
1154
1155         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1156         pe->pbus = bus;
1157         pe->pdev = NULL;
1158         pe->mve_number = -1;
1159         pe->rid = bus->busn_res.start << 8;
1160
1161         if (all)
1162                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1163                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1164         else
1165                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1166                         bus->busn_res.start, pe->pe_number);
1167
1168         if (pnv_ioda_configure_pe(phb, pe)) {
1169                 /* XXX What do we do here ? */
1170                 pnv_ioda_free_pe(pe);
1171                 pe->pbus = NULL;
1172                 return NULL;
1173         }
1174
1175         /* Associate it with all child devices */
1176         pnv_ioda_setup_same_PE(bus, pe);
1177
1178         /* Put PE to the list */
1179         list_add_tail(&pe->list, &phb->ioda.pe_list);
1180
1181         return pe;
1182 }
1183
1184 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1185 {
1186         int pe_num, found_pe = false, rc;
1187         long rid;
1188         struct pnv_ioda_pe *pe;
1189         struct pci_dev *gpu_pdev;
1190         struct pci_dn *npu_pdn;
1191         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1192         struct pnv_phb *phb = hose->private_data;
1193
1194         /*
1195          * Due to a hardware errata PE#0 on the NPU is reserved for
1196          * error handling. This means we only have three PEs remaining
1197          * which need to be assigned to four links, implying some
1198          * links must share PEs.
1199          *
1200          * To achieve this we assign PEs such that NPUs linking the
1201          * same GPU get assigned the same PE.
1202          */
1203         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1204         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1205                 pe = &phb->ioda.pe_array[pe_num];
1206                 if (!pe->pdev)
1207                         continue;
1208
1209                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1210                         /*
1211                          * This device has the same peer GPU so should
1212                          * be assigned the same PE as the existing
1213                          * peer NPU.
1214                          */
1215                         dev_info(&npu_pdev->dev,
1216                                 "Associating to existing PE %d\n", pe_num);
1217                         pci_dev_get(npu_pdev);
1218                         npu_pdn = pci_get_pdn(npu_pdev);
1219                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1220                         npu_pdn->pcidev = npu_pdev;
1221                         npu_pdn->pe_number = pe_num;
1222                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1223
1224                         /* Map the PE to this link */
1225                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1226                                         OpalPciBusAll,
1227                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1228                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1229                                         OPAL_MAP_PE);
1230                         WARN_ON(rc != OPAL_SUCCESS);
1231                         found_pe = true;
1232                         break;
1233                 }
1234         }
1235
1236         if (!found_pe)
1237                 /*
1238                  * Could not find an existing PE so allocate a new
1239                  * one.
1240                  */
1241                 return pnv_ioda_setup_dev_PE(npu_pdev);
1242         else
1243                 return pe;
1244 }
1245
1246 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1247 {
1248         struct pci_dev *pdev;
1249
1250         list_for_each_entry(pdev, &bus->devices, bus_list)
1251                 pnv_ioda_setup_npu_PE(pdev);
1252 }
1253
1254 static void pnv_pci_ioda_setup_PEs(void)
1255 {
1256         struct pci_controller *hose, *tmp;
1257         struct pnv_phb *phb;
1258
1259         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1260                 phb = hose->private_data;
1261                 if (phb->type == PNV_PHB_NPU) {
1262                         /* PE#0 is needed for error reporting */
1263                         pnv_ioda_reserve_pe(phb, 0);
1264                         pnv_ioda_setup_npu_PEs(hose->bus);
1265                 }
1266         }
1267 }
1268
1269 #ifdef CONFIG_PCI_IOV
1270 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1271 {
1272         struct pci_bus        *bus;
1273         struct pci_controller *hose;
1274         struct pnv_phb        *phb;
1275         struct pci_dn         *pdn;
1276         int                    i, j;
1277         int                    m64_bars;
1278
1279         bus = pdev->bus;
1280         hose = pci_bus_to_host(bus);
1281         phb = hose->private_data;
1282         pdn = pci_get_pdn(pdev);
1283
1284         if (pdn->m64_single_mode)
1285                 m64_bars = num_vfs;
1286         else
1287                 m64_bars = 1;
1288
1289         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1290                 for (j = 0; j < m64_bars; j++) {
1291                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1292                                 continue;
1293                         opal_pci_phb_mmio_enable(phb->opal_id,
1294                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1295                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1296                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1297                 }
1298
1299         kfree(pdn->m64_map);
1300         return 0;
1301 }
1302
1303 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1304 {
1305         struct pci_bus        *bus;
1306         struct pci_controller *hose;
1307         struct pnv_phb        *phb;
1308         struct pci_dn         *pdn;
1309         unsigned int           win;
1310         struct resource       *res;
1311         int                    i, j;
1312         int64_t                rc;
1313         int                    total_vfs;
1314         resource_size_t        size, start;
1315         int                    pe_num;
1316         int                    m64_bars;
1317
1318         bus = pdev->bus;
1319         hose = pci_bus_to_host(bus);
1320         phb = hose->private_data;
1321         pdn = pci_get_pdn(pdev);
1322         total_vfs = pci_sriov_get_totalvfs(pdev);
1323
1324         if (pdn->m64_single_mode)
1325                 m64_bars = num_vfs;
1326         else
1327                 m64_bars = 1;
1328
1329         pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1330         if (!pdn->m64_map)
1331                 return -ENOMEM;
1332         /* Initialize the m64_map to IODA_INVALID_M64 */
1333         for (i = 0; i < m64_bars ; i++)
1334                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1335                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1336
1337
1338         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1339                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1340                 if (!res->flags || !res->parent)
1341                         continue;
1342
1343                 for (j = 0; j < m64_bars; j++) {
1344                         do {
1345                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1346                                                 phb->ioda.m64_bar_idx + 1, 0);
1347
1348                                 if (win >= phb->ioda.m64_bar_idx + 1)
1349                                         goto m64_failed;
1350                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1351
1352                         pdn->m64_map[j][i] = win;
1353
1354                         if (pdn->m64_single_mode) {
1355                                 size = pci_iov_resource_size(pdev,
1356                                                         PCI_IOV_RESOURCES + i);
1357                                 start = res->start + size * j;
1358                         } else {
1359                                 size = resource_size(res);
1360                                 start = res->start;
1361                         }
1362
1363                         /* Map the M64 here */
1364                         if (pdn->m64_single_mode) {
1365                                 pe_num = pdn->pe_num_map[j];
1366                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1367                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1368                                                 pdn->m64_map[j][i], 0);
1369                         }
1370
1371                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1372                                                  OPAL_M64_WINDOW_TYPE,
1373                                                  pdn->m64_map[j][i],
1374                                                  start,
1375                                                  0, /* unused */
1376                                                  size);
1377
1378
1379                         if (rc != OPAL_SUCCESS) {
1380                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1381                                         win, rc);
1382                                 goto m64_failed;
1383                         }
1384
1385                         if (pdn->m64_single_mode)
1386                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1387                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1388                         else
1389                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1390                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1391
1392                         if (rc != OPAL_SUCCESS) {
1393                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1394                                         win, rc);
1395                                 goto m64_failed;
1396                         }
1397                 }
1398         }
1399         return 0;
1400
1401 m64_failed:
1402         pnv_pci_vf_release_m64(pdev, num_vfs);
1403         return -EBUSY;
1404 }
1405
1406 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1407                 int num);
1408 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1409
1410 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1411 {
1412         struct iommu_table    *tbl;
1413         int64_t               rc;
1414
1415         tbl = pe->table_group.tables[0];
1416         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1417         if (rc)
1418                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1419
1420         pnv_pci_ioda2_set_bypass(pe, false);
1421         if (pe->table_group.group) {
1422                 iommu_group_put(pe->table_group.group);
1423                 BUG_ON(pe->table_group.group);
1424         }
1425         pnv_pci_ioda2_table_free_pages(tbl);
1426         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1427 }
1428
1429 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1430 {
1431         struct pci_bus        *bus;
1432         struct pci_controller *hose;
1433         struct pnv_phb        *phb;
1434         struct pnv_ioda_pe    *pe, *pe_n;
1435         struct pci_dn         *pdn;
1436
1437         bus = pdev->bus;
1438         hose = pci_bus_to_host(bus);
1439         phb = hose->private_data;
1440         pdn = pci_get_pdn(pdev);
1441
1442         if (!pdev->is_physfn)
1443                 return;
1444
1445         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1446                 if (pe->parent_dev != pdev)
1447                         continue;
1448
1449                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1450
1451                 /* Remove from list */
1452                 mutex_lock(&phb->ioda.pe_list_mutex);
1453                 list_del(&pe->list);
1454                 mutex_unlock(&phb->ioda.pe_list_mutex);
1455
1456                 pnv_ioda_deconfigure_pe(phb, pe);
1457
1458                 pnv_ioda_free_pe(pe);
1459         }
1460 }
1461
1462 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1463 {
1464         struct pci_bus        *bus;
1465         struct pci_controller *hose;
1466         struct pnv_phb        *phb;
1467         struct pnv_ioda_pe    *pe;
1468         struct pci_dn         *pdn;
1469         struct pci_sriov      *iov;
1470         u16                    num_vfs, i;
1471
1472         bus = pdev->bus;
1473         hose = pci_bus_to_host(bus);
1474         phb = hose->private_data;
1475         pdn = pci_get_pdn(pdev);
1476         iov = pdev->sriov;
1477         num_vfs = pdn->num_vfs;
1478
1479         /* Release VF PEs */
1480         pnv_ioda_release_vf_PE(pdev);
1481
1482         if (phb->type == PNV_PHB_IODA2) {
1483                 if (!pdn->m64_single_mode)
1484                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1485
1486                 /* Release M64 windows */
1487                 pnv_pci_vf_release_m64(pdev, num_vfs);
1488
1489                 /* Release PE numbers */
1490                 if (pdn->m64_single_mode) {
1491                         for (i = 0; i < num_vfs; i++) {
1492                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1493                                         continue;
1494
1495                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1496                                 pnv_ioda_free_pe(pe);
1497                         }
1498                 } else
1499                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1500                 /* Releasing pe_num_map */
1501                 kfree(pdn->pe_num_map);
1502         }
1503 }
1504
1505 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1506                                        struct pnv_ioda_pe *pe);
1507 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1508 {
1509         struct pci_bus        *bus;
1510         struct pci_controller *hose;
1511         struct pnv_phb        *phb;
1512         struct pnv_ioda_pe    *pe;
1513         int                    pe_num;
1514         u16                    vf_index;
1515         struct pci_dn         *pdn;
1516
1517         bus = pdev->bus;
1518         hose = pci_bus_to_host(bus);
1519         phb = hose->private_data;
1520         pdn = pci_get_pdn(pdev);
1521
1522         if (!pdev->is_physfn)
1523                 return;
1524
1525         /* Reserve PE for each VF */
1526         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1527                 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
1528                 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
1529                 struct pci_dn *vf_pdn;
1530
1531                 if (pdn->m64_single_mode)
1532                         pe_num = pdn->pe_num_map[vf_index];
1533                 else
1534                         pe_num = *pdn->pe_num_map + vf_index;
1535
1536                 pe = &phb->ioda.pe_array[pe_num];
1537                 pe->pe_number = pe_num;
1538                 pe->phb = phb;
1539                 pe->flags = PNV_IODA_PE_VF;
1540                 pe->pbus = NULL;
1541                 pe->parent_dev = pdev;
1542                 pe->mve_number = -1;
1543                 pe->rid = (vf_bus << 8) | vf_devfn;
1544
1545                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1546                         hose->global_number, pdev->bus->number,
1547                         PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
1548
1549                 if (pnv_ioda_configure_pe(phb, pe)) {
1550                         /* XXX What do we do here ? */
1551                         pnv_ioda_free_pe(pe);
1552                         pe->pdev = NULL;
1553                         continue;
1554                 }
1555
1556                 /* Put PE to the list */
1557                 mutex_lock(&phb->ioda.pe_list_mutex);
1558                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1559                 mutex_unlock(&phb->ioda.pe_list_mutex);
1560
1561                 /* associate this pe to it's pdn */
1562                 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
1563                         if (vf_pdn->busno == vf_bus &&
1564                             vf_pdn->devfn == vf_devfn) {
1565                                 vf_pdn->pe_number = pe_num;
1566                                 break;
1567                         }
1568                 }
1569
1570                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1571         }
1572 }
1573
1574 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1575 {
1576         struct pci_bus        *bus;
1577         struct pci_controller *hose;
1578         struct pnv_phb        *phb;
1579         struct pnv_ioda_pe    *pe;
1580         struct pci_dn         *pdn;
1581         int                    ret;
1582         u16                    i;
1583
1584         bus = pdev->bus;
1585         hose = pci_bus_to_host(bus);
1586         phb = hose->private_data;
1587         pdn = pci_get_pdn(pdev);
1588
1589         if (phb->type == PNV_PHB_IODA2) {
1590                 if (!pdn->vfs_expanded) {
1591                         dev_info(&pdev->dev, "don't support this SRIOV device"
1592                                 " with non 64bit-prefetchable IOV BAR\n");
1593                         return -ENOSPC;
1594                 }
1595
1596                 /*
1597                  * When M64 BARs functions in Single PE mode, the number of VFs
1598                  * could be enabled must be less than the number of M64 BARs.
1599                  */
1600                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1601                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1602                         return -EBUSY;
1603                 }
1604
1605                 /* Allocating pe_num_map */
1606                 if (pdn->m64_single_mode)
1607                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1608                                         GFP_KERNEL);
1609                 else
1610                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1611
1612                 if (!pdn->pe_num_map)
1613                         return -ENOMEM;
1614
1615                 if (pdn->m64_single_mode)
1616                         for (i = 0; i < num_vfs; i++)
1617                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1618
1619                 /* Calculate available PE for required VFs */
1620                 if (pdn->m64_single_mode) {
1621                         for (i = 0; i < num_vfs; i++) {
1622                                 pe = pnv_ioda_alloc_pe(phb);
1623                                 if (!pe) {
1624                                         ret = -EBUSY;
1625                                         goto m64_failed;
1626                                 }
1627
1628                                 pdn->pe_num_map[i] = pe->pe_number;
1629                         }
1630                 } else {
1631                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1632                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1633                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1634                                 0, num_vfs, 0);
1635                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1636                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1637                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1638                                 kfree(pdn->pe_num_map);
1639                                 return -EBUSY;
1640                         }
1641                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1642                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1643                 }
1644                 pdn->num_vfs = num_vfs;
1645
1646                 /* Assign M64 window accordingly */
1647                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1648                 if (ret) {
1649                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1650                         goto m64_failed;
1651                 }
1652
1653                 /*
1654                  * When using one M64 BAR to map one IOV BAR, we need to shift
1655                  * the IOV BAR according to the PE# allocated to the VFs.
1656                  * Otherwise, the PE# for the VF will conflict with others.
1657                  */
1658                 if (!pdn->m64_single_mode) {
1659                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1660                         if (ret)
1661                                 goto m64_failed;
1662                 }
1663         }
1664
1665         /* Setup VF PEs */
1666         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1667
1668         return 0;
1669
1670 m64_failed:
1671         if (pdn->m64_single_mode) {
1672                 for (i = 0; i < num_vfs; i++) {
1673                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1674                                 continue;
1675
1676                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1677                         pnv_ioda_free_pe(pe);
1678                 }
1679         } else
1680                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1681
1682         /* Releasing pe_num_map */
1683         kfree(pdn->pe_num_map);
1684
1685         return ret;
1686 }
1687
1688 int pcibios_sriov_disable(struct pci_dev *pdev)
1689 {
1690         pnv_pci_sriov_disable(pdev);
1691
1692         /* Release PCI data */
1693         remove_dev_pci_data(pdev);
1694         return 0;
1695 }
1696
1697 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1698 {
1699         /* Allocate PCI data */
1700         add_dev_pci_data(pdev);
1701
1702         return pnv_pci_sriov_enable(pdev, num_vfs);
1703 }
1704 #endif /* CONFIG_PCI_IOV */
1705
1706 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1707 {
1708         struct pci_dn *pdn = pci_get_pdn(pdev);
1709         struct pnv_ioda_pe *pe;
1710
1711         /*
1712          * The function can be called while the PE#
1713          * hasn't been assigned. Do nothing for the
1714          * case.
1715          */
1716         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1717                 return;
1718
1719         pe = &phb->ioda.pe_array[pdn->pe_number];
1720         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1721         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1722         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1723         /*
1724          * Note: iommu_add_device() will fail here as
1725          * for physical PE: the device is already added by now;
1726          * for virtual PE: sysfs entries are not ready yet and
1727          * tce_iommu_bus_notifier will add the device to a group later.
1728          */
1729 }
1730
1731 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1732 {
1733         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1734         struct pnv_phb *phb = hose->private_data;
1735         struct pci_dn *pdn = pci_get_pdn(pdev);
1736         struct pnv_ioda_pe *pe;
1737         uint64_t top;
1738         bool bypass = false;
1739
1740         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1741                 return -ENODEV;;
1742
1743         pe = &phb->ioda.pe_array[pdn->pe_number];
1744         if (pe->tce_bypass_enabled) {
1745                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1746                 bypass = (dma_mask >= top);
1747         }
1748
1749         if (bypass) {
1750                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1751                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1752         } else {
1753                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1754                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1755         }
1756         *pdev->dev.dma_mask = dma_mask;
1757
1758         /* Update peer npu devices */
1759         pnv_npu_try_dma_set_bypass(pdev, bypass);
1760
1761         return 0;
1762 }
1763
1764 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1765 {
1766         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1767         struct pnv_phb *phb = hose->private_data;
1768         struct pci_dn *pdn = pci_get_pdn(pdev);
1769         struct pnv_ioda_pe *pe;
1770         u64 end, mask;
1771
1772         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1773                 return 0;
1774
1775         pe = &phb->ioda.pe_array[pdn->pe_number];
1776         if (!pe->tce_bypass_enabled)
1777                 return __dma_get_required_mask(&pdev->dev);
1778
1779
1780         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1781         mask = 1ULL << (fls64(end) - 1);
1782         mask += mask - 1;
1783
1784         return mask;
1785 }
1786
1787 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1788                                    struct pci_bus *bus)
1789 {
1790         struct pci_dev *dev;
1791
1792         list_for_each_entry(dev, &bus->devices, bus_list) {
1793                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1794                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1795                 iommu_add_device(&dev->dev);
1796
1797                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1798                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1799         }
1800 }
1801
1802 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1803                                                      bool real_mode)
1804 {
1805         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1806                 (phb->regs + 0x210);
1807 }
1808
1809 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1810                 unsigned long index, unsigned long npages, bool rm)
1811 {
1812         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1813                         &tbl->it_group_list, struct iommu_table_group_link,
1814                         next);
1815         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1816                         struct pnv_ioda_pe, table_group);
1817         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1818         unsigned long start, end, inc;
1819
1820         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1821         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1822                         npages - 1);
1823
1824         /* p7ioc-style invalidation, 2 TCEs per write */
1825         start |= (1ull << 63);
1826         end |= (1ull << 63);
1827         inc = 16;
1828         end |= inc - 1; /* round up end to be different than start */
1829
1830         mb(); /* Ensure above stores are visible */
1831         while (start <= end) {
1832                 if (rm)
1833                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1834                 else
1835                         __raw_writeq(cpu_to_be64(start), invalidate);
1836                 start += inc;
1837         }
1838
1839         /*
1840          * The iommu layer will do another mb() for us on build()
1841          * and we don't care on free()
1842          */
1843 }
1844
1845 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1846                 long npages, unsigned long uaddr,
1847                 enum dma_data_direction direction,
1848                 unsigned long attrs)
1849 {
1850         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1851                         attrs);
1852
1853         if (!ret)
1854                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1855
1856         return ret;
1857 }
1858
1859 #ifdef CONFIG_IOMMU_API
1860 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1861                 unsigned long *hpa, enum dma_data_direction *direction)
1862 {
1863         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1864
1865         if (!ret)
1866                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1867
1868         return ret;
1869 }
1870 #endif
1871
1872 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1873                 long npages)
1874 {
1875         pnv_tce_free(tbl, index, npages);
1876
1877         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1878 }
1879
1880 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1881         .set = pnv_ioda1_tce_build,
1882 #ifdef CONFIG_IOMMU_API
1883         .exchange = pnv_ioda1_tce_xchg,
1884 #endif
1885         .clear = pnv_ioda1_tce_free,
1886         .get = pnv_tce_get,
1887 };
1888
1889 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
1890 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
1891 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
1892
1893 void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1894 {
1895         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1896         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1897
1898         mb(); /* Ensure previous TCE table stores are visible */
1899         if (rm)
1900                 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1901         else
1902                 __raw_writeq(cpu_to_be64(val), invalidate);
1903 }
1904
1905 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1906 {
1907         /* 01xb - invalidate TCEs that match the specified PE# */
1908         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1909         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1910
1911         mb(); /* Ensure above stores are visible */
1912         __raw_writeq(cpu_to_be64(val), invalidate);
1913 }
1914
1915 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1916                                         unsigned shift, unsigned long index,
1917                                         unsigned long npages)
1918 {
1919         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1920         unsigned long start, end, inc;
1921
1922         /* We'll invalidate DMA address in PE scope */
1923         start = PHB3_TCE_KILL_INVAL_ONE;
1924         start |= (pe->pe_number & 0xFF);
1925         end = start;
1926
1927         /* Figure out the start, end and step */
1928         start |= (index << shift);
1929         end |= ((index + npages - 1) << shift);
1930         inc = (0x1ull << shift);
1931         mb();
1932
1933         while (start <= end) {
1934                 if (rm)
1935                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1936                 else
1937                         __raw_writeq(cpu_to_be64(start), invalidate);
1938                 start += inc;
1939         }
1940 }
1941
1942 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1943 {
1944         struct pnv_phb *phb = pe->phb;
1945
1946         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1947                 pnv_pci_phb3_tce_invalidate_pe(pe);
1948         else
1949                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1950                                   pe->pe_number, 0, 0, 0);
1951 }
1952
1953 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1954                 unsigned long index, unsigned long npages, bool rm)
1955 {
1956         struct iommu_table_group_link *tgl;
1957
1958         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1959                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1960                                 struct pnv_ioda_pe, table_group);
1961                 struct pnv_phb *phb = pe->phb;
1962                 unsigned int shift = tbl->it_page_shift;
1963
1964                 if (phb->type == PNV_PHB_NPU) {
1965                         /*
1966                          * The NVLink hardware does not support TCE kill
1967                          * per TCE entry so we have to invalidate
1968                          * the entire cache for it.
1969                          */
1970                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1971                         continue;
1972                 }
1973                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1974                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1975                                                     index, npages);
1976                 else if (rm)
1977                         opal_rm_pci_tce_kill(phb->opal_id,
1978                                              OPAL_PCI_TCE_KILL_PAGES,
1979                                              pe->pe_number, 1u << shift,
1980                                              index << shift, npages);
1981                 else
1982                         opal_pci_tce_kill(phb->opal_id,
1983                                           OPAL_PCI_TCE_KILL_PAGES,
1984                                           pe->pe_number, 1u << shift,
1985                                           index << shift, npages);
1986         }
1987 }
1988
1989 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1990                 long npages, unsigned long uaddr,
1991                 enum dma_data_direction direction,
1992                 unsigned long attrs)
1993 {
1994         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1995                         attrs);
1996
1997         if (!ret)
1998                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1999
2000         return ret;
2001 }
2002
2003 #ifdef CONFIG_IOMMU_API
2004 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2005                 unsigned long *hpa, enum dma_data_direction *direction)
2006 {
2007         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2008
2009         if (!ret)
2010                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2011
2012         return ret;
2013 }
2014 #endif
2015
2016 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2017                 long npages)
2018 {
2019         pnv_tce_free(tbl, index, npages);
2020
2021         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2022 }
2023
2024 static void pnv_ioda2_table_free(struct iommu_table *tbl)
2025 {
2026         pnv_pci_ioda2_table_free_pages(tbl);
2027         iommu_free_table(tbl, "pnv");
2028 }
2029
2030 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2031         .set = pnv_ioda2_tce_build,
2032 #ifdef CONFIG_IOMMU_API
2033         .exchange = pnv_ioda2_tce_xchg,
2034 #endif
2035         .clear = pnv_ioda2_tce_free,
2036         .get = pnv_tce_get,
2037         .free = pnv_ioda2_table_free,
2038 };
2039
2040 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2041 {
2042         unsigned int *weight = (unsigned int *)data;
2043
2044         /* This is quite simplistic. The "base" weight of a device
2045          * is 10. 0 means no DMA is to be accounted for it.
2046          */
2047         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2048                 return 0;
2049
2050         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2051             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2052             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2053                 *weight += 3;
2054         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2055                 *weight += 15;
2056         else
2057                 *weight += 10;
2058
2059         return 0;
2060 }
2061
2062 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2063 {
2064         unsigned int weight = 0;
2065
2066         /* SRIOV VF has same DMA32 weight as its PF */
2067 #ifdef CONFIG_PCI_IOV
2068         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2069                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2070                 return weight;
2071         }
2072 #endif
2073
2074         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2075                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2076         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2077                 struct pci_dev *pdev;
2078
2079                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2080                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2081         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2082                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2083         }
2084
2085         return weight;
2086 }
2087
2088 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2089                                        struct pnv_ioda_pe *pe)
2090 {
2091
2092         struct page *tce_mem = NULL;
2093         struct iommu_table *tbl;
2094         unsigned int weight, total_weight = 0;
2095         unsigned int tce32_segsz, base, segs, avail, i;
2096         int64_t rc;
2097         void *addr;
2098
2099         /* XXX FIXME: Handle 64-bit only DMA devices */
2100         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2101         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2102         weight = pnv_pci_ioda_pe_dma_weight(pe);
2103         if (!weight)
2104                 return;
2105
2106         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2107                      &total_weight);
2108         segs = (weight * phb->ioda.dma32_count) / total_weight;
2109         if (!segs)
2110                 segs = 1;
2111
2112         /*
2113          * Allocate contiguous DMA32 segments. We begin with the expected
2114          * number of segments. With one more attempt, the number of DMA32
2115          * segments to be allocated is decreased by one until one segment
2116          * is allocated successfully.
2117          */
2118         do {
2119                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2120                         for (avail = 0, i = base; i < base + segs; i++) {
2121                                 if (phb->ioda.dma32_segmap[i] ==
2122                                     IODA_INVALID_PE)
2123                                         avail++;
2124                         }
2125
2126                         if (avail == segs)
2127                                 goto found;
2128                 }
2129         } while (--segs);
2130
2131         if (!segs) {
2132                 pe_warn(pe, "No available DMA32 segments\n");
2133                 return;
2134         }
2135
2136 found:
2137         tbl = pnv_pci_table_alloc(phb->hose->node);
2138         iommu_register_group(&pe->table_group, phb->hose->global_number,
2139                         pe->pe_number);
2140         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2141
2142         /* Grab a 32-bit TCE table */
2143         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2144                 weight, total_weight, base, segs);
2145         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2146                 base * PNV_IODA1_DMA32_SEGSIZE,
2147                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2148
2149         /* XXX Currently, we allocate one big contiguous table for the
2150          * TCEs. We only really need one chunk per 256M of TCE space
2151          * (ie per segment) but that's an optimization for later, it
2152          * requires some added smarts with our get/put_tce implementation
2153          *
2154          * Each TCE page is 4KB in size and each TCE entry occupies 8
2155          * bytes
2156          */
2157         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2158         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2159                                    get_order(tce32_segsz * segs));
2160         if (!tce_mem) {
2161                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2162                 goto fail;
2163         }
2164         addr = page_address(tce_mem);
2165         memset(addr, 0, tce32_segsz * segs);
2166
2167         /* Configure HW */
2168         for (i = 0; i < segs; i++) {
2169                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2170                                               pe->pe_number,
2171                                               base + i, 1,
2172                                               __pa(addr) + tce32_segsz * i,
2173                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2174                 if (rc) {
2175                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2176                                " err %ld\n", rc);
2177                         goto fail;
2178                 }
2179         }
2180
2181         /* Setup DMA32 segment mapping */
2182         for (i = base; i < base + segs; i++)
2183                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2184
2185         /* Setup linux iommu table */
2186         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2187                                   base * PNV_IODA1_DMA32_SEGSIZE,
2188                                   IOMMU_PAGE_SHIFT_4K);
2189
2190         tbl->it_ops = &pnv_ioda1_iommu_ops;
2191         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2192         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2193         iommu_init_table(tbl, phb->hose->node);
2194
2195         if (pe->flags & PNV_IODA_PE_DEV) {
2196                 /*
2197                  * Setting table base here only for carrying iommu_group
2198                  * further down to let iommu_add_device() do the job.
2199                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2200                  */
2201                 set_iommu_table_base(&pe->pdev->dev, tbl);
2202                 iommu_add_device(&pe->pdev->dev);
2203         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2204                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2205
2206         return;
2207  fail:
2208         /* XXX Failure: Try to fallback to 64-bit only ? */
2209         if (tce_mem)
2210                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2211         if (tbl) {
2212                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2213                 iommu_free_table(tbl, "pnv");
2214         }
2215 }
2216
2217 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2218                 int num, struct iommu_table *tbl)
2219 {
2220         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2221                         table_group);
2222         struct pnv_phb *phb = pe->phb;
2223         int64_t rc;
2224         const unsigned long size = tbl->it_indirect_levels ?
2225                         tbl->it_level_size : tbl->it_size;
2226         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2227         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2228
2229         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2230                         start_addr, start_addr + win_size - 1,
2231                         IOMMU_PAGE_SIZE(tbl));
2232
2233         /*
2234          * Map TCE table through TVT. The TVE index is the PE number
2235          * shifted by 1 bit for 32-bits DMA space.
2236          */
2237         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2238                         pe->pe_number,
2239                         (pe->pe_number << 1) + num,
2240                         tbl->it_indirect_levels + 1,
2241                         __pa(tbl->it_base),
2242                         size << 3,
2243                         IOMMU_PAGE_SIZE(tbl));
2244         if (rc) {
2245                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2246                 return rc;
2247         }
2248
2249         pnv_pci_link_table_and_group(phb->hose->node, num,
2250                         tbl, &pe->table_group);
2251         pnv_pci_ioda2_tce_invalidate_pe(pe);
2252
2253         return 0;
2254 }
2255
2256 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2257 {
2258         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2259         int64_t rc;
2260
2261         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2262         if (enable) {
2263                 phys_addr_t top = memblock_end_of_DRAM();
2264
2265                 top = roundup_pow_of_two(top);
2266                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2267                                                      pe->pe_number,
2268                                                      window_id,
2269                                                      pe->tce_bypass_base,
2270                                                      top);
2271         } else {
2272                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2273                                                      pe->pe_number,
2274                                                      window_id,
2275                                                      pe->tce_bypass_base,
2276                                                      0);
2277         }
2278         if (rc)
2279                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2280         else
2281                 pe->tce_bypass_enabled = enable;
2282 }
2283
2284 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2285                 __u32 page_shift, __u64 window_size, __u32 levels,
2286                 struct iommu_table *tbl);
2287
2288 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2289                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2290                 struct iommu_table **ptbl)
2291 {
2292         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2293                         table_group);
2294         int nid = pe->phb->hose->node;
2295         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2296         long ret;
2297         struct iommu_table *tbl;
2298
2299         tbl = pnv_pci_table_alloc(nid);
2300         if (!tbl)
2301                 return -ENOMEM;
2302
2303         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2304                         bus_offset, page_shift, window_size,
2305                         levels, tbl);
2306         if (ret) {
2307                 iommu_free_table(tbl, "pnv");
2308                 return ret;
2309         }
2310
2311         tbl->it_ops = &pnv_ioda2_iommu_ops;
2312
2313         *ptbl = tbl;
2314
2315         return 0;
2316 }
2317
2318 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2319 {
2320         struct iommu_table *tbl = NULL;
2321         long rc;
2322
2323         /*
2324          * crashkernel= specifies the kdump kernel's maximum memory at
2325          * some offset and there is no guaranteed the result is a power
2326          * of 2, which will cause errors later.
2327          */
2328         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2329
2330         /*
2331          * In memory constrained environments, e.g. kdump kernel, the
2332          * DMA window can be larger than available memory, which will
2333          * cause errors later.
2334          */
2335         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2336
2337         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2338                         IOMMU_PAGE_SHIFT_4K,
2339                         window_size,
2340                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2341         if (rc) {
2342                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2343                                 rc);
2344                 return rc;
2345         }
2346
2347         iommu_init_table(tbl, pe->phb->hose->node);
2348
2349         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2350         if (rc) {
2351                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2352                                 rc);
2353                 pnv_ioda2_table_free(tbl);
2354                 return rc;
2355         }
2356
2357         if (!pnv_iommu_bypass_disabled)
2358                 pnv_pci_ioda2_set_bypass(pe, true);
2359
2360         /*
2361          * Setting table base here only for carrying iommu_group
2362          * further down to let iommu_add_device() do the job.
2363          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2364          */
2365         if (pe->flags & PNV_IODA_PE_DEV)
2366                 set_iommu_table_base(&pe->pdev->dev, tbl);
2367
2368         return 0;
2369 }
2370
2371 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2372 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2373                 int num)
2374 {
2375         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2376                         table_group);
2377         struct pnv_phb *phb = pe->phb;
2378         long ret;
2379
2380         pe_info(pe, "Removing DMA window #%d\n", num);
2381
2382         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2383                         (pe->pe_number << 1) + num,
2384                         0/* levels */, 0/* table address */,
2385                         0/* table size */, 0/* page size */);
2386         if (ret)
2387                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2388         else
2389                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2390
2391         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2392
2393         return ret;
2394 }
2395 #endif
2396
2397 #ifdef CONFIG_IOMMU_API
2398 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2399                 __u64 window_size, __u32 levels)
2400 {
2401         unsigned long bytes = 0;
2402         const unsigned window_shift = ilog2(window_size);
2403         unsigned entries_shift = window_shift - page_shift;
2404         unsigned table_shift = entries_shift + 3;
2405         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2406         unsigned long direct_table_size;
2407
2408         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2409                         (window_size > memory_hotplug_max()) ||
2410                         !is_power_of_2(window_size))
2411                 return 0;
2412
2413         /* Calculate a direct table size from window_size and levels */
2414         entries_shift = (entries_shift + levels - 1) / levels;
2415         table_shift = entries_shift + 3;
2416         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2417         direct_table_size =  1UL << table_shift;
2418
2419         for ( ; levels; --levels) {
2420                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2421
2422                 tce_table_size /= direct_table_size;
2423                 tce_table_size <<= 3;
2424                 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2425         }
2426
2427         return bytes;
2428 }
2429
2430 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2431 {
2432         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2433                                                 table_group);
2434         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2435         struct iommu_table *tbl = pe->table_group.tables[0];
2436
2437         pnv_pci_ioda2_set_bypass(pe, false);
2438         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2439         pnv_ioda2_table_free(tbl);
2440 }
2441
2442 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2443 {
2444         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2445                                                 table_group);
2446
2447         pnv_pci_ioda2_setup_default_config(pe);
2448 }
2449
2450 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2451         .get_table_size = pnv_pci_ioda2_get_table_size,
2452         .create_table = pnv_pci_ioda2_create_table,
2453         .set_window = pnv_pci_ioda2_set_window,
2454         .unset_window = pnv_pci_ioda2_unset_window,
2455         .take_ownership = pnv_ioda2_take_ownership,
2456         .release_ownership = pnv_ioda2_release_ownership,
2457 };
2458
2459 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2460 {
2461         struct pci_controller *hose;
2462         struct pnv_phb *phb;
2463         struct pnv_ioda_pe **ptmppe = opaque;
2464         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2465         struct pci_dn *pdn = pci_get_pdn(pdev);
2466
2467         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2468                 return 0;
2469
2470         hose = pci_bus_to_host(pdev->bus);
2471         phb = hose->private_data;
2472         if (phb->type != PNV_PHB_NPU)
2473                 return 0;
2474
2475         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2476
2477         return 1;
2478 }
2479
2480 /*
2481  * This returns PE of associated NPU.
2482  * This assumes that NPU is in the same IOMMU group with GPU and there is
2483  * no other PEs.
2484  */
2485 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2486                 struct iommu_table_group *table_group)
2487 {
2488         struct pnv_ioda_pe *npe = NULL;
2489         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2490                         gpe_table_group_to_npe_cb);
2491
2492         BUG_ON(!ret || !npe);
2493
2494         return npe;
2495 }
2496
2497 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2498                 int num, struct iommu_table *tbl)
2499 {
2500         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2501
2502         if (ret)
2503                 return ret;
2504
2505         ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2506         if (ret)
2507                 pnv_pci_ioda2_unset_window(table_group, num);
2508
2509         return ret;
2510 }
2511
2512 static long pnv_pci_ioda2_npu_unset_window(
2513                 struct iommu_table_group *table_group,
2514                 int num)
2515 {
2516         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2517
2518         if (ret)
2519                 return ret;
2520
2521         return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2522 }
2523
2524 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2525 {
2526         /*
2527          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2528          * the iommu_table if 32bit DMA is enabled.
2529          */
2530         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2531         pnv_ioda2_take_ownership(table_group);
2532 }
2533
2534 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2535         .get_table_size = pnv_pci_ioda2_get_table_size,
2536         .create_table = pnv_pci_ioda2_create_table,
2537         .set_window = pnv_pci_ioda2_npu_set_window,
2538         .unset_window = pnv_pci_ioda2_npu_unset_window,
2539         .take_ownership = pnv_ioda2_npu_take_ownership,
2540         .release_ownership = pnv_ioda2_release_ownership,
2541 };
2542
2543 static void pnv_pci_ioda_setup_iommu_api(void)
2544 {
2545         struct pci_controller *hose, *tmp;
2546         struct pnv_phb *phb;
2547         struct pnv_ioda_pe *pe, *gpe;
2548
2549         /*
2550          * Now we have all PHBs discovered, time to add NPU devices to
2551          * the corresponding IOMMU groups.
2552          */
2553         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2554                 phb = hose->private_data;
2555
2556                 if (phb->type != PNV_PHB_NPU)
2557                         continue;
2558
2559                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2560                         gpe = pnv_pci_npu_setup_iommu(pe);
2561                         if (gpe)
2562                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2563                 }
2564         }
2565 }
2566 #else /* !CONFIG_IOMMU_API */
2567 static void pnv_pci_ioda_setup_iommu_api(void) { };
2568 #endif
2569
2570 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2571                 unsigned levels, unsigned long limit,
2572                 unsigned long *current_offset, unsigned long *total_allocated)
2573 {
2574         struct page *tce_mem = NULL;
2575         __be64 *addr, *tmp;
2576         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2577         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2578         unsigned entries = 1UL << (shift - 3);
2579         long i;
2580
2581         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2582         if (!tce_mem) {
2583                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2584                 return NULL;
2585         }
2586         addr = page_address(tce_mem);
2587         memset(addr, 0, allocated);
2588         *total_allocated += allocated;
2589
2590         --levels;
2591         if (!levels) {
2592                 *current_offset += allocated;
2593                 return addr;
2594         }
2595
2596         for (i = 0; i < entries; ++i) {
2597                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2598                                 levels, limit, current_offset, total_allocated);
2599                 if (!tmp)
2600                         break;
2601
2602                 addr[i] = cpu_to_be64(__pa(tmp) |
2603                                 TCE_PCI_READ | TCE_PCI_WRITE);
2604
2605                 if (*current_offset >= limit)
2606                         break;
2607         }
2608
2609         return addr;
2610 }
2611
2612 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2613                 unsigned long size, unsigned level);
2614
2615 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2616                 __u32 page_shift, __u64 window_size, __u32 levels,
2617                 struct iommu_table *tbl)
2618 {
2619         void *addr;
2620         unsigned long offset = 0, level_shift, total_allocated = 0;
2621         const unsigned window_shift = ilog2(window_size);
2622         unsigned entries_shift = window_shift - page_shift;
2623         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2624         const unsigned long tce_table_size = 1UL << table_shift;
2625
2626         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2627                 return -EINVAL;
2628
2629         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2630                 return -EINVAL;
2631
2632         /* Adjust direct table size from window_size and levels */
2633         entries_shift = (entries_shift + levels - 1) / levels;
2634         level_shift = entries_shift + 3;
2635         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2636
2637         if ((level_shift - 3) * levels + page_shift >= 55)
2638                 return -EINVAL;
2639
2640         /* Allocate TCE table */
2641         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2642                         levels, tce_table_size, &offset, &total_allocated);
2643
2644         /* addr==NULL means that the first level allocation failed */
2645         if (!addr)
2646                 return -ENOMEM;
2647
2648         /*
2649          * First level was allocated but some lower level failed as
2650          * we did not allocate as much as we wanted,
2651          * release partially allocated table.
2652          */
2653         if (offset < tce_table_size) {
2654                 pnv_pci_ioda2_table_do_free_pages(addr,
2655                                 1ULL << (level_shift - 3), levels - 1);
2656                 return -ENOMEM;
2657         }
2658
2659         /* Setup linux iommu table */
2660         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2661                         page_shift);
2662         tbl->it_level_size = 1ULL << (level_shift - 3);
2663         tbl->it_indirect_levels = levels - 1;
2664         tbl->it_allocated_size = total_allocated;
2665
2666         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2667                         window_size, tce_table_size, bus_offset);
2668
2669         return 0;
2670 }
2671
2672 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2673                 unsigned long size, unsigned level)
2674 {
2675         const unsigned long addr_ul = (unsigned long) addr &
2676                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2677
2678         if (level) {
2679                 long i;
2680                 u64 *tmp = (u64 *) addr_ul;
2681
2682                 for (i = 0; i < size; ++i) {
2683                         unsigned long hpa = be64_to_cpu(tmp[i]);
2684
2685                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2686                                 continue;
2687
2688                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2689                                         level - 1);
2690                 }
2691         }
2692
2693         free_pages(addr_ul, get_order(size << 3));
2694 }
2695
2696 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2697 {
2698         const unsigned long size = tbl->it_indirect_levels ?
2699                         tbl->it_level_size : tbl->it_size;
2700
2701         if (!tbl->it_size)
2702                 return;
2703
2704         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2705                         tbl->it_indirect_levels);
2706 }
2707
2708 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2709                                        struct pnv_ioda_pe *pe)
2710 {
2711         int64_t rc;
2712
2713         if (!pnv_pci_ioda_pe_dma_weight(pe))
2714                 return;
2715
2716         /* TVE #1 is selected by PCI address bit 59 */
2717         pe->tce_bypass_base = 1ull << 59;
2718
2719         iommu_register_group(&pe->table_group, phb->hose->global_number,
2720                         pe->pe_number);
2721
2722         /* The PE will reserve all possible 32-bits space */
2723         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2724                 phb->ioda.m32_pci_base);
2725
2726         /* Setup linux iommu table */
2727         pe->table_group.tce32_start = 0;
2728         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2729         pe->table_group.max_dynamic_windows_supported =
2730                         IOMMU_TABLE_GROUP_MAX_TABLES;
2731         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2732         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2733 #ifdef CONFIG_IOMMU_API
2734         pe->table_group.ops = &pnv_pci_ioda2_ops;
2735 #endif
2736
2737         rc = pnv_pci_ioda2_setup_default_config(pe);
2738         if (rc)
2739                 return;
2740
2741         if (pe->flags & PNV_IODA_PE_DEV)
2742                 iommu_add_device(&pe->pdev->dev);
2743         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2744                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2745 }
2746
2747 #ifdef CONFIG_PCI_MSI
2748 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2749 {
2750         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2751                                            ioda.irq_chip);
2752
2753         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2754 }
2755
2756 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2757 {
2758         int64_t rc;
2759         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2760         struct irq_chip *chip = irq_data_get_irq_chip(d);
2761
2762         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2763         WARN_ON_ONCE(rc);
2764
2765         icp_native_eoi(d);
2766 }
2767
2768
2769 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2770 {
2771         struct irq_data *idata;
2772         struct irq_chip *ichip;
2773
2774         /* The MSI EOI OPAL call is only needed on PHB3 */
2775         if (phb->model != PNV_PHB_MODEL_PHB3)
2776                 return;
2777
2778         if (!phb->ioda.irq_chip_init) {
2779                 /*
2780                  * First time we setup an MSI IRQ, we need to setup the
2781                  * corresponding IRQ chip to route correctly.
2782                  */
2783                 idata = irq_get_irq_data(virq);
2784                 ichip = irq_data_get_irq_chip(idata);
2785                 phb->ioda.irq_chip_init = 1;
2786                 phb->ioda.irq_chip = *ichip;
2787                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2788         }
2789         irq_set_chip(virq, &phb->ioda.irq_chip);
2790 }
2791
2792 /*
2793  * Returns true iff chip is something that we could call
2794  * pnv_opal_pci_msi_eoi for.
2795  */
2796 bool is_pnv_opal_msi(struct irq_chip *chip)
2797 {
2798         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2799 }
2800 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2801
2802 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2803                                   unsigned int hwirq, unsigned int virq,
2804                                   unsigned int is_64, struct msi_msg *msg)
2805 {
2806         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2807         unsigned int xive_num = hwirq - phb->msi_base;
2808         __be32 data;
2809         int rc;
2810
2811         /* No PE assigned ? bail out ... no MSI for you ! */
2812         if (pe == NULL)
2813                 return -ENXIO;
2814
2815         /* Check if we have an MVE */
2816         if (pe->mve_number < 0)
2817                 return -ENXIO;
2818
2819         /* Force 32-bit MSI on some broken devices */
2820         if (dev->no_64bit_msi)
2821                 is_64 = 0;
2822
2823         /* Assign XIVE to PE */
2824         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2825         if (rc) {
2826                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2827                         pci_name(dev), rc, xive_num);
2828                 return -EIO;
2829         }
2830
2831         if (is_64) {
2832                 __be64 addr64;
2833
2834                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2835                                      &addr64, &data);
2836                 if (rc) {
2837                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2838                                 pci_name(dev), rc);
2839                         return -EIO;
2840                 }
2841                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2842                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2843         } else {
2844                 __be32 addr32;
2845
2846                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2847                                      &addr32, &data);
2848                 if (rc) {
2849                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2850                                 pci_name(dev), rc);
2851                         return -EIO;
2852                 }
2853                 msg->address_hi = 0;
2854                 msg->address_lo = be32_to_cpu(addr32);
2855         }
2856         msg->data = be32_to_cpu(data);
2857
2858         pnv_set_msi_irq_chip(phb, virq);
2859
2860         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2861                  " address=%x_%08x data=%x PE# %d\n",
2862                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2863                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2864
2865         return 0;
2866 }
2867
2868 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2869 {
2870         unsigned int count;
2871         const __be32 *prop = of_get_property(phb->hose->dn,
2872                                              "ibm,opal-msi-ranges", NULL);
2873         if (!prop) {
2874                 /* BML Fallback */
2875                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2876         }
2877         if (!prop)
2878                 return;
2879
2880         phb->msi_base = be32_to_cpup(prop);
2881         count = be32_to_cpup(prop + 1);
2882         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2883                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2884                        phb->hose->global_number);
2885                 return;
2886         }
2887
2888         phb->msi_setup = pnv_pci_ioda_msi_setup;
2889         phb->msi32_support = 1;
2890         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2891                 count, phb->msi_base);
2892 }
2893 #else
2894 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2895 #endif /* CONFIG_PCI_MSI */
2896
2897 #ifdef CONFIG_PCI_IOV
2898 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2899 {
2900         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2901         struct pnv_phb *phb = hose->private_data;
2902         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2903         struct resource *res;
2904         int i;
2905         resource_size_t size, total_vf_bar_sz;
2906         struct pci_dn *pdn;
2907         int mul, total_vfs;
2908
2909         if (!pdev->is_physfn || pdev->is_added)
2910                 return;
2911
2912         pdn = pci_get_pdn(pdev);
2913         pdn->vfs_expanded = 0;
2914         pdn->m64_single_mode = false;
2915
2916         total_vfs = pci_sriov_get_totalvfs(pdev);
2917         mul = phb->ioda.total_pe_num;
2918         total_vf_bar_sz = 0;
2919
2920         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2921                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2922                 if (!res->flags || res->parent)
2923                         continue;
2924                 if (!pnv_pci_is_m64_flags(res->flags)) {
2925                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2926                                         " non M64 VF BAR%d: %pR. \n",
2927                                  i, res);
2928                         goto truncate_iov;
2929                 }
2930
2931                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2932                                 i + PCI_IOV_RESOURCES);
2933
2934                 /*
2935                  * If bigger than quarter of M64 segment size, just round up
2936                  * power of two.
2937                  *
2938                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2939                  * with other devices, IOV BAR size is expanded to be
2940                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2941                  * segment size , the expanded size would equal to half of the
2942                  * whole M64 space size, which will exhaust the M64 Space and
2943                  * limit the system flexibility.  This is a design decision to
2944                  * set the boundary to quarter of the M64 segment size.
2945                  */
2946                 if (total_vf_bar_sz > gate) {
2947                         mul = roundup_pow_of_two(total_vfs);
2948                         dev_info(&pdev->dev,
2949                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2950                                 total_vf_bar_sz, gate, mul);
2951                         pdn->m64_single_mode = true;
2952                         break;
2953                 }
2954         }
2955
2956         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2957                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2958                 if (!res->flags || res->parent)
2959                         continue;
2960
2961                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2962                 /*
2963                  * On PHB3, the minimum size alignment of M64 BAR in single
2964                  * mode is 32MB.
2965                  */
2966                 if (pdn->m64_single_mode && (size < SZ_32M))
2967                         goto truncate_iov;
2968                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2969                 res->end = res->start + size * mul - 1;
2970                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2971                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2972                          i, res, mul);
2973         }
2974         pdn->vfs_expanded = mul;
2975
2976         return;
2977
2978 truncate_iov:
2979         /* To save MMIO space, IOV BAR is truncated. */
2980         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2981                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2982                 res->flags = 0;
2983                 res->end = res->start - 1;
2984         }
2985 }
2986 #endif /* CONFIG_PCI_IOV */
2987
2988 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2989                                   struct resource *res)
2990 {
2991         struct pnv_phb *phb = pe->phb;
2992         struct pci_bus_region region;
2993         int index;
2994         int64_t rc;
2995
2996         if (!res || !res->flags || res->start > res->end)
2997                 return;
2998
2999         if (res->flags & IORESOURCE_IO) {
3000                 region.start = res->start - phb->ioda.io_pci_base;
3001                 region.end   = res->end - phb->ioda.io_pci_base;
3002                 index = region.start / phb->ioda.io_segsize;
3003
3004                 while (index < phb->ioda.total_pe_num &&
3005                        region.start <= region.end) {
3006                         phb->ioda.io_segmap[index] = pe->pe_number;
3007                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3008                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3009                         if (rc != OPAL_SUCCESS) {
3010                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
3011                                        __func__, rc, index, pe->pe_number);
3012                                 break;
3013                         }
3014
3015                         region.start += phb->ioda.io_segsize;
3016                         index++;
3017                 }
3018         } else if ((res->flags & IORESOURCE_MEM) &&
3019                    !pnv_pci_is_m64(phb, res)) {
3020                 region.start = res->start -
3021                                phb->hose->mem_offset[0] -
3022                                phb->ioda.m32_pci_base;
3023                 region.end   = res->end -
3024                                phb->hose->mem_offset[0] -
3025                                phb->ioda.m32_pci_base;
3026                 index = region.start / phb->ioda.m32_segsize;
3027
3028                 while (index < phb->ioda.total_pe_num &&
3029                        region.start <= region.end) {
3030                         phb->ioda.m32_segmap[index] = pe->pe_number;
3031                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3032                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3033                         if (rc != OPAL_SUCCESS) {
3034                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
3035                                        __func__, rc, index, pe->pe_number);
3036                                 break;
3037                         }
3038
3039                         region.start += phb->ioda.m32_segsize;
3040                         index++;
3041                 }
3042         }
3043 }
3044
3045 /*
3046  * This function is supposed to be called on basis of PE from top
3047  * to bottom style. So the the I/O or MMIO segment assigned to
3048  * parent PE could be overrided by its child PEs if necessary.
3049  */
3050 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3051 {
3052         struct pci_dev *pdev;
3053         int i;
3054
3055         /*
3056          * NOTE: We only care PCI bus based PE for now. For PCI
3057          * device based PE, for example SRIOV sensitive VF should
3058          * be figured out later.
3059          */
3060         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3061
3062         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3063                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3064                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3065
3066                 /*
3067                  * If the PE contains all subordinate PCI buses, the
3068                  * windows of the child bridges should be mapped to
3069                  * the PE as well.
3070                  */
3071                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3072                         continue;
3073                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3074                         pnv_ioda_setup_pe_res(pe,
3075                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3076         }
3077 }
3078
3079 #ifdef CONFIG_DEBUG_FS
3080 static int pnv_pci_diag_data_set(void *data, u64 val)
3081 {
3082         struct pci_controller *hose;
3083         struct pnv_phb *phb;
3084         s64 ret;
3085
3086         if (val != 1ULL)
3087                 return -EINVAL;
3088
3089         hose = (struct pci_controller *)data;
3090         if (!hose || !hose->private_data)
3091                 return -ENODEV;
3092
3093         phb = hose->private_data;
3094
3095         /* Retrieve the diag data from firmware */
3096         ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
3097                                           PNV_PCI_DIAG_BUF_SIZE);
3098         if (ret != OPAL_SUCCESS)
3099                 return -EIO;
3100
3101         /* Print the diag data to the kernel log */
3102         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
3103         return 0;
3104 }
3105
3106 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3107                         pnv_pci_diag_data_set, "%llu\n");
3108
3109 #endif /* CONFIG_DEBUG_FS */
3110
3111 static void pnv_pci_ioda_create_dbgfs(void)
3112 {
3113 #ifdef CONFIG_DEBUG_FS
3114         struct pci_controller *hose, *tmp;
3115         struct pnv_phb *phb;
3116         char name[16];
3117
3118         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3119                 phb = hose->private_data;
3120
3121                 /* Notify initialization of PHB done */
3122                 phb->initialized = 1;
3123
3124                 sprintf(name, "PCI%04x", hose->global_number);
3125                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3126                 if (!phb->dbgfs) {
3127                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3128                                 __func__, hose->global_number);
3129                         continue;
3130                 }
3131
3132                 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3133                                     &pnv_pci_diag_data_fops);
3134         }
3135 #endif /* CONFIG_DEBUG_FS */
3136 }
3137
3138 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3139 {
3140         struct pci_dev *dev = bus->self;
3141         struct pci_bus *child;
3142
3143         /* Empty bus ? bail */
3144         if (list_empty(&bus->devices))
3145                 return;
3146
3147         /*
3148          * If there's a bridge associated with that bus enable it. This works
3149          * around races in the generic code if the enabling is done during
3150          * parallel probing. This can be removed once those races have been
3151          * fixed.
3152          */
3153         if (dev) {
3154                 int rc = pci_enable_device(dev);
3155                 if (rc)
3156                         pci_err(dev, "Error enabling bridge (%d)\n", rc);
3157                 pci_set_master(dev);
3158         }
3159
3160         /* Perform the same to child busses */
3161         list_for_each_entry(child, &bus->children, node)
3162                 pnv_pci_enable_bridge(child);
3163 }
3164
3165 static void pnv_pci_enable_bridges(void)
3166 {
3167         struct pci_controller *hose;
3168
3169         list_for_each_entry(hose, &hose_list, list_node)
3170                 pnv_pci_enable_bridge(hose->bus);
3171 }
3172
3173 static void pnv_pci_ioda_fixup(void)
3174 {
3175         pnv_pci_ioda_setup_PEs();
3176         pnv_pci_ioda_setup_iommu_api();
3177         pnv_pci_ioda_create_dbgfs();
3178
3179         pnv_pci_enable_bridges();
3180
3181 #ifdef CONFIG_EEH
3182         eeh_init();
3183         eeh_addr_cache_build();
3184 #endif
3185 }
3186
3187 /*
3188  * Returns the alignment for I/O or memory windows for P2P
3189  * bridges. That actually depends on how PEs are segmented.
3190  * For now, we return I/O or M32 segment size for PE sensitive
3191  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3192  * 1MiB for memory) will be returned.
3193  *
3194  * The current PCI bus might be put into one PE, which was
3195  * create against the parent PCI bridge. For that case, we
3196  * needn't enlarge the alignment so that we can save some
3197  * resources.
3198  */
3199 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3200                                                 unsigned long type)
3201 {
3202         struct pci_dev *bridge;
3203         struct pci_controller *hose = pci_bus_to_host(bus);
3204         struct pnv_phb *phb = hose->private_data;
3205         int num_pci_bridges = 0;
3206
3207         bridge = bus->self;
3208         while (bridge) {
3209                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3210                         num_pci_bridges++;
3211                         if (num_pci_bridges >= 2)
3212                                 return 1;
3213                 }
3214
3215                 bridge = bridge->bus->self;
3216         }
3217
3218         /*
3219          * We fall back to M32 if M64 isn't supported. We enforce the M64
3220          * alignment for any 64-bit resource, PCIe doesn't care and
3221          * bridges only do 64-bit prefetchable anyway.
3222          */
3223         if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3224                 return phb->ioda.m64_segsize;
3225         if (type & IORESOURCE_MEM)
3226                 return phb->ioda.m32_segsize;
3227
3228         return phb->ioda.io_segsize;
3229 }
3230
3231 /*
3232  * We are updating root port or the upstream port of the
3233  * bridge behind the root port with PHB's windows in order
3234  * to accommodate the changes on required resources during
3235  * PCI (slot) hotplug, which is connected to either root
3236  * port or the downstream ports of PCIe switch behind the
3237  * root port.
3238  */
3239 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3240                                            unsigned long type)
3241 {
3242         struct pci_controller *hose = pci_bus_to_host(bus);
3243         struct pnv_phb *phb = hose->private_data;
3244         struct pci_dev *bridge = bus->self;
3245         struct resource *r, *w;
3246         bool msi_region = false;
3247         int i;
3248
3249         /* Check if we need apply fixup to the bridge's windows */
3250         if (!pci_is_root_bus(bridge->bus) &&
3251             !pci_is_root_bus(bridge->bus->self->bus))
3252                 return;
3253
3254         /* Fixup the resources */
3255         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3256                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3257                 if (!r->flags || !r->parent)
3258                         continue;
3259
3260                 w = NULL;
3261                 if (r->flags & type & IORESOURCE_IO)
3262                         w = &hose->io_resource;
3263                 else if (pnv_pci_is_m64(phb, r) &&
3264                          (type & IORESOURCE_PREFETCH) &&
3265                          phb->ioda.m64_segsize)
3266                         w = &hose->mem_resources[1];
3267                 else if (r->flags & type & IORESOURCE_MEM) {
3268                         w = &hose->mem_resources[0];
3269                         msi_region = true;
3270                 }
3271
3272                 r->start = w->start;
3273                 r->end = w->end;
3274
3275                 /* The 64KB 32-bits MSI region shouldn't be included in
3276                  * the 32-bits bridge window. Otherwise, we can see strange
3277                  * issues. One of them is EEH error observed on Garrison.
3278                  *
3279                  * Exclude top 1MB region which is the minimal alignment of
3280                  * 32-bits bridge window.
3281                  */
3282                 if (msi_region) {
3283                         r->end += 0x10000;
3284                         r->end -= 0x100000;
3285                 }
3286         }
3287 }
3288
3289 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3290 {
3291         struct pci_controller *hose = pci_bus_to_host(bus);
3292         struct pnv_phb *phb = hose->private_data;
3293         struct pci_dev *bridge = bus->self;
3294         struct pnv_ioda_pe *pe;
3295         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3296
3297         /* Extend bridge's windows if necessary */
3298         pnv_pci_fixup_bridge_resources(bus, type);
3299
3300         /* The PE for root bus should be realized before any one else */
3301         if (!phb->ioda.root_pe_populated) {
3302                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3303                 if (pe) {
3304                         phb->ioda.root_pe_idx = pe->pe_number;
3305                         phb->ioda.root_pe_populated = true;
3306                 }
3307         }
3308
3309         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3310         if (list_empty(&bus->devices))
3311                 return;
3312
3313         /* Reserve PEs according to used M64 resources */
3314         if (phb->reserve_m64_pe)
3315                 phb->reserve_m64_pe(bus, NULL, all);
3316
3317         /*
3318          * Assign PE. We might run here because of partial hotplug.
3319          * For the case, we just pick up the existing PE and should
3320          * not allocate resources again.
3321          */
3322         pe = pnv_ioda_setup_bus_PE(bus, all);
3323         if (!pe)
3324                 return;
3325
3326         pnv_ioda_setup_pe_seg(pe);
3327         switch (phb->type) {
3328         case PNV_PHB_IODA1:
3329                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3330                 break;
3331         case PNV_PHB_IODA2:
3332                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3333                 break;
3334         default:
3335                 pr_warn("%s: No DMA for PHB#%d (type %d)\n",
3336                         __func__, phb->hose->global_number, phb->type);
3337         }
3338 }
3339
3340 #ifdef CONFIG_PCI_IOV
3341 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3342                                                       int resno)
3343 {
3344         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3345         struct pnv_phb *phb = hose->private_data;
3346         struct pci_dn *pdn = pci_get_pdn(pdev);
3347         resource_size_t align;
3348
3349         /*
3350          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3351          * SR-IOV. While from hardware perspective, the range mapped by M64
3352          * BAR should be size aligned.
3353          *
3354          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3355          * powernv-specific hardware restriction is gone. But if just use the
3356          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3357          * in one segment of M64 #15, which introduces the PE conflict between
3358          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3359          * m64_segsize.
3360          *
3361          * This function returns the total IOV BAR size if M64 BAR is in
3362          * Shared PE mode or just VF BAR size if not.
3363          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3364          * M64 segment size if IOV BAR size is less.
3365          */
3366         align = pci_iov_resource_size(pdev, resno);
3367         if (!pdn->vfs_expanded)
3368                 return align;
3369         if (pdn->m64_single_mode)
3370                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3371
3372         return pdn->vfs_expanded * align;
3373 }
3374 #endif /* CONFIG_PCI_IOV */
3375
3376 /* Prevent enabling devices for which we couldn't properly
3377  * assign a PE
3378  */
3379 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3380 {
3381         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3382         struct pnv_phb *phb = hose->private_data;
3383         struct pci_dn *pdn;
3384
3385         /* The function is probably called while the PEs have
3386          * not be created yet. For example, resource reassignment
3387          * during PCI probe period. We just skip the check if
3388          * PEs isn't ready.
3389          */
3390         if (!phb->initialized)
3391                 return true;
3392
3393         pdn = pci_get_pdn(dev);
3394         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3395                 return false;
3396
3397         return true;
3398 }
3399
3400 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3401                                        int num)
3402 {
3403         struct pnv_ioda_pe *pe = container_of(table_group,
3404                                               struct pnv_ioda_pe, table_group);
3405         struct pnv_phb *phb = pe->phb;
3406         unsigned int idx;
3407         long rc;
3408
3409         pe_info(pe, "Removing DMA window #%d\n", num);
3410         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3411                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3412                         continue;
3413
3414                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3415                                                 idx, 0, 0ul, 0ul, 0ul);
3416                 if (rc != OPAL_SUCCESS) {
3417                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3418                                 rc, idx);
3419                         return rc;
3420                 }
3421
3422                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3423         }
3424
3425         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3426         return OPAL_SUCCESS;
3427 }
3428
3429 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3430 {
3431         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3432         struct iommu_table *tbl = pe->table_group.tables[0];
3433         int64_t rc;
3434
3435         if (!weight)
3436                 return;
3437
3438         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3439         if (rc != OPAL_SUCCESS)
3440                 return;
3441
3442         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3443         if (pe->table_group.group) {
3444                 iommu_group_put(pe->table_group.group);
3445                 WARN_ON(pe->table_group.group);
3446         }
3447
3448         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3449         iommu_free_table(tbl, "pnv");
3450 }
3451
3452 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3453 {
3454         struct iommu_table *tbl = pe->table_group.tables[0];
3455         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3456 #ifdef CONFIG_IOMMU_API
3457         int64_t rc;
3458 #endif
3459
3460         if (!weight)
3461                 return;
3462
3463 #ifdef CONFIG_IOMMU_API
3464         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3465         if (rc)
3466                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3467 #endif
3468
3469         pnv_pci_ioda2_set_bypass(pe, false);
3470         if (pe->table_group.group) {
3471                 iommu_group_put(pe->table_group.group);
3472                 WARN_ON(pe->table_group.group);
3473         }
3474
3475         iommu_free_table(tbl, "pnv");
3476 }
3477
3478 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3479                                  unsigned short win,
3480                                  unsigned int *map)
3481 {
3482         struct pnv_phb *phb = pe->phb;
3483         int idx;
3484         int64_t rc;
3485
3486         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3487                 if (map[idx] != pe->pe_number)
3488                         continue;
3489
3490                 if (win == OPAL_M64_WINDOW_TYPE)
3491                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3492                                         phb->ioda.reserved_pe_idx, win,
3493                                         idx / PNV_IODA1_M64_SEGS,
3494                                         idx % PNV_IODA1_M64_SEGS);
3495                 else
3496                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3497                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3498
3499                 if (rc != OPAL_SUCCESS)
3500                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3501                                 rc, win, idx);
3502
3503                 map[idx] = IODA_INVALID_PE;
3504         }
3505 }
3506
3507 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3508 {
3509         struct pnv_phb *phb = pe->phb;
3510
3511         if (phb->type == PNV_PHB_IODA1) {
3512                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3513                                      phb->ioda.io_segmap);
3514                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3515                                      phb->ioda.m32_segmap);
3516                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3517                                      phb->ioda.m64_segmap);
3518         } else if (phb->type == PNV_PHB_IODA2) {
3519                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3520                                      phb->ioda.m32_segmap);
3521         }
3522 }
3523
3524 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3525 {
3526         struct pnv_phb *phb = pe->phb;
3527         struct pnv_ioda_pe *slave, *tmp;
3528
3529         list_del(&pe->list);
3530         switch (phb->type) {
3531         case PNV_PHB_IODA1:
3532                 pnv_pci_ioda1_release_pe_dma(pe);
3533                 break;
3534         case PNV_PHB_IODA2:
3535                 pnv_pci_ioda2_release_pe_dma(pe);
3536                 break;
3537         default:
3538                 WARN_ON(1);
3539         }
3540
3541         pnv_ioda_release_pe_seg(pe);
3542         pnv_ioda_deconfigure_pe(pe->phb, pe);
3543
3544         /* Release slave PEs in the compound PE */
3545         if (pe->flags & PNV_IODA_PE_MASTER) {
3546                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3547                         list_del(&slave->list);
3548                         pnv_ioda_free_pe(slave);
3549                 }
3550         }
3551
3552         /*
3553          * The PE for root bus can be removed because of hotplug in EEH
3554          * recovery for fenced PHB error. We need to mark the PE dead so
3555          * that it can be populated again in PCI hot add path. The PE
3556          * shouldn't be destroyed as it's the global reserved resource.
3557          */
3558         if (phb->ioda.root_pe_populated &&
3559             phb->ioda.root_pe_idx == pe->pe_number)
3560                 phb->ioda.root_pe_populated = false;
3561         else
3562                 pnv_ioda_free_pe(pe);
3563 }
3564
3565 static void pnv_pci_release_device(struct pci_dev *pdev)
3566 {
3567         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3568         struct pnv_phb *phb = hose->private_data;
3569         struct pci_dn *pdn = pci_get_pdn(pdev);
3570         struct pnv_ioda_pe *pe;
3571
3572         if (pdev->is_virtfn)
3573                 return;
3574
3575         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3576                 return;
3577
3578         /*
3579          * PCI hotplug can happen as part of EEH error recovery. The @pdn
3580          * isn't removed and added afterwards in this scenario. We should
3581          * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3582          * device count is decreased on removing devices while failing to
3583          * be increased on adding devices. It leads to unbalanced PE's device
3584          * count and eventually make normal PCI hotplug path broken.
3585          */
3586         pe = &phb->ioda.pe_array[pdn->pe_number];
3587         pdn->pe_number = IODA_INVALID_PE;
3588
3589         WARN_ON(--pe->device_count < 0);
3590         if (pe->device_count == 0)
3591                 pnv_ioda_release_pe(pe);
3592 }
3593
3594 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3595 {
3596         struct pnv_phb *phb = hose->private_data;
3597
3598         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3599                        OPAL_ASSERT_RESET);
3600 }
3601
3602 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3603         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3604         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3605 #ifdef CONFIG_PCI_MSI
3606         .setup_msi_irqs         = pnv_setup_msi_irqs,
3607         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3608 #endif
3609         .enable_device_hook     = pnv_pci_enable_device_hook,
3610         .release_device         = pnv_pci_release_device,
3611         .window_alignment       = pnv_pci_window_alignment,
3612         .setup_bridge           = pnv_pci_setup_bridge,
3613         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3614         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3615         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3616         .shutdown               = pnv_pci_ioda_shutdown,
3617 };
3618
3619 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3620 {
3621         dev_err_once(&npdev->dev,
3622                         "%s operation unsupported for NVLink devices\n",
3623                         __func__);
3624         return -EPERM;
3625 }
3626
3627 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3628         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3629 #ifdef CONFIG_PCI_MSI
3630         .setup_msi_irqs         = pnv_setup_msi_irqs,
3631         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3632 #endif
3633         .enable_device_hook     = pnv_pci_enable_device_hook,
3634         .window_alignment       = pnv_pci_window_alignment,
3635         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3636         .dma_set_mask           = pnv_npu_dma_set_mask,
3637         .shutdown               = pnv_pci_ioda_shutdown,
3638 };
3639
3640 #ifdef CONFIG_CXL_BASE
3641 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3642         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3643         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3644 #ifdef CONFIG_PCI_MSI
3645         .setup_msi_irqs         = pnv_cxl_cx4_setup_msi_irqs,
3646         .teardown_msi_irqs      = pnv_cxl_cx4_teardown_msi_irqs,
3647 #endif
3648         .enable_device_hook     = pnv_cxl_enable_device_hook,
3649         .disable_device         = pnv_cxl_disable_device,
3650         .release_device         = pnv_pci_release_device,
3651         .window_alignment       = pnv_pci_window_alignment,
3652         .setup_bridge           = pnv_pci_setup_bridge,
3653         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3654         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3655         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3656         .shutdown               = pnv_pci_ioda_shutdown,
3657 };
3658 #endif
3659
3660 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3661                                          u64 hub_id, int ioda_type)
3662 {
3663         struct pci_controller *hose;
3664         struct pnv_phb *phb;
3665         unsigned long size, m64map_off, m32map_off, pemap_off;
3666         unsigned long iomap_off = 0, dma32map_off = 0;
3667         struct resource r;
3668         const __be64 *prop64;
3669         const __be32 *prop32;
3670         int len;
3671         unsigned int segno;
3672         u64 phb_id;
3673         void *aux;
3674         long rc;
3675
3676         if (!of_device_is_available(np))
3677                 return;
3678
3679         pr_info("Initializing %s PHB (%s)\n",
3680                 pnv_phb_names[ioda_type], of_node_full_name(np));
3681
3682         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3683         if (!prop64) {
3684                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3685                 return;
3686         }
3687         phb_id = be64_to_cpup(prop64);
3688         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3689
3690         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3691
3692         /* Allocate PCI controller */
3693         phb->hose = hose = pcibios_alloc_controller(np);
3694         if (!phb->hose) {
3695                 pr_err("  Can't allocate PCI controller for %s\n",
3696                        np->full_name);
3697                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3698                 return;
3699         }
3700
3701         spin_lock_init(&phb->lock);
3702         prop32 = of_get_property(np, "bus-range", &len);
3703         if (prop32 && len == 8) {
3704                 hose->first_busno = be32_to_cpu(prop32[0]);
3705                 hose->last_busno = be32_to_cpu(prop32[1]);
3706         } else {
3707                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3708                 hose->first_busno = 0;
3709                 hose->last_busno = 0xff;
3710         }
3711         hose->private_data = phb;
3712         phb->hub_id = hub_id;
3713         phb->opal_id = phb_id;
3714         phb->type = ioda_type;
3715         mutex_init(&phb->ioda.pe_alloc_mutex);
3716
3717         /* Detect specific models for error handling */
3718         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3719                 phb->model = PNV_PHB_MODEL_P7IOC;
3720         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3721                 phb->model = PNV_PHB_MODEL_PHB3;
3722         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3723                 phb->model = PNV_PHB_MODEL_NPU;
3724         else
3725                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3726
3727         /* Parse 32-bit and IO ranges (if any) */
3728         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3729
3730         /* Get registers */
3731         if (!of_address_to_resource(np, 0, &r)) {
3732                 phb->regs_phys = r.start;
3733                 phb->regs = ioremap(r.start, resource_size(&r));
3734                 if (phb->regs == NULL)
3735                         pr_err("  Failed to map registers !\n");
3736         }
3737
3738         /* Initialize more IODA stuff */
3739         phb->ioda.total_pe_num = 1;
3740         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3741         if (prop32)
3742                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3743         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3744         if (prop32)
3745                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3746
3747         /* Invalidate RID to PE# mapping */
3748         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3749                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3750
3751         /* Parse 64-bit MMIO range */
3752         pnv_ioda_parse_m64_window(phb);
3753
3754         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3755         /* FW Has already off top 64k of M32 space (MSI space) */
3756         phb->ioda.m32_size += 0x10000;
3757
3758         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3759         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3760         phb->ioda.io_size = hose->pci_io_size;
3761         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3762         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3763
3764         /* Calculate how many 32-bit TCE segments we have */
3765         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3766                                 PNV_IODA1_DMA32_SEGSIZE;
3767
3768         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3769         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3770                         sizeof(unsigned long));
3771         m64map_off = size;
3772         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3773         m32map_off = size;
3774         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3775         if (phb->type == PNV_PHB_IODA1) {
3776                 iomap_off = size;
3777                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3778                 dma32map_off = size;
3779                 size += phb->ioda.dma32_count *
3780                         sizeof(phb->ioda.dma32_segmap[0]);
3781         }
3782         pemap_off = size;
3783         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3784         aux = memblock_virt_alloc(size, 0);
3785         phb->ioda.pe_alloc = aux;
3786         phb->ioda.m64_segmap = aux + m64map_off;
3787         phb->ioda.m32_segmap = aux + m32map_off;
3788         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3789                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3790                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3791         }
3792         if (phb->type == PNV_PHB_IODA1) {
3793                 phb->ioda.io_segmap = aux + iomap_off;
3794                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3795                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3796
3797                 phb->ioda.dma32_segmap = aux + dma32map_off;
3798                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3799                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3800         }
3801         phb->ioda.pe_array = aux + pemap_off;
3802
3803         /*
3804          * Choose PE number for root bus, which shouldn't have
3805          * M64 resources consumed by its child devices. To pick
3806          * the PE number adjacent to the reserved one if possible.
3807          */
3808         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3809         if (phb->ioda.reserved_pe_idx == 0) {
3810                 phb->ioda.root_pe_idx = 1;
3811                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3812         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3813                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3814                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3815         } else {
3816                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3817         }
3818
3819         INIT_LIST_HEAD(&phb->ioda.pe_list);
3820         mutex_init(&phb->ioda.pe_list_mutex);
3821
3822         /* Calculate how many 32-bit TCE segments we have */
3823         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3824                                 PNV_IODA1_DMA32_SEGSIZE;
3825
3826 #if 0 /* We should really do that ... */
3827         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3828                                          window_type,
3829                                          window_num,
3830                                          starting_real_address,
3831                                          starting_pci_address,
3832                                          segment_size);
3833 #endif
3834
3835         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3836                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3837                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3838         if (phb->ioda.m64_size)
3839                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3840                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3841         if (phb->ioda.io_size)
3842                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3843                         phb->ioda.io_size, phb->ioda.io_segsize);
3844
3845
3846         phb->hose->ops = &pnv_pci_ops;
3847         phb->get_pe_state = pnv_ioda_get_pe_state;
3848         phb->freeze_pe = pnv_ioda_freeze_pe;
3849         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3850
3851         /* Setup MSI support */
3852         pnv_pci_init_ioda_msis(phb);
3853
3854         /*
3855          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3856          * to let the PCI core do resource assignment. It's supposed
3857          * that the PCI core will do correct I/O and MMIO alignment
3858          * for the P2P bridge bars so that each PCI bus (excluding
3859          * the child P2P bridges) can form individual PE.
3860          */
3861         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3862
3863         if (phb->type == PNV_PHB_NPU) {
3864                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3865         } else {
3866                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3867                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3868         }
3869
3870 #ifdef CONFIG_PCI_IOV
3871         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3872         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3873 #endif
3874
3875         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3876
3877         /* Reset IODA tables to a clean state */
3878         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3879         if (rc)
3880                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3881
3882         /*
3883          * If we're running in kdump kernel, the previous kernel never
3884          * shutdown PCI devices correctly. We already got IODA table
3885          * cleaned out. So we have to issue PHB reset to stop all PCI
3886          * transactions from previous kernel.
3887          */
3888         if (is_kdump_kernel()) {
3889                 pr_info("  Issue PHB reset ...\n");
3890                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3891                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3892         }
3893
3894         /* Remove M64 resource if we can't configure it successfully */
3895         if (!phb->init_m64 || phb->init_m64(phb))
3896                 hose->mem_resources[1].flags = 0;
3897 }
3898
3899 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3900 {
3901         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3902 }
3903
3904 void __init pnv_pci_init_npu_phb(struct device_node *np)
3905 {
3906         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3907 }
3908
3909 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3910 {
3911         struct device_node *phbn;
3912         const __be64 *prop64;
3913         u64 hub_id;
3914
3915         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3916
3917         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3918         if (!prop64) {
3919                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3920                 return;
3921         }
3922         hub_id = be64_to_cpup(prop64);
3923         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3924
3925         /* Count child PHBs */
3926         for_each_child_of_node(np, phbn) {
3927                 /* Look for IODA1 PHBs */
3928                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3929                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3930         }
3931 }