arch/powerpc/sysdev/xive/native.c

   1 /*
   2  * Copyright 2016,2017 IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #define pr_fmt(fmt) "xive: " fmt
  11
  12 #include <linux/types.h>
  13 #include <linux/irq.h>
  14 #include <linux/debugfs.h>
  15 #include <linux/smp.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/init.h>
  19 #include <linux/of.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/cpumask.h>
  24 #include <linux/mm.h>
  25 #include <linux/kmemleak.h>
  26
  27 #include <asm/prom.h>
  28 #include <asm/io.h>
  29 #include <asm/smp.h>
  30 #include <asm/irq.h>
  31 #include <asm/errno.h>
  32 #include <asm/xive.h>
  33 #include <asm/xive-regs.h>
  34 #include <asm/opal.h>
  35 #include <asm/kvm_ppc.h>
  36
  37 #include "xive-internal.h"
  38
  39
  40 static u32 xive_provision_size;
  41 static u32 *xive_provision_chips;
  42 static u32 xive_provision_chip_count;
  43 static u32 xive_queue_shift;
  44 static u32 xive_pool_vps = XIVE_INVALID_VP;
  45 static struct kmem_cache *xive_provision_cache;
  46 static bool xive_has_single_esc;
  47
  48 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
  49 {
  50         __be64 flags, eoi_page, trig_page;
  51         __be32 esb_shift, src_chip;
  52         u64 opal_flags;
  53         s64 rc;
  54
  55         memset(data, 0, sizeof(*data));
  56
  57         rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
  58                                     &esb_shift, &src_chip);
  59         if (rc) {
  60                 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
  61                        hw_irq, rc);
  62                 return -EINVAL;
  63         }
  64
  65         opal_flags = be64_to_cpu(flags);
  66         if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
  67                 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
  68         if (opal_flags & OPAL_XIVE_IRQ_LSI)
  69                 data->flags |= XIVE_IRQ_FLAG_LSI;
  70         if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
  71                 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
  72         if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
  73                 data->flags |= XIVE_IRQ_FLAG_MASK_FW;
  74         if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
  75                 data->flags |= XIVE_IRQ_FLAG_EOI_FW;
  76         data->eoi_page = be64_to_cpu(eoi_page);
  77         data->trig_page = be64_to_cpu(trig_page);
  78         data->esb_shift = be32_to_cpu(esb_shift);
  79         data->src_chip = be32_to_cpu(src_chip);
  80
  81         data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
  82         if (!data->eoi_mmio) {
  83                 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
  84                 return -ENOMEM;
  85         }
  86
  87         data->hw_irq = hw_irq;
  88
  89         if (!data->trig_page)
  90                 return 0;
  91         if (data->trig_page == data->eoi_page) {
  92                 data->trig_mmio = data->eoi_mmio;
  93                 return 0;
  94         }
  95
  96         data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
  97         if (!data->trig_mmio) {
  98                 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
  99                 return -ENOMEM;
 100         }
 101         return 0;
 102 }
 103 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);
 104
 105 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
 106 {
 107         s64 rc;
 108
 109         for (;;) {
 110                 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
 111                 if (rc != OPAL_BUSY)
 112                         break;
 113                 msleep(OPAL_BUSY_DELAY_MS);
 114         }
 115         return rc == 0 ? 0 : -ENXIO;
 116 }
 117 EXPORT_SYMBOL_GPL(xive_native_configure_irq);
 118
 119
 120 /* This can be called multiple time to change a queue configuration */
 121 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
 122                                 __be32 *qpage, u32 order, bool can_escalate)
 123 {
 124         s64 rc = 0;
 125         __be64 qeoi_page_be;
 126         __be32 esc_irq_be;
 127         u64 flags, qpage_phys;
 128
 129         /* If there's an actual queue page, clean it */
 130         if (order) {
 131                 if (WARN_ON(!qpage))
 132                         return -EINVAL;
 133                 qpage_phys = __pa(qpage);
 134         } else
 135                 qpage_phys = 0;
 136
 137         /* Initialize the rest of the fields */
 138         q->msk = order ? ((1u << (order - 2)) - 1) : 0;
 139         q->idx = 0;
 140         q->toggle = 0;
 141
 142         rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
 143                                       &qeoi_page_be,
 144                                       &esc_irq_be,
 145                                       NULL);
 146         if (rc) {
 147                 pr_err("Error %lld getting queue info prio %d\n", rc, prio);
 148                 rc = -EIO;
 149                 goto fail;
 150         }
 151         q->eoi_phys = be64_to_cpu(qeoi_page_be);
 152
 153         /* Default flags */
 154         flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;
 155
 156         /* Escalation needed ? */
 157         if (can_escalate) {
 158                 q->esc_irq = be32_to_cpu(esc_irq_be);
 159                 flags |= OPAL_XIVE_EQ_ESCALATE;
 160         }
 161
 162         /* Configure and enable the queue in HW */
 163         for (;;) {
 164                 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
 165                 if (rc != OPAL_BUSY)
 166                         break;
 167                 msleep(OPAL_BUSY_DELAY_MS);
 168         }
 169         if (rc) {
 170                 pr_err("Error %lld setting queue for prio %d\n", rc, prio);
 171                 rc = -EIO;
 172         } else {
 173                 /*
 174                  * KVM code requires all of the above to be visible before
 175                  * q->qpage is set due to how it manages IPI EOIs
 176                  */
 177                 wmb();
 178                 q->qpage = qpage;
 179         }
 180 fail:
 181         return rc;
 182 }
 183 EXPORT_SYMBOL_GPL(xive_native_configure_queue);
 184
 185 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 186 {
 187         s64 rc;
 188
 189         /* Disable the queue in HW */
 190         for (;;) {
 191                 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
 192                 if (rc != OPAL_BUSY)
 193                         break;
 194                 msleep(OPAL_BUSY_DELAY_MS);
 195         }
 196         if (rc)
 197                 pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
 198 }
 199
 200 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 201 {
 202         __xive_native_disable_queue(vp_id, q, prio);
 203 }
 204 EXPORT_SYMBOL_GPL(xive_native_disable_queue);
 205
 206 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 207 {
 208         struct xive_q *q = &xc->queue[prio];
 209         __be32 *qpage;
 210
 211         qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
 212         if (IS_ERR(qpage))
 213                 return PTR_ERR(qpage);
 214
 215         return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
 216                                            q, prio, qpage, xive_queue_shift, false);
 217 }
 218
 219 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 220 {
 221         struct xive_q *q = &xc->queue[prio];
 222         unsigned int alloc_order;
 223
 224         /*
 225          * We use the variant with no iounmap as this is called on exec
 226          * from an IPI and iounmap isn't safe
 227          */
 228         __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
 229         alloc_order = xive_alloc_order(xive_queue_shift);
 230         free_pages((unsigned long)q->qpage, alloc_order);
 231         q->qpage = NULL;
 232 }
 233
 234 static bool xive_native_match(struct device_node *node)
 235 {
 236         return of_device_is_compatible(node, "ibm,opal-xive-vc");
 237 }
 238
 239 static s64 opal_xive_allocate_irq(u32 chip_id)
 240 {
 241         s64 irq = opal_xive_allocate_irq_raw(chip_id);
 242
 243         /*
 244          * Old versions of skiboot can incorrectly return 0xffffffff to
 245          * indicate no space, fix it up here.
 246          */
 247         return irq == 0xffffffff ? OPAL_RESOURCE : irq;
 248 }
 249
 250 #ifdef CONFIG_SMP
 251 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 252 {
 253         struct device_node *np;
 254         unsigned int chip_id;
 255         s64 irq;
 256
 257         /* Find the chip ID */
 258         np = of_get_cpu_node(cpu, NULL);
 259         if (np) {
 260                 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
 261                         chip_id = 0;
 262         }
 263
 264         /* Allocate an IPI and populate info about it */
 265         for (;;) {
 266                 irq = opal_xive_allocate_irq(chip_id);
 267                 if (irq == OPAL_BUSY) {
 268                         msleep(OPAL_BUSY_DELAY_MS);
 269                         continue;
 270                 }
 271                 if (irq < 0) {
 272                         pr_err("Failed to allocate IPI on CPU %d\n", cpu);
 273                         return -ENXIO;
 274                 }
 275                 xc->hw_ipi = irq;
 276                 break;
 277         }
 278         return 0;
 279 }
 280 #endif /* CONFIG_SMP */
 281
 282 u32 xive_native_alloc_irq(void)
 283 {
 284         s64 rc;
 285
 286         for (;;) {
 287                 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
 288                 if (rc != OPAL_BUSY)
 289                         break;
 290                 msleep(OPAL_BUSY_DELAY_MS);
 291         }
 292         if (rc < 0)
 293                 return 0;
 294         return rc;
 295 }
 296 EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
 297
 298 void xive_native_free_irq(u32 irq)
 299 {
 300         for (;;) {
 301                 s64 rc = opal_xive_free_irq(irq);
 302                 if (rc != OPAL_BUSY)
 303                         break;
 304                 msleep(OPAL_BUSY_DELAY_MS);
 305         }
 306 }
 307 EXPORT_SYMBOL_GPL(xive_native_free_irq);
 308
 309 #ifdef CONFIG_SMP
 310 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 311 {
 312         s64 rc;
 313
 314         /* Free the IPI */
 315         if (xc->hw_ipi == XIVE_BAD_IRQ)
 316                 return;
 317         for (;;) {
 318                 rc = opal_xive_free_irq(xc->hw_ipi);
 319                 if (rc == OPAL_BUSY) {
 320                         msleep(OPAL_BUSY_DELAY_MS);
 321                         continue;
 322                 }
 323                 xc->hw_ipi = XIVE_BAD_IRQ;
 324                 break;
 325         }
 326 }
 327 #endif /* CONFIG_SMP */
 328
 329 static void xive_native_shutdown(void)
 330 {
 331         /* Switch the XIVE to emulation mode */
 332         opal_xive_reset(OPAL_XIVE_MODE_EMU);
 333 }
 334
 335 /*
 336  * Perform an "ack" cycle on the current thread, thus
 337  * grabbing the pending active priorities and updating
 338  * the CPPR to the most favored one.
 339  */
 340 static void xive_native_update_pending(struct xive_cpu *xc)
 341 {
 342         u8 he, cppr;
 343         u16 ack;
 344
 345         /* Perform the acknowledge hypervisor to register cycle */
 346         ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
 347
 348         /* Synchronize subsequent queue accesses */
 349         mb();
 350
 351         /*
 352          * Grab the CPPR and the "HE" field which indicates the source
 353          * of the hypervisor interrupt (if any)
 354          */
 355         cppr = ack & 0xff;
 356         he = (ack >> 8) >> 6;
 357         switch(he) {
 358         case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
 359                 break;
 360         case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
 361                 if (cppr == 0xff)
 362                         return;
 363                 /* Mark the priority pending */
 364                 xc->pending_prio |= 1 << cppr;
 365
 366                 /*
 367                  * A new interrupt should never have a CPPR less favored
 368                  * than our current one.
 369                  */
 370                 if (cppr >= xc->cppr)
 371                         pr_err("CPU %d odd ack CPPR, got %d at %d\n",
 372                                smp_processor_id(), cppr, xc->cppr);
 373
 374                 /* Update our idea of what the CPPR is */
 375                 xc->cppr = cppr;
 376                 break;
 377         case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
 378         case TM_QW3_NSR_HE_LSI:  /* Legacy FW LSI (unused) */
 379                 pr_err("CPU %d got unexpected interrupt type HE=%d\n",
 380                        smp_processor_id(), he);
 381                 return;
 382         }
 383 }
 384
 385 static void xive_native_eoi(u32 hw_irq)
 386 {
 387         /*
 388          * Not normally used except if specific interrupts need
 389          * a workaround on EOI.
 390          */
 391         opal_int_eoi(hw_irq);
 392 }
 393
 394 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 395 {
 396         s64 rc;
 397         u32 vp;
 398         __be64 vp_cam_be;
 399         u64 vp_cam;
 400
 401         if (xive_pool_vps == XIVE_INVALID_VP)
 402                 return;
 403
 404         /* Check if pool VP already active, if it is, pull it */
 405         if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP)
 406                 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
 407
 408         /* Enable the pool VP */
 409         vp = xive_pool_vps + cpu;
 410         for (;;) {
 411                 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
 412                 if (rc != OPAL_BUSY)
 413                         break;
 414                 msleep(OPAL_BUSY_DELAY_MS);
 415         }
 416         if (rc) {
 417                 pr_err("Failed to enable pool VP on CPU %d\n", cpu);
 418                 return;
 419         }
 420
 421         /* Grab it's CAM value */
 422         rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
 423         if (rc) {
 424                 pr_err("Failed to get pool VP info CPU %d\n", cpu);
 425                 return;
 426         }
 427         vp_cam = be64_to_cpu(vp_cam_be);
 428
 429         /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
 430         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
 431         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam);
 432 }
 433
 434 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
 435 {
 436         s64 rc;
 437         u32 vp;
 438
 439         if (xive_pool_vps == XIVE_INVALID_VP)
 440                 return;
 441
 442         /* Pull the pool VP from the CPU */
 443         in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
 444
 445         /* Disable it */
 446         vp = xive_pool_vps + cpu;
 447         for (;;) {
 448                 rc = opal_xive_set_vp_info(vp, 0, 0);
 449                 if (rc != OPAL_BUSY)
 450                         break;
 451                 msleep(OPAL_BUSY_DELAY_MS);
 452         }
 453 }
 454
 455 void xive_native_sync_source(u32 hw_irq)
 456 {
 457         opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
 458 }
 459 EXPORT_SYMBOL_GPL(xive_native_sync_source);
 460
 461 static const struct xive_ops xive_native_ops = {
 462         .populate_irq_data      = xive_native_populate_irq_data,
 463         .configure_irq          = xive_native_configure_irq,
 464         .setup_queue            = xive_native_setup_queue,
 465         .cleanup_queue          = xive_native_cleanup_queue,
 466         .match                  = xive_native_match,
 467         .shutdown               = xive_native_shutdown,
 468         .update_pending         = xive_native_update_pending,
 469         .eoi                    = xive_native_eoi,
 470         .setup_cpu              = xive_native_setup_cpu,
 471         .teardown_cpu           = xive_native_teardown_cpu,
 472         .sync_source            = xive_native_sync_source,
 473 #ifdef CONFIG_SMP
 474         .get_ipi                = xive_native_get_ipi,
 475         .put_ipi                = xive_native_put_ipi,
 476 #endif /* CONFIG_SMP */
 477         .name                   = "native",
 478 };
 479
 480 static bool xive_parse_provisioning(struct device_node *np)
 481 {
 482         int rc;
 483
 484         if (of_property_read_u32(np, "ibm,xive-provision-page-size",
 485                                  &xive_provision_size) < 0)
 486                 return true;
 487         rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
 488         if (rc < 0) {
 489                 pr_err("Error %d getting provision chips array\n", rc);
 490                 return false;
 491         }
 492         xive_provision_chip_count = rc;
 493         if (rc == 0)
 494                 return true;
 495
 496         xive_provision_chips = kcalloc(4, xive_provision_chip_count,
 497                                        GFP_KERNEL);
 498         if (WARN_ON(!xive_provision_chips))
 499                 return false;
 500
 501         rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
 502                                         xive_provision_chips,
 503                                         xive_provision_chip_count);
 504         if (rc < 0) {
 505                 pr_err("Error %d reading provision chips array\n", rc);
 506                 return false;
 507         }
 508
 509         xive_provision_cache = kmem_cache_create("xive-provision",
 510                                                  xive_provision_size,
 511                                                  xive_provision_size,
 512                                                  0, NULL);
 513         if (!xive_provision_cache) {
 514                 pr_err("Failed to allocate provision cache\n");
 515                 return false;
 516         }
 517         return true;
 518 }
 519
 520 static void xive_native_setup_pools(void)
 521 {
 522         /* Allocate a pool big enough */
 523         pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);
 524
 525         xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
 526         if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
 527                 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");
 528
 529         pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n",
 530                  xive_pool_vps, nr_cpu_ids);
 531 }
 532
 533 u32 xive_native_default_eq_shift(void)
 534 {
 535         return xive_queue_shift;
 536 }
 537 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
 538
 539 bool __init xive_native_init(void)
 540 {
 541         struct device_node *np;
 542         struct resource r;
 543         void __iomem *tima;
 544         struct property *prop;
 545         u8 max_prio = 7;
 546         const __be32 *p;
 547         u32 val, cpu;
 548         s64 rc;
 549
 550         if (xive_cmdline_disabled)
 551                 return false;
 552
 553         pr_devel("xive_native_init()\n");
 554         np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
 555         if (!np) {
 556                 pr_devel("not found !\n");
 557                 return false;
 558         }
 559         pr_devel("Found %pOF\n", np);
 560
 561         /* Resource 1 is HV window */
 562         if (of_address_to_resource(np, 1, &r)) {
 563                 pr_err("Failed to get thread mgmnt area resource\n");
 564                 return false;
 565         }
 566         tima = ioremap(r.start, resource_size(&r));
 567         if (!tima) {
 568                 pr_err("Failed to map thread mgmnt area\n");
 569                 return false;
 570         }
 571
 572         /* Read number of priorities */
 573         if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
 574                 max_prio = val - 1;
 575
 576         /* Iterate the EQ sizes and pick one */
 577         of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
 578                 xive_queue_shift = val;
 579                 if (val == PAGE_SHIFT)
 580                         break;
 581         }
 582
 583         /* Do we support single escalation */
 584         if (of_get_property(np, "single-escalation-support", NULL) != NULL)
 585                 xive_has_single_esc = true;
 586
 587         /* Configure Thread Management areas for KVM */
 588         for_each_possible_cpu(cpu)
 589                 kvmppc_set_xive_tima(cpu, r.start, tima);
 590
 591         /* Grab size of provisionning pages */
 592         xive_parse_provisioning(np);
 593
 594         /* Switch the XIVE to exploitation mode */
 595         rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
 596         if (rc) {
 597                 pr_err("Switch to exploitation mode failed with error %lld\n", rc);
 598                 return false;
 599         }
 600
 601         /* Setup some dummy HV pool VPs */
 602         xive_native_setup_pools();
 603
 604         /* Initialize XIVE core with our backend */
 605         if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
 606                             max_prio)) {
 607                 opal_xive_reset(OPAL_XIVE_MODE_EMU);
 608                 return false;
 609         }
 610         pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
 611         return true;
 612 }
 613
 614 static bool xive_native_provision_pages(void)
 615 {
 616         u32 i;
 617         void *p;
 618
 619         for (i = 0; i < xive_provision_chip_count; i++) {
 620                 u32 chip = xive_provision_chips[i];
 621
 622                 /*
 623                  * XXX TODO: Try to make the allocation local to the node where
 624                  * the chip resides.
 625                  */
 626                 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
 627                 if (!p) {
 628                         pr_err("Failed to allocate provisioning page\n");
 629                         return false;
 630                 }
 631                 kmemleak_ignore(p);
 632                 opal_xive_donate_page(chip, __pa(p));
 633         }
 634         return true;
 635 }
 636
 637 u32 xive_native_alloc_vp_block(u32 max_vcpus)
 638 {
 639         s64 rc;
 640         u32 order;
 641
 642         order = fls(max_vcpus) - 1;
 643         if (max_vcpus > (1 << order))
 644                 order++;
 645
 646         pr_debug("VP block alloc, for max VCPUs %d use order %d\n",
 647                  max_vcpus, order);
 648
 649         for (;;) {
 650                 rc = opal_xive_alloc_vp_block(order);
 651                 switch (rc) {
 652                 case OPAL_BUSY:
 653                         msleep(OPAL_BUSY_DELAY_MS);
 654                         break;
 655                 case OPAL_XIVE_PROVISIONING:
 656                         if (!xive_native_provision_pages())
 657                                 return XIVE_INVALID_VP;
 658                         break;
 659                 default:
 660                         if (rc < 0) {
 661                                 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
 662                                        order, rc);
 663                                 return XIVE_INVALID_VP;
 664                         }
 665                         return rc;
 666                 }
 667         }
 668 }
 669 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
 670
 671 void xive_native_free_vp_block(u32 vp_base)
 672 {
 673         s64 rc;
 674
 675         if (vp_base == XIVE_INVALID_VP)
 676                 return;
 677
 678         rc = opal_xive_free_vp_block(vp_base);
 679         if (rc < 0)
 680                 pr_warn("OPAL error %lld freeing VP block\n", rc);
 681 }
 682 EXPORT_SYMBOL_GPL(xive_native_free_vp_block);
 683
 684 int xive_native_enable_vp(u32 vp_id, bool single_escalation)
 685 {
 686         s64 rc;
 687         u64 flags = OPAL_XIVE_VP_ENABLED;
 688
 689         if (single_escalation)
 690                 flags |= OPAL_XIVE_VP_SINGLE_ESCALATION;
 691         for (;;) {
 692                 rc = opal_xive_set_vp_info(vp_id, flags, 0);
 693                 if (rc != OPAL_BUSY)
 694                         break;
 695                 msleep(OPAL_BUSY_DELAY_MS);
 696         }
 697         return rc ? -EIO : 0;
 698 }
 699 EXPORT_SYMBOL_GPL(xive_native_enable_vp);
 700
 701 int xive_native_disable_vp(u32 vp_id)
 702 {
 703         s64 rc;
 704
 705         for (;;) {
 706                 rc = opal_xive_set_vp_info(vp_id, 0, 0);
 707                 if (rc != OPAL_BUSY)
 708                         break;
 709                 msleep(OPAL_BUSY_DELAY_MS);
 710         }
 711         return rc ? -EIO : 0;
 712 }
 713 EXPORT_SYMBOL_GPL(xive_native_disable_vp);
 714
 715 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
 716 {
 717         __be64 vp_cam_be;
 718         __be32 vp_chip_id_be;
 719         s64 rc;
 720
 721         rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
 722         if (rc)
 723                 return -EIO;
 724         *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
 725         *out_chip_id = be32_to_cpu(vp_chip_id_be);
 726
 727         return 0;
 728 }
 729 EXPORT_SYMBOL_GPL(xive_native_get_vp_info);
 730
 731 bool xive_native_has_single_escalation(void)
 732 {
 733         return xive_has_single_esc;
 734 }
 735 EXPORT_SYMBOL_GPL(xive_native_has_single_escalation);