2 * Copyright 2016,2017 IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #define pr_fmt(fmt) "xive: " fmt
12 #include <linux/types.h>
13 #include <linux/irq.h>
14 #include <linux/smp.h>
15 #include <linux/interrupt.h>
16 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/cpumask.h>
27 #include <asm/errno.h>
29 #include <asm/xive-regs.h>
30 #include <asm/hvcall.h>
32 #include "xive-internal.h"
34 static u32 xive_queue_shift;
36 struct xive_irq_bitmap {
37 unsigned long *bitmap;
41 struct list_head list;
44 static LIST_HEAD(xive_irq_bitmaps);
46 static int xive_irq_bitmap_add(int base, int count)
48 struct xive_irq_bitmap *xibm;
50 xibm = kzalloc(sizeof(*xibm), GFP_ATOMIC);
54 spin_lock_init(&xibm->lock);
57 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
58 list_add(&xibm->list, &xive_irq_bitmaps);
60 pr_info("Using IRQ range [%x-%x]", xibm->base,
61 xibm->base + xibm->count - 1);
65 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
69 irq = find_first_zero_bit(xibm->bitmap, xibm->count);
70 if (irq != xibm->count) {
71 set_bit(irq, xibm->bitmap);
80 static int xive_irq_bitmap_alloc(void)
82 struct xive_irq_bitmap *xibm;
86 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
87 spin_lock_irqsave(&xibm->lock, flags);
88 irq = __xive_irq_bitmap_alloc(xibm);
89 spin_unlock_irqrestore(&xibm->lock, flags);
96 static void xive_irq_bitmap_free(int irq)
99 struct xive_irq_bitmap *xibm;
101 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
102 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
103 spin_lock_irqsave(&xibm->lock, flags);
104 clear_bit(irq - xibm->base, xibm->bitmap);
105 spin_unlock_irqrestore(&xibm->lock, flags);
111 static long plpar_int_get_source_info(unsigned long flags,
113 unsigned long *src_flags,
114 unsigned long *eoi_page,
115 unsigned long *trig_page,
116 unsigned long *esb_shift)
118 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
121 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
123 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc);
127 *src_flags = retbuf[0];
128 *eoi_page = retbuf[1];
129 *trig_page = retbuf[2];
130 *esb_shift = retbuf[3];
132 pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n",
133 retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
138 #define XIVE_SRC_SET_EISN (1ull << (63 - 62))
139 #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */
141 static long plpar_int_set_source_config(unsigned long flags,
143 unsigned long target,
145 unsigned long sw_irq)
150 pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n",
151 flags, lisn, target, prio, sw_irq);
154 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
155 target, prio, sw_irq);
157 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n",
158 lisn, target, prio, rc);
165 static long plpar_int_get_queue_info(unsigned long flags,
166 unsigned long target,
167 unsigned long priority,
168 unsigned long *esn_page,
169 unsigned long *esn_size)
171 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
174 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, priority);
176 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
177 target, priority, rc);
181 *esn_page = retbuf[0];
182 *esn_size = retbuf[1];
184 pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n",
185 retbuf[0], retbuf[1]);
190 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
192 static long plpar_int_set_queue_config(unsigned long flags,
193 unsigned long target,
194 unsigned long priority,
200 pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n",
201 flags, target, priority, qpage, qsize);
203 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
204 priority, qpage, qsize);
206 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n",
207 target, priority, qpage, rc);
214 static long plpar_int_sync(unsigned long flags, unsigned long lisn)
218 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
220 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc);
227 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
229 static long plpar_int_esb(unsigned long flags,
231 unsigned long offset,
232 unsigned long in_data,
233 unsigned long *out_data)
235 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
238 pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
239 flags, lisn, offset, in_data);
241 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, in_data);
243 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
248 *out_data = retbuf[0];
253 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
255 unsigned long read_data;
258 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
259 lisn, offset, data, &read_data);
263 return write ? 0 : read_data;
266 #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))
267 #define XIVE_SRC_LSI (1ull << (63 - 61))
268 #define XIVE_SRC_TRIGGER (1ull << (63 - 62))
269 #define XIVE_SRC_STORE_EOI (1ull << (63 - 63))
271 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
275 unsigned long eoi_page;
276 unsigned long trig_page;
277 unsigned long esb_shift;
279 memset(data, 0, sizeof(*data));
281 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
286 if (flags & XIVE_SRC_H_INT_ESB)
287 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB;
288 if (flags & XIVE_SRC_STORE_EOI)
289 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
290 if (flags & XIVE_SRC_LSI)
291 data->flags |= XIVE_IRQ_FLAG_LSI;
292 data->eoi_page = eoi_page;
293 data->esb_shift = esb_shift;
294 data->trig_page = trig_page;
296 data->hw_irq = hw_irq;
299 * No chip-id for the sPAPR backend. This has an impact how we
300 * pick a target. See xive_pick_irq_target().
302 data->src_chip = XIVE_INVALID_CHIP_ID;
305 * When the H_INT_ESB flag is set, the H_INT_ESB hcall should
306 * be used for interrupt management. Skip the remapping of the
307 * ESB pages which are not available.
309 if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB)
312 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
313 if (!data->eoi_mmio) {
314 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
318 /* Full function page supports trigger */
319 if (flags & XIVE_SRC_TRIGGER) {
320 data->trig_mmio = data->eoi_mmio;
324 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
325 if (!data->trig_mmio) {
326 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
332 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
336 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
339 return rc == 0 ? 0 : -ENXIO;
342 /* This can be called multiple time to change a queue configuration */
343 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
344 __be32 *qpage, u32 order)
347 unsigned long esn_page;
348 unsigned long esn_size;
349 u64 flags, qpage_phys;
351 /* If there's an actual queue page, clean it */
355 qpage_phys = __pa(qpage);
360 /* Initialize the rest of the fields */
361 q->msk = order ? ((1u << (order - 2)) - 1) : 0;
365 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
367 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
373 /* TODO: add support for the notification page */
374 q->eoi_phys = esn_page;
376 /* Default is to always notify */
377 flags = XIVE_EQ_ALWAYS_NOTIFY;
379 /* Configure and enable the queue in HW */
380 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
382 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
392 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
395 struct xive_q *q = &xc->queue[prio];
398 qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
400 return PTR_ERR(qpage);
402 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
403 q, prio, qpage, xive_queue_shift);
406 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
409 struct xive_q *q = &xc->queue[prio];
410 unsigned int alloc_order;
412 int hw_cpu = get_hard_smp_processor_id(cpu);
414 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
416 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
419 alloc_order = xive_alloc_order(xive_queue_shift);
420 free_pages((unsigned long)q->qpage, alloc_order);
424 static bool xive_spapr_match(struct device_node *node)
426 /* Ignore cascaded controllers for the moment */
431 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
433 int irq = xive_irq_bitmap_alloc();
436 pr_err("Failed to allocate IPI on CPU %d\n", cpu);
444 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
446 if (xc->hw_ipi == XIVE_BAD_IRQ)
449 xive_irq_bitmap_free(xc->hw_ipi);
450 xc->hw_ipi = XIVE_BAD_IRQ;
452 #endif /* CONFIG_SMP */
454 static void xive_spapr_shutdown(void)
458 rc = plpar_hcall_norets(H_INT_RESET, 0);
460 pr_err("H_INT_RESET failed %ld\n", rc);
464 * Perform an "ack" cycle on the current thread. Grab the pending
465 * active priorities and update the CPPR to the most favored one.
467 static void xive_spapr_update_pending(struct xive_cpu *xc)
473 * Perform the "Acknowledge O/S to Register" cycle.
475 * Let's speedup the access to the TIMA using the raw I/O
476 * accessor as we don't need the synchronisation routine of
477 * the higher level ones
479 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
481 /* Synchronize subsequent queue accesses */
485 * Grab the CPPR and the "NSR" field which indicates the source
486 * of the interrupt (if any)
491 if (nsr & TM_QW1_NSR_EO) {
494 /* Mark the priority pending */
495 xc->pending_prio |= 1 << cppr;
498 * A new interrupt should never have a CPPR less favored
499 * than our current one.
501 if (cppr >= xc->cppr)
502 pr_err("CPU %d odd ack CPPR, got %d at %d\n",
503 smp_processor_id(), cppr, xc->cppr);
505 /* Update our idea of what the CPPR is */
510 static void xive_spapr_eoi(u32 hw_irq)
515 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
517 /* Only some debug on the TIMA settings */
518 pr_debug("(HW value: %08x %08x %08x)\n",
519 in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
520 in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
521 in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
524 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
529 static void xive_spapr_sync_source(u32 hw_irq)
531 /* Specs are unclear on what this is doing */
532 plpar_int_sync(0, hw_irq);
535 static const struct xive_ops xive_spapr_ops = {
536 .populate_irq_data = xive_spapr_populate_irq_data,
537 .configure_irq = xive_spapr_configure_irq,
538 .setup_queue = xive_spapr_setup_queue,
539 .cleanup_queue = xive_spapr_cleanup_queue,
540 .match = xive_spapr_match,
541 .shutdown = xive_spapr_shutdown,
542 .update_pending = xive_spapr_update_pending,
543 .eoi = xive_spapr_eoi,
544 .setup_cpu = xive_spapr_setup_cpu,
545 .teardown_cpu = xive_spapr_teardown_cpu,
546 .sync_source = xive_spapr_sync_source,
547 .esb_rw = xive_spapr_esb_rw,
549 .get_ipi = xive_spapr_get_ipi,
550 .put_ipi = xive_spapr_put_ipi,
551 #endif /* CONFIG_SMP */
556 * get max priority from "/ibm,plat-res-int-priorities"
558 static bool xive_get_max_prio(u8 *max_prio)
560 struct device_node *rootdn;
565 rootdn = of_find_node_by_path("/");
567 pr_err("not root node found !\n");
571 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
573 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
577 if (len % (2 * sizeof(u32)) != 0) {
578 pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
582 /* HW supports priorities in the range [0-7] and 0xFF is a
583 * wildcard priority used to mask. We scan the ranges reserved
584 * by the hypervisor to find the lowest priority we can use.
587 for (prio = 0; prio < 8; prio++) {
591 for (i = 0; i < len / (2 * sizeof(u32)); i++) {
592 int base = be32_to_cpu(reg[2 * i]);
593 int range = be32_to_cpu(reg[2 * i + 1]);
595 if (prio >= base && prio < base + range)
604 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
612 bool __init xive_spapr_init(void)
614 struct device_node *np;
617 struct property *prop;
624 if (xive_cmdline_disabled)
627 pr_devel("%s()\n", __func__);
628 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
630 pr_devel("not found !\n");
633 pr_devel("Found %s\n", np->full_name);
635 /* Resource 1 is the OS ring TIMA */
636 if (of_address_to_resource(np, 1, &r)) {
637 pr_err("Failed to get thread mgmnt area resource\n");
640 tima = ioremap(r.start, resource_size(&r));
642 pr_err("Failed to map thread mgmnt area\n");
646 if (!xive_get_max_prio(&max_prio))
649 /* Feed the IRQ number allocator with the ranges given in the DT */
650 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
652 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
656 if (len % (2 * sizeof(u32)) != 0) {
657 pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
661 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
662 xive_irq_bitmap_add(be32_to_cpu(reg[0]),
663 be32_to_cpu(reg[1]));
665 /* Iterate the EQ sizes and pick one */
666 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
667 xive_queue_shift = val;
668 if (val == PAGE_SHIFT)
672 /* Initialize XIVE core with our backend */
673 if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
676 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));