2 * S390 low-level entry points.
4 * Copyright IBM Corp. 1999, 2012
5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
6 * Hartmut Penner (hp@de.ibm.com),
7 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
8 * Heiko Carstens <heiko.carstens@de.ibm.com>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/errno.h>
16 #include <asm/ptrace.h>
17 #include <asm/thread_info.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/unistd.h>
23 #include <asm/vx-insn.h>
24 #include <asm/setup.h>
26 #include <asm/nospec-insn.h>
29 __PT_R1 = __PT_GPRS + 8
30 __PT_R2 = __PT_GPRS + 16
31 __PT_R3 = __PT_GPRS + 24
32 __PT_R4 = __PT_GPRS + 32
33 __PT_R5 = __PT_GPRS + 40
34 __PT_R6 = __PT_GPRS + 48
35 __PT_R7 = __PT_GPRS + 56
36 __PT_R8 = __PT_GPRS + 64
37 __PT_R9 = __PT_GPRS + 72
38 __PT_R10 = __PT_GPRS + 80
39 __PT_R11 = __PT_GPRS + 88
40 __PT_R12 = __PT_GPRS + 96
41 __PT_R13 = __PT_GPRS + 104
42 __PT_R14 = __PT_GPRS + 112
43 __PT_R15 = __PT_GPRS + 120
45 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
46 STACK_SIZE = 1 << STACK_SHIFT
47 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
49 _TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
51 _TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
52 _TIF_SYSCALL_TRACEPOINT)
53 _CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE | _CIF_FPU)
54 _PIF_WORK = (_PIF_PER_TRAP)
56 #define BASED(name) name-cleanup_critical(%r13)
59 #ifdef CONFIG_TRACE_IRQFLAGS
61 brasl %r14,trace_hardirqs_on_caller
66 #ifdef CONFIG_TRACE_IRQFLAGS
68 brasl %r14,trace_hardirqs_off_caller
72 .macro LOCKDEP_SYS_EXIT
74 tm __PT_PSW+1(%r11),0x01 # returning to user ?
76 brasl %r14,lockdep_sys_exit
80 .macro CHECK_STACK stacksize,savearea
81 #ifdef CONFIG_CHECK_STACK
82 tml %r15,\stacksize - CONFIG_STACK_GUARD
88 .macro SWITCH_ASYNC savearea,timer
89 tmhh %r8,0x0001 # interrupting from user ?
92 slg %r14,BASED(.Lcritical_start)
93 clg %r14,BASED(.Lcritical_length)
95 lghi %r11,\savearea # inside critical section, do cleanup
96 brasl %r14,cleanup_critical
97 tmhh %r8,0x0001 # retest problem state after cleanup
99 0: lg %r14,__LC_ASYNC_STACK # are we already on the async stack?
101 srag %r14,%r14,STACK_SHIFT
103 CHECK_STACK 1<<STACK_SHIFT,\savearea
104 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
107 UPDATE_VTIME %r14,%r15,\timer
108 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
109 2: lg %r15,__LC_ASYNC_STACK # load async stack
110 3: la %r11,STACK_FRAME_OVERHEAD(%r15)
113 .macro UPDATE_VTIME w1,w2,enter_timer
114 lg \w1,__LC_EXIT_TIMER
115 lg \w2,__LC_LAST_UPDATE_TIMER
117 slg \w2,__LC_EXIT_TIMER
118 alg \w1,__LC_USER_TIMER
119 alg \w2,__LC_SYSTEM_TIMER
120 stg \w1,__LC_USER_TIMER
121 stg \w2,__LC_SYSTEM_TIMER
122 mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer
125 .macro LAST_BREAK scratch
126 srag \scratch,%r10,23
128 stg %r10,__TI_last_break(%r12)
132 stg %r8,__LC_RETURN_PSW
133 ni __LC_RETURN_PSW,0xbf
138 #ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
139 .insn s,0xb27c0000,\savearea # store clock fast
141 .insn s,0xb2050000,\savearea # store clock
146 * The TSTMSK macro generates a test-under-mask instruction by
147 * calculating the memory offset for the specified mask value.
148 * Mask value can be any constant. The macro shifts the mask
149 * value to calculate the memory offset for the test-under-mask
152 .macro TSTMSK addr, mask, size=8, bytepos=0
153 .if (\bytepos < \size) && (\mask >> 8)
155 .error "Mask exceeds byte boundary"
157 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
161 .error "Mask must not be zero"
163 off = \size - \bytepos - 1
168 .pushsection .altinstr_replacement, "ax"
169 660: .long 0xb2e8c000
171 661: .long 0x47000000
172 .pushsection .altinstructions, "a"
182 .pushsection .altinstr_replacement, "ax"
183 662: .long 0xb2e8d000
185 663: .long 0x47000000
186 .pushsection .altinstructions, "a"
195 .macro BPENTER tif_ptr,tif_mask
196 .pushsection .altinstr_replacement, "ax"
197 662: .word 0xc004, 0x0000, 0x0000 # 6 byte nop
198 .word 0xc004, 0x0000, 0x0000 # 6 byte nop
200 664: TSTMSK \tif_ptr,\tif_mask
203 .pushsection .altinstructions, "a"
212 .macro BPEXIT tif_ptr,tif_mask
213 TSTMSK \tif_ptr,\tif_mask
214 .pushsection .altinstr_replacement, "ax"
220 .pushsection .altinstructions, "a"
231 GEN_BR_THUNK %r14,%r11
233 .section .kprobes.text, "ax"
241 * Scheduler resume function, called by switch_to
242 * gpr2 = (task_struct *) prev
243 * gpr3 = (task_struct *) next
248 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
250 aghi %r1,__TASK_thread # thread_struct of prev task
251 lg %r4,__TASK_thread_info(%r2) # get thread_info of prev
252 lg %r5,__TASK_thread_info(%r3) # get thread_info of next
253 stg %r15,__THREAD_ksp(%r1) # store kernel stack of prev
255 aghi %r1,__TASK_thread # thread_struct of next task
257 aghi %r15,STACK_INIT # end of kernel stack of next
258 stg %r3,__LC_CURRENT # store task struct of next
259 stg %r5,__LC_THREAD_INFO # store thread info of next
260 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
261 lg %r15,__THREAD_ksp(%r1) # load kernel stack of next
262 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
263 mvc __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next
264 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
265 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
267 .insn s,0xb2800000,__LC_LPP # set program parameter
272 #if IS_ENABLED(CONFIG_KVM)
274 * sie64a calling convention:
275 * %r2 pointer to sie control block
276 * %r3 guest register save area
279 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
281 stg %r2,__SF_EMPTY(%r15) # save control block pointer
282 stg %r3,__SF_EMPTY+8(%r15) # save guest register save area
283 xc __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # reason code = 0
284 mvc __SF_EMPTY+24(8,%r15),__TI_flags(%r12) # copy thread flags
285 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
286 jno .Lsie_load_guest_gprs
287 brasl %r14,load_fpu_regs # load guest fp/vx regs
288 .Lsie_load_guest_gprs:
289 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
290 lg %r14,__LC_GMAP # get gmap pointer
293 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
295 lg %r14,__SF_EMPTY(%r15) # get control block pointer
296 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
297 tm __SIE_PROG20+3(%r14),3 # last exit...
299 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
300 jo .Lsie_skip # exit if fp/vx regs changed
301 BPEXIT __SF_EMPTY+24(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
305 BPENTER __SF_EMPTY+24(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
307 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
308 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
310 # some program checks are suppressing. C code (e.g. do_protection_exception)
311 # will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
312 # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
313 # Other instructions between sie64a and .Lsie_done should not cause program
314 # interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
315 # See also .Lcleanup_sie
324 lg %r14,__SF_EMPTY+8(%r15) # load guest register save area
325 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
326 xgr %r0,%r0 # clear guest registers to
327 xgr %r1,%r1 # prevent speculative use
332 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
333 lg %r2,__SF_EMPTY+16(%r15) # return exit reason code
337 stg %r14,__SF_EMPTY+16(%r15) # set exit reason code
340 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
341 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
342 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
343 EX_TABLE(sie_exit,.Lsie_fault)
347 * SVC interrupt handler routine. System calls are synchronous events and
348 * are executed with interrupts enabled.
352 stpt __LC_SYNC_ENTER_TIMER
354 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
356 lg %r10,__LC_LAST_BREAK
357 lg %r12,__LC_THREAD_INFO
358 lghi %r14,_PIF_SYSCALL
360 lg %r15,__LC_KERNEL_STACK
361 la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
364 UPDATE_VTIME %r10,%r13,__LC_SYNC_ENTER_TIMER
365 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
366 stmg %r0,%r7,__PT_R0(%r11)
367 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
368 mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
369 mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC
370 stg %r14,__PT_FLAGS(%r11)
372 # clear user controlled register to prevent speculative use
374 lg %r10,__TI_sysc_table(%r12) # address of system call table
375 llgh %r8,__PT_INT_CODE+2(%r11)
376 slag %r8,%r8,2 # shift and test for svc 0
378 # svc 0: system call number in %r1
379 llgfr %r1,%r1 # clear high word in r1
382 sth %r1,__PT_INT_CODE+2(%r11)
385 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
386 stg %r2,__PT_ORIG_GPR2(%r11)
387 stg %r7,STACK_FRAME_OVERHEAD(%r15)
388 lgf %r9,0(%r8,%r10) # get system call add.
389 TSTMSK __TI_flags(%r12),_TIF_TRACE
391 BASR_EX %r14,%r9 # call sys_xxxx
392 stg %r2,__PT_R2(%r11) # store return value
397 TSTMSK __PT_FLAGS(%r11),_PIF_WORK
399 TSTMSK __TI_flags(%r12),_TIF_WORK
400 jnz .Lsysc_work # check for work
401 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
403 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
405 lg %r14,__LC_VDSO_PER_CPU
406 lmg %r0,%r10,__PT_R0(%r11)
407 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
410 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
411 lmg %r11,%r15,__PT_R11(%r11)
412 lpswe __LC_RETURN_PSW
416 # One of the work bits is on. Find out which one.
419 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
420 jo .Lsysc_mcck_pending
421 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
423 #ifdef CONFIG_UPROBES
424 TSTMSK __TI_flags(%r12),_TIF_UPROBE
425 jo .Lsysc_uprobe_notify
427 TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP
429 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
431 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
432 jo .Lsysc_notify_resume
433 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
435 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE
437 j .Lsysc_return # beware of critical section cleanup
440 # _TIF_NEED_RESCHED is set, call schedule
443 larl %r14,.Lsysc_return
447 # _CIF_MCCK_PENDING is set, call handler
450 larl %r14,.Lsysc_return
451 jg s390_handle_mcck # TIF bit will be cleared by handler
454 # _CIF_ASCE is set, load user space asce
457 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE
458 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
462 # CIF_FPU is set, restore floating-point controls and floating-point registers.
465 larl %r14,.Lsysc_return
469 # _TIF_SIGPENDING is set, call do_signal
472 lgr %r2,%r11 # pass pointer to pt_regs
474 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
476 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
477 lg %r10,__TI_sysc_table(%r12) # address of system call table
478 lghi %r8,0 # svc 0 returns -ENOSYS
479 llgh %r1,__PT_INT_CODE+2(%r11) # load new svc number
481 jnl .Lsysc_nr_ok # invalid svc number -> do svc 0
483 j .Lsysc_nr_ok # restart svc
486 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
488 .Lsysc_notify_resume:
489 lgr %r2,%r11 # pass pointer to pt_regs
490 larl %r14,.Lsysc_return
494 # _TIF_UPROBE is set, call uprobe_notify_resume
496 #ifdef CONFIG_UPROBES
497 .Lsysc_uprobe_notify:
498 lgr %r2,%r11 # pass pointer to pt_regs
499 larl %r14,.Lsysc_return
500 jg uprobe_notify_resume
504 # _PIF_PER_TRAP is set, call do_per_trap
507 ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
508 lgr %r2,%r11 # pass pointer to pt_regs
509 larl %r14,.Lsysc_return
513 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
514 # and after the system call
517 lgr %r2,%r11 # pass pointer to pt_regs
519 llgh %r0,__PT_INT_CODE+2(%r11)
520 stg %r0,__PT_R2(%r11)
521 brasl %r14,do_syscall_trace_enter
528 lmg %r3,%r7,__PT_R3(%r11)
529 stg %r7,STACK_FRAME_OVERHEAD(%r15)
530 lg %r2,__PT_ORIG_GPR2(%r11)
531 BASR_EX %r14,%r9 # call sys_xxx
532 stg %r2,__PT_R2(%r11) # store return value
534 TSTMSK __TI_flags(%r12),_TIF_TRACE
536 lgr %r2,%r11 # pass pointer to pt_regs
537 larl %r14,.Lsysc_return
538 jg do_syscall_trace_exit
541 # a new process exits the kernel with ret_from_fork
544 la %r11,STACK_FRAME_OVERHEAD(%r15)
545 lg %r12,__LC_THREAD_INFO
546 brasl %r14,schedule_tail
548 ssm __LC_SVC_NEW_PSW # reenable interrupts
549 tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ?
551 # it's a kernel thread
552 lmg %r9,%r10,__PT_R9(%r11) # load gprs
553 ENTRY(kernel_thread_starter)
559 * Program check handler routine
562 ENTRY(pgm_check_handler)
563 stpt __LC_SYNC_ENTER_TIMER
565 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
566 lg %r10,__LC_LAST_BREAK
567 lg %r12,__LC_THREAD_INFO
568 larl %r13,cleanup_critical
569 lmg %r8,%r9,__LC_PGM_OLD_PSW
570 tmhh %r8,0x0001 # test problem state bit
571 jnz 2f # -> fault in user space
572 #if IS_ENABLED(CONFIG_KVM)
573 # cleanup critical section for sie64a
575 slg %r14,BASED(.Lsie_critical_start)
576 clg %r14,BASED(.Lsie_critical_length)
578 brasl %r14,.Lcleanup_sie
580 0: tmhh %r8,0x4000 # PER bit set in old PSW ?
581 jnz 1f # -> enabled, can't be a double fault
582 tm __LC_PGM_ILC+3,0x80 # check for per exception
583 jnz .Lpgm_svcper # -> single stepped svc
584 1: CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
585 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
588 UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
589 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
590 lg %r15,__LC_KERNEL_STACK
591 lg %r14,__TI_task(%r12)
592 aghi %r14,__TASK_thread # pointer to thread_struct
593 lghi %r13,__LC_PGM_TDB
594 tm __LC_PGM_ILC+2,0x02 # check for transaction abort
596 mvc __THREAD_trap_tdb(256,%r14),0(%r13)
597 3: la %r11,STACK_FRAME_OVERHEAD(%r15)
598 stmg %r0,%r7,__PT_R0(%r11)
599 # clear user controlled registers to prevent speculative use
608 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
609 stmg %r8,%r9,__PT_PSW(%r11)
610 mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC
611 mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
612 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
613 stg %r10,__PT_ARGS(%r11)
614 tm __LC_PGM_ILC+3,0x80 # check for per exception
616 tmhh %r8,0x0001 # kernel per event ?
618 oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP
619 mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS
620 mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE
621 mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
623 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
624 larl %r1,pgm_check_table
625 llgh %r10,__PT_INT_CODE+2(%r11)
629 lgf %r9,0(%r10,%r1) # load address of handler routine
630 lgr %r2,%r11 # pass pointer to pt_regs
631 BASR_EX %r14,%r9 # branch to interrupt-handler
634 tm __PT_PSW+1(%r11),0x01 # returning to user ?
639 # PER event in supervisor state, must be kprobes
643 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
644 lgr %r2,%r11 # pass pointer to pt_regs
645 brasl %r14,do_per_trap
649 # single stepped system call
652 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
654 stg %r14,__LC_RETURN_PSW+8
655 lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP
656 lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs
659 * IO interrupt handler routine
661 ENTRY(io_int_handler)
663 stpt __LC_ASYNC_ENTER_TIMER
665 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
666 lg %r10,__LC_LAST_BREAK
667 lg %r12,__LC_THREAD_INFO
668 larl %r13,cleanup_critical
669 lmg %r8,%r9,__LC_IO_OLD_PSW
670 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
671 stmg %r0,%r7,__PT_R0(%r11)
672 # clear user controlled registers to prevent speculative use
682 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
683 stmg %r8,%r9,__PT_PSW(%r11)
684 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
685 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
686 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
689 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
691 lgr %r2,%r11 # pass pointer to pt_regs
692 lghi %r3,IO_INTERRUPT
693 tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ?
695 lghi %r3,THIN_INTERRUPT
698 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
702 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
708 TSTMSK __TI_flags(%r12),_TIF_WORK
709 jnz .Lio_work # there is work to do (signals etc.)
710 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
713 lg %r14,__LC_VDSO_PER_CPU
714 lmg %r0,%r10,__PT_R0(%r11)
715 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
716 tm __PT_PSW+1(%r11),0x01 # returning to user ?
718 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
721 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
723 lmg %r11,%r15,__PT_R11(%r11)
724 lpswe __LC_RETURN_PSW
728 # There is work todo, find out in which context we have been interrupted:
729 # 1) if we return to user space we can do all _TIF_WORK work
730 # 2) if we return to kernel code and kvm is enabled check if we need to
731 # modify the psw to leave SIE
732 # 3) if we return to kernel code and preemptive scheduling is enabled check
733 # the preemption counter and if it is zero call preempt_schedule_irq
734 # Before any work can be done, a switch to the kernel stack is required.
737 tm __PT_PSW+1(%r11),0x01 # returning to user ?
738 jo .Lio_work_user # yes -> do resched & signal
739 #ifdef CONFIG_PREEMPT
740 # check for preemptive scheduling
741 icm %r0,15,__TI_precount(%r12)
742 jnz .Lio_restore # preemption is disabled
743 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
745 # switch to kernel stack
746 lg %r1,__PT_R15(%r11)
747 aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
748 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
749 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
750 la %r11,STACK_FRAME_OVERHEAD(%r1)
752 # TRACE_IRQS_ON already done at .Lio_return, call
753 # TRACE_IRQS_OFF to keep things symmetrical
755 brasl %r14,preempt_schedule_irq
762 # Need to do work before returning to userspace, switch to kernel stack
765 lg %r1,__LC_KERNEL_STACK
766 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
767 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
768 la %r11,STACK_FRAME_OVERHEAD(%r1)
772 # One of the work bits is on. Find out which one.
775 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
777 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
779 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
781 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
782 jo .Lio_notify_resume
783 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
785 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE
787 j .Lio_return # beware of critical section cleanup
790 # _CIF_MCCK_PENDING is set, call handler
793 # TRACE_IRQS_ON already done at .Lio_return
794 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
799 # _CIF_ASCE is set, load user space asce
802 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE
803 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
807 # CIF_FPU is set, restore floating-point controls and floating-point registers.
810 larl %r14,.Lio_return
814 # _TIF_NEED_RESCHED is set, call schedule
817 # TRACE_IRQS_ON already done at .Lio_return
818 ssm __LC_SVC_NEW_PSW # reenable interrupts
819 brasl %r14,schedule # call scheduler
820 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
825 # _TIF_SIGPENDING or is set, call do_signal
828 # TRACE_IRQS_ON already done at .Lio_return
829 ssm __LC_SVC_NEW_PSW # reenable interrupts
830 lgr %r2,%r11 # pass pointer to pt_regs
832 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
837 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
840 # TRACE_IRQS_ON already done at .Lio_return
841 ssm __LC_SVC_NEW_PSW # reenable interrupts
842 lgr %r2,%r11 # pass pointer to pt_regs
843 brasl %r14,do_notify_resume
844 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
849 * External interrupt handler routine
851 ENTRY(ext_int_handler)
853 stpt __LC_ASYNC_ENTER_TIMER
855 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
856 lg %r10,__LC_LAST_BREAK
857 lg %r12,__LC_THREAD_INFO
858 larl %r13,cleanup_critical
859 lmg %r8,%r9,__LC_EXT_OLD_PSW
860 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
861 stmg %r0,%r7,__PT_R0(%r11)
862 # clear user controlled registers to prevent speculative use
872 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
873 stmg %r8,%r9,__PT_PSW(%r11)
874 lghi %r1,__LC_EXT_PARAMS2
875 mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
876 mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
877 mvc __PT_INT_PARM_LONG(8,%r11),0(%r1)
878 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
879 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
882 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
883 lgr %r2,%r11 # pass pointer to pt_regs
884 lghi %r3,EXT_INTERRUPT
889 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
892 stg %r14,(__SF_GPRS+8*8)(%r15)
893 stg %r3,__SF_EMPTY(%r15)
894 larl %r1,.Lpsw_idle_lpsw+4
895 stg %r1,__SF_EMPTY+8(%r15)
897 larl %r1,smp_cpu_mtid
901 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
905 STCK __CLOCK_IDLE_ENTER(%r2)
906 stpt __TIMER_IDLE_ENTER(%r2)
908 lpswe __SF_EMPTY(%r15)
913 * Store floating-point controls and floating-point or vector register
914 * depending whether the vector facility is available. A critical section
915 * cleanup assures that the registers are stored even if interrupted for
916 * some other work. The CIF_FPU flag is set to trigger a lazy restore
917 * of the register contents at return from io or a system call.
921 aghi %r2,__TASK_thread
922 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
923 jo .Lsave_fpu_regs_exit
924 stfpc __THREAD_FPU_fpc(%r2)
925 .Lsave_fpu_regs_fpc_end:
926 lg %r3,__THREAD_FPU_regs(%r2)
927 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
928 jz .Lsave_fpu_regs_fp # no -> store FP regs
929 .Lsave_fpu_regs_vx_low:
930 VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
931 .Lsave_fpu_regs_vx_high:
932 VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3)
933 j .Lsave_fpu_regs_done # -> set CIF_FPU flag
951 .Lsave_fpu_regs_done:
952 oi __LC_CPU_FLAGS+7,_CIF_FPU
953 .Lsave_fpu_regs_exit:
958 * Load floating-point controls and floating-point or vector registers.
959 * A critical section cleanup assures that the register contents are
960 * loaded even if interrupted for some other work.
962 * There are special calling conventions to fit into sysc and io return work:
963 * %r15: <kernel stack>
964 * The function requires:
969 aghi %r4,__TASK_thread
970 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
971 jno .Lload_fpu_regs_exit
972 lfpc __THREAD_FPU_fpc(%r4)
973 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
974 lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
975 jz .Lload_fpu_regs_fp # -> no VX, load FP regs
978 .Lload_fpu_regs_vx_high:
979 VLM %v16,%v31,256,%r4
980 j .Lload_fpu_regs_done
998 .Lload_fpu_regs_done:
999 ni __LC_CPU_FLAGS+7,255-_CIF_FPU
1000 .Lload_fpu_regs_exit:
1002 .Lload_fpu_regs_end:
1007 * Machine check handler routines
1009 ENTRY(mcck_int_handler)
1010 STCK __LC_MCCK_CLOCK
1012 la %r1,4095 # revalidate r1
1013 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
1014 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
1015 lg %r10,__LC_LAST_BREAK
1016 lg %r12,__LC_THREAD_INFO
1017 larl %r13,cleanup_critical
1018 lmg %r8,%r9,__LC_MCK_OLD_PSW
1019 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
1020 jo .Lmcck_panic # yes -> rest of mcck code invalid
1021 lghi %r14,__LC_CPU_TIMER_SAVE_AREA
1022 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1023 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
1025 la %r14,__LC_SYNC_ENTER_TIMER
1026 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
1028 la %r14,__LC_ASYNC_ENTER_TIMER
1029 0: clc 0(8,%r14),__LC_EXIT_TIMER
1031 la %r14,__LC_EXIT_TIMER
1032 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
1034 la %r14,__LC_LAST_UPDATE_TIMER
1036 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1037 3: TSTMSK __LC_MCCK_CODE,(MCCK_CODE_PSW_MWP_VALID|MCCK_CODE_PSW_IA_VALID)
1038 jno .Lmcck_panic # no -> skip cleanup critical
1039 SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
1041 lghi %r14,__LC_GPREGS_SAVE_AREA+64
1042 stmg %r0,%r7,__PT_R0(%r11)
1043 # clear user controlled registers to prevent speculative use
1053 mvc __PT_R8(64,%r11),0(%r14)
1054 stmg %r8,%r9,__PT_PSW(%r11)
1055 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1056 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1057 lgr %r2,%r11 # pass pointer to pt_regs
1058 brasl %r14,s390_do_machine_check
1059 tm __PT_PSW+1(%r11),0x01 # returning to user ?
1061 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
1062 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
1063 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
1064 la %r11,STACK_FRAME_OVERHEAD(%r1)
1066 ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off
1067 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
1070 brasl %r14,s390_handle_mcck
1073 lg %r14,__LC_VDSO_PER_CPU
1074 lmg %r0,%r10,__PT_R0(%r11)
1075 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1076 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
1078 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
1079 stpt __LC_EXIT_TIMER
1080 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
1081 0: lmg %r11,%r15,__PT_R11(%r11)
1082 lpswe __LC_RETURN_MCCK_PSW
1085 lg %r15,__LC_PANIC_STACK
1086 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
1090 # PSW restart interrupt handler
1092 ENTRY(restart_int_handler)
1093 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
1095 .insn s,0xb2800000,__LC_LPP
1096 0: stg %r15,__LC_SAVE_AREA_RESTART
1097 lg %r15,__LC_RESTART_STACK
1098 aghi %r15,-__PT_SIZE # create pt_regs on stack
1099 xc 0(__PT_SIZE,%r15),0(%r15)
1100 stmg %r0,%r14,__PT_R0(%r15)
1101 mvc __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
1102 mvc __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
1103 aghi %r15,-STACK_FRAME_OVERHEAD # create stack frame on stack
1104 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
1105 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
1106 lg %r2,__LC_RESTART_DATA
1107 lg %r3,__LC_RESTART_SOURCE
1108 ltgr %r3,%r3 # test source cpu address
1109 jm 1f # negative -> skip source stop
1110 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
1111 brc 10,0b # wait for status stored
1112 1: basr %r14,%r1 # call function
1113 stap __SF_EMPTY(%r15) # store cpu address
1114 llgh %r3,__SF_EMPTY(%r15)
1115 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
1119 .section .kprobes.text, "ax"
1121 #ifdef CONFIG_CHECK_STACK
1123 * The synchronous or the asynchronous stack overflowed. We are dead.
1124 * No need to properly save the registers, we are going to panic anyway.
1125 * Setup a pt_regs so that show_trace can provide a good call trace.
1128 lg %r15,__LC_PANIC_STACK # change to panic stack
1129 la %r11,STACK_FRAME_OVERHEAD(%r15)
1130 stmg %r0,%r7,__PT_R0(%r11)
1131 stmg %r8,%r9,__PT_PSW(%r11)
1132 mvc __PT_R8(64,%r11),0(%r14)
1133 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1134 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1135 lgr %r2,%r11 # pass pointer to pt_regs
1136 jg kernel_stack_overflow
1140 #if IS_ENABLED(CONFIG_KVM)
1141 clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap
1143 clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1146 clg %r9,BASED(.Lcleanup_table) # system_call
1148 clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc
1149 jl .Lcleanup_system_call
1150 clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif
1152 clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore
1153 jl .Lcleanup_sysc_tif
1154 clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done
1155 jl .Lcleanup_sysc_restore
1156 clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif
1158 clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore
1160 clg %r9,BASED(.Lcleanup_table+56) # .Lio_done
1161 jl .Lcleanup_io_restore
1162 clg %r9,BASED(.Lcleanup_table+64) # psw_idle
1164 clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end
1166 clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs
1168 clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end
1169 jl .Lcleanup_save_fpu_regs
1170 clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs
1172 clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
1173 jl .Lcleanup_load_fpu_regs
1181 .quad .Lsysc_restore
1187 .quad .Lpsw_idle_end
1189 .quad .Lsave_fpu_regs_end
1191 .quad .Lload_fpu_regs_end
1193 #if IS_ENABLED(CONFIG_KVM)
1194 .Lcleanup_table_sie:
1199 BPENTER __SF_EMPTY+24(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
1200 lg %r9,__SF_EMPTY(%r15) # get control block pointer
1201 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
1202 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
1203 larl %r9,sie_exit # skip forward to sie_exit
1207 .Lcleanup_system_call:
1208 # check if stpt has been executed
1209 clg %r9,BASED(.Lcleanup_system_call_insn)
1211 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1212 cghi %r11,__LC_SAVE_AREA_ASYNC
1214 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
1215 0: # check if stmg has been executed
1216 clg %r9,BASED(.Lcleanup_system_call_insn+8)
1218 mvc __LC_SAVE_AREA_SYNC(64),0(%r11)
1219 0: # check if base register setup + TIF bit load has been done
1220 clg %r9,BASED(.Lcleanup_system_call_insn+16)
1222 # set up saved registers r10 and r12
1223 stg %r10,16(%r11) # r10 last break
1224 stg %r12,32(%r11) # r12 thread-info pointer
1225 0: # check if the user time update has been done
1226 clg %r9,BASED(.Lcleanup_system_call_insn+24)
1228 lg %r15,__LC_EXIT_TIMER
1229 slg %r15,__LC_SYNC_ENTER_TIMER
1230 alg %r15,__LC_USER_TIMER
1231 stg %r15,__LC_USER_TIMER
1232 0: # check if the system time update has been done
1233 clg %r9,BASED(.Lcleanup_system_call_insn+32)
1235 lg %r15,__LC_LAST_UPDATE_TIMER
1236 slg %r15,__LC_EXIT_TIMER
1237 alg %r15,__LC_SYSTEM_TIMER
1238 stg %r15,__LC_SYSTEM_TIMER
1239 0: # update accounting time stamp
1240 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1245 mvc __TI_last_break(8,%r12),16(%r11)
1246 0: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
1247 # set up saved register r11
1248 lg %r15,__LC_KERNEL_STACK
1249 la %r9,STACK_FRAME_OVERHEAD(%r15)
1250 stg %r9,24(%r11) # r11 pt_regs pointer
1252 mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1253 stmg %r0,%r7,__PT_R0(%r9)
1254 mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1255 mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC
1256 xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1257 mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL
1258 # setup saved register r15
1259 stg %r15,56(%r11) # r15 stack pointer
1260 # set new psw address and exit
1261 larl %r9,.Lsysc_do_svc
1263 .Lcleanup_system_call_insn:
1267 .quad .Lsysc_vtime+36
1268 .quad .Lsysc_vtime+42
1274 .Lcleanup_sysc_restore:
1275 # check if stpt has been executed
1276 clg %r9,BASED(.Lcleanup_sysc_restore_insn)
1278 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1279 cghi %r11,__LC_SAVE_AREA_ASYNC
1281 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1282 0: clg %r9,BASED(.Lcleanup_sysc_restore_insn+8)
1284 lg %r9,24(%r11) # get saved pointer to pt_regs
1285 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1286 mvc 0(64,%r11),__PT_R8(%r9)
1287 lmg %r0,%r7,__PT_R0(%r9)
1288 1: lmg %r8,%r9,__LC_RETURN_PSW
1290 .Lcleanup_sysc_restore_insn:
1291 .quad .Lsysc_exit_timer
1292 .quad .Lsysc_done - 4
1298 .Lcleanup_io_restore:
1299 # check if stpt has been executed
1300 clg %r9,BASED(.Lcleanup_io_restore_insn)
1302 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1303 0: clg %r9,BASED(.Lcleanup_io_restore_insn+8)
1305 lg %r9,24(%r11) # get saved r11 pointer to pt_regs
1306 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1307 mvc 0(64,%r11),__PT_R8(%r9)
1308 lmg %r0,%r7,__PT_R0(%r9)
1309 1: lmg %r8,%r9,__LC_RETURN_PSW
1311 .Lcleanup_io_restore_insn:
1312 .quad .Lio_exit_timer
1316 # copy interrupt clock & cpu timer
1317 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1318 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1319 cghi %r11,__LC_SAVE_AREA_ASYNC
1321 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1322 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
1323 0: # check if stck & stpt have been executed
1324 clg %r9,BASED(.Lcleanup_idle_insn)
1326 mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1327 mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
1328 1: # calculate idle cycles
1330 clg %r9,BASED(.Lcleanup_idle_insn)
1332 larl %r1,smp_cpu_mtid
1336 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1338 ag %r3,__LC_PERCPU_OFFSET
1339 la %r4,__SF_EMPTY+16(%r15)
1348 3: # account system time going idle
1349 lg %r9,__LC_STEAL_TIMER
1350 alg %r9,__CLOCK_IDLE_ENTER(%r2)
1351 slg %r9,__LC_LAST_UPDATE_CLOCK
1352 stg %r9,__LC_STEAL_TIMER
1353 mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1354 lg %r9,__LC_SYSTEM_TIMER
1355 alg %r9,__LC_LAST_UPDATE_TIMER
1356 slg %r9,__TIMER_IDLE_ENTER(%r2)
1357 stg %r9,__LC_SYSTEM_TIMER
1358 mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1359 # prepare return psw
1360 nihh %r8,0xfcfd # clear irq & wait state bits
1361 lg %r9,48(%r11) # return from psw_idle
1363 .Lcleanup_idle_insn:
1364 .quad .Lpsw_idle_lpsw
1366 .Lcleanup_save_fpu_regs:
1367 larl %r9,save_fpu_regs
1370 .Lcleanup_load_fpu_regs:
1371 larl %r9,load_fpu_regs
1379 .quad .L__critical_start
1381 .quad .L__critical_end - .L__critical_start
1382 #if IS_ENABLED(CONFIG_KVM)
1383 .Lsie_critical_start:
1385 .Lsie_critical_length:
1386 .quad .Lsie_done - .Lsie_gmap
1388 .section .rodata, "a"
1389 #define SYSCALL(esame,emu) .long esame
1390 .globl sys_call_table
1392 #include "syscalls.S"
1395 #ifdef CONFIG_COMPAT
1397 #define SYSCALL(esame,emu) .long emu
1398 .globl sys_call_table_emu
1400 #include "syscalls.S"