arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <linux/serial_sci.h>
  18 #include <generated/machtypes.h>
  19
  20 static struct resource rtc_resources[] = {
  21         [0] = {
  22                 .start  = 0xffc80000,
  23                 .end    = 0xffc80000 + 0x58 - 1,
  24                 .flags  = IORESOURCE_IO,
  25         },
  26         [1] = {
  27                 /* Shared Period/Carry/Alarm IRQ */
  28                 .start  = evt2irq(0x480),
  29                 .flags  = IORESOURCE_IRQ,
  30         },
  31 };
  32
  33 static struct platform_device rtc_device = {
  34         .name           = "sh-rtc",
  35         .id             = -1,
  36         .num_resources  = ARRAY_SIZE(rtc_resources),
  37         .resource       = rtc_resources,
  38 };
  39
  40 static struct plat_sci_port sci_platform_data = {
  41         .type           = PORT_SCI,
  42 };
  43
  44 static struct resource sci_resources[] = {
  45         DEFINE_RES_MEM(0xffe00000, 0x20),
  46         DEFINE_RES_IRQ(evt2irq(0x4e0)),
  47 };
  48
  49 static struct platform_device sci_device = {
  50         .name           = "sh-sci",
  51         .id             = 0,
  52         .resource       = sci_resources,
  53         .num_resources  = ARRAY_SIZE(sci_resources),
  54         .dev            = {
  55                 .platform_data  = &sci_platform_data,
  56         },
  57 };
  58
  59 static struct plat_sci_port scif_platform_data = {
  60         .scscr          = SCSCR_REIE,
  61         .type           = PORT_SCIF,
  62 };
  63
  64 static struct resource scif_resources[] = {
  65         DEFINE_RES_MEM(0xffe80000, 0x100),
  66         DEFINE_RES_IRQ(evt2irq(0x700)),
  67 };
  68
  69 static struct platform_device scif_device = {
  70         .name           = "sh-sci",
  71         .id             = 1,
  72         .resource       = scif_resources,
  73         .num_resources  = ARRAY_SIZE(scif_resources),
  74         .dev            = {
  75                 .platform_data  = &scif_platform_data,
  76         },
  77 };
  78
  79 static struct sh_timer_config tmu0_platform_data = {
  80         .channels_mask = 7,
  81 };
  82
  83 static struct resource tmu0_resources[] = {
  84         DEFINE_RES_MEM(0xffd80000, 0x30),
  85         DEFINE_RES_IRQ(evt2irq(0x400)),
  86         DEFINE_RES_IRQ(evt2irq(0x420)),
  87         DEFINE_RES_IRQ(evt2irq(0x440)),
  88 };
  89
  90 static struct platform_device tmu0_device = {
  91         .name           = "sh-tmu",
  92         .id             = 0,
  93         .dev = {
  94                 .platform_data  = &tmu0_platform_data,
  95         },
  96         .resource       = tmu0_resources,
  97         .num_resources  = ARRAY_SIZE(tmu0_resources),
  98 };
  99
 100 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 101 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 102         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 103         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 104
 105 static struct sh_timer_config tmu1_platform_data = {
 106         .channels_mask = 3,
 107 };
 108
 109 static struct resource tmu1_resources[] = {
 110         DEFINE_RES_MEM(0xfe100000, 0x20),
 111         DEFINE_RES_IRQ(evt2irq(0xb00)),
 112         DEFINE_RES_IRQ(evt2irq(0xb80)),
 113 };
 114
 115 static struct platform_device tmu1_device = {
 116         .name           = "sh-tmu",
 117         .id             = 1,
 118         .dev = {
 119                 .platform_data  = &tmu1_platform_data,
 120         },
 121         .resource       = tmu1_resources,
 122         .num_resources  = ARRAY_SIZE(tmu1_resources),
 123 };
 124
 125 #endif
 126
 127 static struct platform_device *sh7750_devices[] __initdata = {
 128         &rtc_device,
 129         &tmu0_device,
 130 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 131         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 132         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 133         &tmu1_device,
 134 #endif
 135 };
 136
 137 static int __init sh7750_devices_setup(void)
 138 {
 139         if (mach_is_rts7751r2d()) {
 140                 platform_device_register(&scif_device);
 141         } else {
 142                 platform_device_register(&sci_device);
 143                 platform_device_register(&scif_device);
 144         }
 145
 146         return platform_add_devices(sh7750_devices,
 147                                     ARRAY_SIZE(sh7750_devices));
 148 }
 149 arch_initcall(sh7750_devices_setup);
 150
 151 static struct platform_device *sh7750_early_devices[] __initdata = {
 152         &tmu0_device,
 153 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 154         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 155         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 156         &tmu1_device,
 157 #endif
 158 };
 159
 160 void __init plat_early_device_setup(void)
 161 {
 162         struct platform_device *dev[1];
 163
 164         if (mach_is_rts7751r2d()) {
 165                 scif_platform_data.scscr |= SCSCR_CKE1;
 166                 dev[0] = &scif_device;
 167                 early_platform_add_devices(dev, 1);
 168         } else {
 169                 dev[0] = &sci_device;
 170                 early_platform_add_devices(dev, 1);
 171                 dev[0] = &scif_device;
 172                 early_platform_add_devices(dev, 1);
 173         }
 174
 175         early_platform_add_devices(sh7750_early_devices,
 176                                    ARRAY_SIZE(sh7750_early_devices));
 177 }
 178
 179 enum {
 180         UNUSED = 0,
 181
 182         /* interrupt sources */
 183         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 184         HUDI, GPIOI, DMAC,
 185         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 186         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 187         TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
 188
 189         /* interrupt groups */
 190         PCIC1,
 191 };
 192
 193 static struct intc_vect vectors[] __initdata = {
 194         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 195         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 196         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 197         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 198         INTC_VECT(RTC, 0x4c0),
 199         INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
 200         INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
 201         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 202         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 203         INTC_VECT(WDT, 0x560),
 204         INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 205 };
 206
 207 static struct intc_prio_reg prio_registers[] __initdata = {
 208         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 209         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 210         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 211         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 212         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 213                                                  TMU4, TMU3,
 214                                                  PCIC1, PCIC0_PCISERR } },
 215 };
 216
 217 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
 218                          NULL, prio_registers, NULL);
 219
 220 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 221 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 222         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 223         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 224         defined(CONFIG_CPU_SUBTYPE_SH7091)
 225 static struct intc_vect vectors_dma4[] __initdata = {
 226         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 227         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 228         INTC_VECT(DMAC, 0x6c0),
 229 };
 230
 231 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 232                          vectors_dma4, NULL,
 233                          NULL, prio_registers, NULL);
 234 #endif
 235
 236 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 237 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 238 static struct intc_vect vectors_dma8[] __initdata = {
 239         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 240         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 241         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 242         INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
 243         INTC_VECT(DMAC, 0x6c0),
 244 };
 245
 246 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 247                          vectors_dma8, NULL,
 248                          NULL, prio_registers, NULL);
 249 #endif
 250
 251 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 252 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 253         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 254         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 255 static struct intc_vect vectors_tmu34[] __initdata = {
 256         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 257 };
 258
 259 static struct intc_mask_reg mask_registers[] __initdata = {
 260         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 261           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 262             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 263             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 264             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 265             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 266 };
 267
 268 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 269                          vectors_tmu34, NULL,
 270                          mask_registers, prio_registers, NULL);
 271 #endif
 272
 273 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 274 static struct intc_vect vectors_irlm[] __initdata = {
 275         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 276         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 277 };
 278
 279 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 280                          NULL, prio_registers, NULL);
 281
 282 /* SH7751 and SH7751R both have PCI */
 283 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 284 static struct intc_vect vectors_pci[] __initdata = {
 285         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 286         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 287         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 288         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 289 };
 290
 291 static struct intc_group groups_pci[] __initdata = {
 292         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 293                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 294 };
 295
 296 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 297                          mask_registers, prio_registers, NULL);
 298 #endif
 299
 300 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 301         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 302         defined(CONFIG_CPU_SUBTYPE_SH7091)
 303 void __init plat_irq_setup(void)
 304 {
 305         /*
 306          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 307          * see below..
 308          */
 309         register_intc_controller(&intc_desc);
 310         register_intc_controller(&intc_desc_dma4);
 311 }
 312 #endif
 313
 314 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 315 void __init plat_irq_setup(void)
 316 {
 317         register_intc_controller(&intc_desc);
 318         register_intc_controller(&intc_desc_dma8);
 319         register_intc_controller(&intc_desc_tmu34);
 320 }
 321 #endif
 322
 323 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 324 void __init plat_irq_setup(void)
 325 {
 326         register_intc_controller(&intc_desc);
 327         register_intc_controller(&intc_desc_dma4);
 328         register_intc_controller(&intc_desc_tmu34);
 329         register_intc_controller(&intc_desc_pci);
 330 }
 331 #endif
 332
 333 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 334 void __init plat_irq_setup(void)
 335 {
 336         register_intc_controller(&intc_desc);
 337         register_intc_controller(&intc_desc_dma8);
 338         register_intc_controller(&intc_desc_tmu34);
 339         register_intc_controller(&intc_desc_pci);
 340 }
 341 #endif
 342
 343 #define INTC_ICR        0xffd00000UL
 344 #define INTC_ICR_IRLM   (1<<7)
 345
 346 void __init plat_irq_setup_pins(int mode)
 347 {
 348 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 349         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 350         return;
 351 #endif
 352
 353         switch (mode) {
 354         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 355                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 356                 register_intc_controller(&intc_desc_irlm);
 357                 break;
 358         default:
 359                 BUG();
 360         }
 361 }