arch/sparc/include/asm/mmu_context_64.h

   1 #ifndef __SPARC64_MMU_CONTEXT_H
   2 #define __SPARC64_MMU_CONTEXT_H
   3
   4 /* Derived heavily from Linus's Alpha/AXP ASN code... */
   5
   6 #ifndef __ASSEMBLY__
   7
   8 #include <linux/spinlock.h>
   9 #include <asm/spitfire.h>
  10 #include <asm-generic/mm_hooks.h>
  11
  12 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  13 {
  14 }
  15
  16 extern spinlock_t ctx_alloc_lock;
  17 extern unsigned long tlb_context_cache;
  18 extern unsigned long mmu_context_bmap[];
  19
  20 DECLARE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm);
  21 void get_new_mmu_context(struct mm_struct *mm);
  22 int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
  23 void destroy_context(struct mm_struct *mm);
  24
  25 void __tsb_context_switch(unsigned long pgd_pa,
  26                           struct tsb_config *tsb_base,
  27                           struct tsb_config *tsb_huge,
  28                           unsigned long tsb_descr_pa,
  29                           unsigned long secondary_ctx);
  30
  31 static inline void tsb_context_switch_ctx(struct mm_struct *mm,
  32                                           unsigned long ctx)
  33 {
  34         __tsb_context_switch(__pa(mm->pgd),
  35                              &mm->context.tsb_block[0],
  36 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
  37                              (mm->context.tsb_block[1].tsb ?
  38                               &mm->context.tsb_block[1] :
  39                               NULL)
  40 #else
  41                              NULL
  42 #endif
  43                              , __pa(&mm->context.tsb_descr[0]),
  44                              ctx);
  45 }
  46
  47 #define tsb_context_switch(X) tsb_context_switch_ctx(X, 0)
  48
  49 void tsb_grow(struct mm_struct *mm,
  50               unsigned long tsb_index,
  51               unsigned long mm_rss);
  52 #ifdef CONFIG_SMP
  53 void smp_tsb_sync(struct mm_struct *mm);
  54 #else
  55 #define smp_tsb_sync(__mm) do { } while (0)
  56 #endif
  57
  58 /* Set MMU context in the actual hardware. */
  59 #define load_secondary_context(__mm) \
  60         __asm__ __volatile__( \
  61         "\n661: stxa            %0, [%1] %2\n" \
  62         "       .section        .sun4v_1insn_patch, \"ax\"\n" \
  63         "       .word           661b\n" \
  64         "       stxa            %0, [%1] %3\n" \
  65         "       .previous\n" \
  66         "       flush           %%g6\n" \
  67         : /* No outputs */ \
  68         : "r" (CTX_HWBITS((__mm)->context)), \
  69           "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
  70
  71 void __flush_tlb_mm(unsigned long, unsigned long);
  72
  73 /* Switch the current MM context. */
  74 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
  75 {
  76         unsigned long ctx_valid, flags;
  77         int cpu = smp_processor_id();
  78
  79         per_cpu(per_cpu_secondary_mm, cpu) = mm;
  80         if (unlikely(mm == &init_mm))
  81                 return;
  82
  83         spin_lock_irqsave(&mm->context.lock, flags);
  84         ctx_valid = CTX_VALID(mm->context);
  85         if (!ctx_valid)
  86                 get_new_mmu_context(mm);
  87
  88         /* We have to be extremely careful here or else we will miss
  89          * a TSB grow if we switch back and forth between a kernel
  90          * thread and an address space which has it's TSB size increased
  91          * on another processor.
  92          *
  93          * It is possible to play some games in order to optimize the
  94          * switch, but the safest thing to do is to unconditionally
  95          * perform the secondary context load and the TSB context switch.
  96          *
  97          * For reference the bad case is, for address space "A":
  98          *
  99          *              CPU 0                   CPU 1
 100          *      run address space A
 101          *      set cpu0's bits in cpu_vm_mask
 102          *      switch to kernel thread, borrow
 103          *      address space A via entry_lazy_tlb
 104          *                                      run address space A
 105          *                                      set cpu1's bit in cpu_vm_mask
 106          *                                      flush_tlb_pending()
 107          *                                      reset cpu_vm_mask to just cpu1
 108          *                                      TSB grow
 109          *      run address space A
 110          *      context was valid, so skip
 111          *      TSB context switch
 112          *
 113          * At that point cpu0 continues to use a stale TSB, the one from
 114          * before the TSB grow performed on cpu1.  cpu1 did not cross-call
 115          * cpu0 to update it's TSB because at that point the cpu_vm_mask
 116          * only had cpu1 set in it.
 117          */
 118         tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
 119
 120         /* Any time a processor runs a context on an address space
 121          * for the first time, we must flush that context out of the
 122          * local TLB.
 123          */
 124         if (!ctx_valid || !cpumask_test_cpu(cpu, mm_cpumask(mm))) {
 125                 cpumask_set_cpu(cpu, mm_cpumask(mm));
 126                 __flush_tlb_mm(CTX_HWBITS(mm->context),
 127                                SECONDARY_CONTEXT);
 128         }
 129         spin_unlock_irqrestore(&mm->context.lock, flags);
 130 }
 131
 132 #define deactivate_mm(tsk,mm)   do { } while (0)
 133 #define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL)
 134 #endif /* !(__ASSEMBLY__) */
 135
 136 #endif /* !(__SPARC64_MMU_CONTEXT_H) */