arch/x86/events/msr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/perf_event.h>
   3 #include <linux/nospec.h>
   4 #include <asm/intel-family.h>
   5
   6 enum perf_msr_id {
   7         PERF_MSR_TSC                    = 0,
   8         PERF_MSR_APERF                  = 1,
   9         PERF_MSR_MPERF                  = 2,
  10         PERF_MSR_PPERF                  = 3,
  11         PERF_MSR_SMI                    = 4,
  12         PERF_MSR_PTSC                   = 5,
  13         PERF_MSR_IRPERF                 = 6,
  14         PERF_MSR_THERM                  = 7,
  15         PERF_MSR_THERM_SNAP             = 8,
  16         PERF_MSR_THERM_UNIT             = 9,
  17         PERF_MSR_EVENT_MAX,
  18 };
  19
  20 static bool test_aperfmperf(int idx)
  21 {
  22         return boot_cpu_has(X86_FEATURE_APERFMPERF);
  23 }
  24
  25 static bool test_ptsc(int idx)
  26 {
  27         return boot_cpu_has(X86_FEATURE_PTSC);
  28 }
  29
  30 static bool test_irperf(int idx)
  31 {
  32         return boot_cpu_has(X86_FEATURE_IRPERF);
  33 }
  34
  35 static bool test_therm_status(int idx)
  36 {
  37         return boot_cpu_has(X86_FEATURE_DTHERM);
  38 }
  39
  40 static bool test_intel(int idx)
  41 {
  42         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
  43             boot_cpu_data.x86 != 6)
  44                 return false;
  45
  46         switch (boot_cpu_data.x86_model) {
  47         case INTEL_FAM6_NEHALEM:
  48         case INTEL_FAM6_NEHALEM_G:
  49         case INTEL_FAM6_NEHALEM_EP:
  50         case INTEL_FAM6_NEHALEM_EX:
  51
  52         case INTEL_FAM6_WESTMERE:
  53         case INTEL_FAM6_WESTMERE_EP:
  54         case INTEL_FAM6_WESTMERE_EX:
  55
  56         case INTEL_FAM6_SANDYBRIDGE:
  57         case INTEL_FAM6_SANDYBRIDGE_X:
  58
  59         case INTEL_FAM6_IVYBRIDGE:
  60         case INTEL_FAM6_IVYBRIDGE_X:
  61
  62         case INTEL_FAM6_HASWELL_CORE:
  63         case INTEL_FAM6_HASWELL_X:
  64         case INTEL_FAM6_HASWELL_ULT:
  65         case INTEL_FAM6_HASWELL_GT3E:
  66
  67         case INTEL_FAM6_BROADWELL_CORE:
  68         case INTEL_FAM6_BROADWELL_XEON_D:
  69         case INTEL_FAM6_BROADWELL_GT3E:
  70         case INTEL_FAM6_BROADWELL_X:
  71
  72         case INTEL_FAM6_ATOM_SILVERMONT:
  73         case INTEL_FAM6_ATOM_SILVERMONT_X:
  74         case INTEL_FAM6_ATOM_AIRMONT:
  75
  76         case INTEL_FAM6_ATOM_GOLDMONT:
  77         case INTEL_FAM6_ATOM_GOLDMONT_X:
  78
  79         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
  80
  81         case INTEL_FAM6_XEON_PHI_KNL:
  82         case INTEL_FAM6_XEON_PHI_KNM:
  83                 if (idx == PERF_MSR_SMI)
  84                         return true;
  85                 break;
  86
  87         case INTEL_FAM6_SKYLAKE_MOBILE:
  88         case INTEL_FAM6_SKYLAKE_DESKTOP:
  89         case INTEL_FAM6_SKYLAKE_X:
  90         case INTEL_FAM6_KABYLAKE_MOBILE:
  91         case INTEL_FAM6_KABYLAKE_DESKTOP:
  92         case INTEL_FAM6_ICELAKE_MOBILE:
  93                 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
  94                         return true;
  95                 break;
  96         }
  97
  98         return false;
  99 }
 100
 101 struct perf_msr {
 102         u64     msr;
 103         struct  perf_pmu_events_attr *attr;
 104         bool    (*test)(int idx);
 105 };
 106
 107 PMU_EVENT_ATTR_STRING(tsc,                              evattr_tsc,             "event=0x00"    );
 108 PMU_EVENT_ATTR_STRING(aperf,                            evattr_aperf,           "event=0x01"    );
 109 PMU_EVENT_ATTR_STRING(mperf,                            evattr_mperf,           "event=0x02"    );
 110 PMU_EVENT_ATTR_STRING(pperf,                            evattr_pperf,           "event=0x03"    );
 111 PMU_EVENT_ATTR_STRING(smi,                              evattr_smi,             "event=0x04"    );
 112 PMU_EVENT_ATTR_STRING(ptsc,                             evattr_ptsc,            "event=0x05"    );
 113 PMU_EVENT_ATTR_STRING(irperf,                           evattr_irperf,          "event=0x06"    );
 114 PMU_EVENT_ATTR_STRING(cpu_thermal_margin,               evattr_therm,           "event=0x07"    );
 115 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot,      evattr_therm_snap,      "1"             );
 116 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit,          evattr_therm_unit,      "C"             );
 117
 118 static struct perf_msr msr[] = {
 119         [PERF_MSR_TSC]          = { 0,                          &evattr_tsc,            NULL,                   },
 120         [PERF_MSR_APERF]        = { MSR_IA32_APERF,             &evattr_aperf,          test_aperfmperf,        },
 121         [PERF_MSR_MPERF]        = { MSR_IA32_MPERF,             &evattr_mperf,          test_aperfmperf,        },
 122         [PERF_MSR_PPERF]        = { MSR_PPERF,                  &evattr_pperf,          test_intel,             },
 123         [PERF_MSR_SMI]          = { MSR_SMI_COUNT,              &evattr_smi,            test_intel,             },
 124         [PERF_MSR_PTSC]         = { MSR_F15H_PTSC,              &evattr_ptsc,           test_ptsc,              },
 125         [PERF_MSR_IRPERF]       = { MSR_F17H_IRPERF,            &evattr_irperf,         test_irperf,            },
 126         [PERF_MSR_THERM]        = { MSR_IA32_THERM_STATUS,      &evattr_therm,          test_therm_status,      },
 127         [PERF_MSR_THERM_SNAP]   = { MSR_IA32_THERM_STATUS,      &evattr_therm_snap,     test_therm_status,      },
 128         [PERF_MSR_THERM_UNIT]   = { MSR_IA32_THERM_STATUS,      &evattr_therm_unit,     test_therm_status,      },
 129 };
 130
 131 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
 132         NULL,
 133 };
 134
 135 static struct attribute_group events_attr_group = {
 136         .name = "events",
 137         .attrs = events_attrs,
 138 };
 139
 140 PMU_FORMAT_ATTR(event, "config:0-63");
 141 static struct attribute *format_attrs[] = {
 142         &format_attr_event.attr,
 143         NULL,
 144 };
 145 static struct attribute_group format_attr_group = {
 146         .name = "format",
 147         .attrs = format_attrs,
 148 };
 149
 150 static const struct attribute_group *attr_groups[] = {
 151         &events_attr_group,
 152         &format_attr_group,
 153         NULL,
 154 };
 155
 156 static int msr_event_init(struct perf_event *event)
 157 {
 158         u64 cfg = event->attr.config;
 159
 160         if (event->attr.type != event->pmu->type)
 161                 return -ENOENT;
 162
 163         /* unsupported modes and filters */
 164         if (event->attr.exclude_user   ||
 165             event->attr.exclude_kernel ||
 166             event->attr.exclude_hv     ||
 167             event->attr.exclude_idle   ||
 168             event->attr.exclude_host   ||
 169             event->attr.exclude_guest  ||
 170             event->attr.sample_period) /* no sampling */
 171                 return -EINVAL;
 172
 173         if (cfg >= PERF_MSR_EVENT_MAX)
 174                 return -EINVAL;
 175
 176         cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
 177
 178         if (!msr[cfg].attr)
 179                 return -EINVAL;
 180
 181         event->hw.idx           = -1;
 182         event->hw.event_base    = msr[cfg].msr;
 183         event->hw.config        = cfg;
 184
 185         return 0;
 186 }
 187
 188 static inline u64 msr_read_counter(struct perf_event *event)
 189 {
 190         u64 now;
 191
 192         if (event->hw.event_base)
 193                 rdmsrl(event->hw.event_base, now);
 194         else
 195                 now = rdtsc_ordered();
 196
 197         return now;
 198 }
 199
 200 static void msr_event_update(struct perf_event *event)
 201 {
 202         u64 prev, now;
 203         s64 delta;
 204
 205         /* Careful, an NMI might modify the previous event value: */
 206 again:
 207         prev = local64_read(&event->hw.prev_count);
 208         now = msr_read_counter(event);
 209
 210         if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
 211                 goto again;
 212
 213         delta = now - prev;
 214         if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
 215                 delta = sign_extend64(delta, 31);
 216                 local64_add(delta, &event->count);
 217         } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
 218                 /* If valid, extract digital readout, otherwise set to -1: */
 219                 now = now & (1ULL << 31) ? (now >> 16) & 0x3f :  -1;
 220                 local64_set(&event->count, now);
 221         } else {
 222                 local64_add(delta, &event->count);
 223         }
 224 }
 225
 226 static void msr_event_start(struct perf_event *event, int flags)
 227 {
 228         u64 now = msr_read_counter(event);
 229
 230         local64_set(&event->hw.prev_count, now);
 231 }
 232
 233 static void msr_event_stop(struct perf_event *event, int flags)
 234 {
 235         msr_event_update(event);
 236 }
 237
 238 static void msr_event_del(struct perf_event *event, int flags)
 239 {
 240         msr_event_stop(event, PERF_EF_UPDATE);
 241 }
 242
 243 static int msr_event_add(struct perf_event *event, int flags)
 244 {
 245         if (flags & PERF_EF_START)
 246                 msr_event_start(event, flags);
 247
 248         return 0;
 249 }
 250
 251 static struct pmu pmu_msr = {
 252         .task_ctx_nr    = perf_sw_context,
 253         .attr_groups    = attr_groups,
 254         .event_init     = msr_event_init,
 255         .add            = msr_event_add,
 256         .del            = msr_event_del,
 257         .start          = msr_event_start,
 258         .stop           = msr_event_stop,
 259         .read           = msr_event_update,
 260         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT,
 261 };
 262
 263 static int __init msr_init(void)
 264 {
 265         int i, j = 0;
 266
 267         if (!boot_cpu_has(X86_FEATURE_TSC)) {
 268                 pr_cont("no MSR PMU driver.\n");
 269                 return 0;
 270         }
 271
 272         /* Probe the MSRs. */
 273         for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
 274                 u64 val;
 275
 276                 /* Virt sucks; you cannot tell if a R/O MSR is present :/ */
 277                 if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
 278                         msr[i].attr = NULL;
 279         }
 280
 281         /* List remaining MSRs in the sysfs attrs. */
 282         for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
 283                 if (msr[i].attr)
 284                         events_attrs[j++] = &msr[i].attr->attr.attr;
 285         }
 286         events_attrs[j] = NULL;
 287
 288         perf_pmu_register(&pmu_msr, "msr", -1);
 289
 290         return 0;
 291 }
 292 device_initcall(msr_init);