1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/apicdef.h>
10 #include <linux/atomic.h>
11 #include <asm/fixmap.h>
12 #include <asm/mpspec.h>
15 #include <asm/hardirq.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
26 /* Macros for apic_extnmi which controls external NMI masking */
27 #define APIC_EXTNMI_BSP 0 /* Default */
28 #define APIC_EXTNMI_ALL 1
29 #define APIC_EXTNMI_NONE 2
32 * Define the default level of output to be very little
33 * This can be turned up by using apic=verbose for more
34 * information and apic=debug for _lots_ of information.
35 * apic_verbosity is defined in apic.c
37 #define apic_printk(v, s, a...) do { \
38 if ((v) <= apic_verbosity) \
43 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
44 extern void generic_apic_probe(void);
46 static inline void generic_apic_probe(void)
51 #ifdef CONFIG_X86_LOCAL_APIC
53 extern int apic_verbosity;
54 extern int local_apic_timer_c2_ok;
56 extern int disable_apic;
57 extern unsigned int lapic_timer_frequency;
60 extern void __inquire_remote_apic(int apicid);
61 #else /* CONFIG_SMP */
62 static inline void __inquire_remote_apic(int apicid)
65 #endif /* CONFIG_SMP */
67 static inline void default_inquire_remote_apic(int apicid)
69 if (apic_verbosity >= APIC_DEBUG)
70 __inquire_remote_apic(apicid);
74 * With 82489DX we can't rely on apic feature bit
75 * retrieved via cpuid but still have to deal with
76 * such an apic chip so we assume that SMP configuration
77 * is found from MP table (64bit case uses ACPI mostly
78 * which set smp presence flag as well so we are safe
79 * to use this helper too).
81 static inline bool apic_from_smp_config(void)
83 return smp_found_config && !disable_apic;
87 * Basic functions accessing APICs.
89 #ifdef CONFIG_PARAVIRT
90 #include <asm/paravirt.h>
93 extern int setup_profiling_timer(unsigned int);
95 static inline void native_apic_mem_write(u32 reg, u32 v)
97 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
99 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
100 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
101 ASM_OUTPUT2("0" (v), "m" (*addr)));
104 static inline u32 native_apic_mem_read(u32 reg)
106 return *((volatile u32 *)(APIC_BASE + reg));
109 extern void native_apic_wait_icr_idle(void);
110 extern u32 native_safe_apic_wait_icr_idle(void);
111 extern void native_apic_icr_write(u32 low, u32 id);
112 extern u64 native_apic_icr_read(void);
114 static inline bool apic_is_x2apic_enabled(void)
118 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
120 return msr & X2APIC_ENABLE;
123 extern void enable_IR_x2apic(void);
125 extern int get_physical_broadcast(void);
127 extern int lapic_get_maxlvt(void);
128 extern void clear_local_APIC(void);
129 extern void disconnect_bsp_APIC(int virt_wire_setup);
130 extern void disable_local_APIC(void);
131 extern void lapic_shutdown(void);
132 extern void sync_Arb_IDs(void);
133 extern void init_bsp_APIC(void);
134 extern void setup_local_APIC(void);
135 extern void init_apic_mappings(void);
136 void register_lapic_address(unsigned long address);
137 extern void setup_boot_APIC_clock(void);
138 extern void setup_secondary_APIC_clock(void);
139 extern void lapic_update_tsc_freq(void);
140 extern int APIC_init_uniprocessor(void);
143 static inline int apic_force_enable(unsigned long addr)
148 extern int apic_force_enable(unsigned long addr);
151 extern int apic_bsp_setup(bool upmode);
152 extern void apic_ap_setup(void);
155 * On 32bit this is mach-xxx local
158 extern int apic_is_clustered_box(void);
160 static inline int apic_is_clustered_box(void)
166 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
168 #else /* !CONFIG_X86_LOCAL_APIC */
169 static inline void lapic_shutdown(void) { }
170 #define local_apic_timer_c2_ok 1
171 static inline void init_apic_mappings(void) { }
172 static inline void disable_local_APIC(void) { }
173 # define setup_boot_APIC_clock x86_init_noop
174 # define setup_secondary_APIC_clock x86_init_noop
175 static inline void lapic_update_tsc_freq(void) { }
176 #endif /* !CONFIG_X86_LOCAL_APIC */
178 #ifdef CONFIG_X86_X2APIC
179 static inline void native_apic_msr_write(u32 reg, u32 v)
181 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
185 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
188 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
190 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
193 static inline u32 native_apic_msr_read(u32 reg)
200 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
204 static inline void native_x2apic_wait_icr_idle(void)
206 /* no need to wait for icr idle in x2apic */
210 static inline u32 native_safe_x2apic_wait_icr_idle(void)
212 /* no need to wait for icr idle in x2apic */
216 static inline void native_x2apic_icr_write(u32 low, u32 id)
218 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
221 static inline u64 native_x2apic_icr_read(void)
225 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
229 extern int x2apic_mode;
230 extern int x2apic_phys;
231 extern void __init check_x2apic(void);
232 extern void x2apic_setup(void);
233 static inline int x2apic_enabled(void)
235 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
238 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
239 #else /* !CONFIG_X86_X2APIC */
240 static inline void check_x2apic(void) { }
241 static inline void x2apic_setup(void) { }
242 static inline int x2apic_enabled(void) { return 0; }
244 #define x2apic_mode (0)
245 #define x2apic_supported() (0)
246 #endif /* !CONFIG_X86_X2APIC */
249 #define SET_APIC_ID(x) (apic->set_apic_id(x))
255 * Copyright 2004 James Cleverdon, IBM.
256 * Subject to the GNU Public License, v.2
258 * Generic APIC sub-arch data struct.
260 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
261 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
268 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
269 int (*apic_id_valid)(int apicid);
270 int (*apic_id_registered)(void);
272 u32 irq_delivery_mode;
275 const struct cpumask *(*target_cpus)(void);
280 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
282 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
283 const struct cpumask *mask);
284 void (*init_apic_ldr)(void);
286 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
288 void (*setup_apic_routing)(void);
289 int (*cpu_present_to_apicid)(int mps_cpu);
290 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
291 int (*check_phys_apicid_present)(int phys_apicid);
292 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
294 unsigned int (*get_apic_id)(unsigned long x);
295 unsigned long (*set_apic_id)(unsigned int id);
297 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
298 const struct cpumask *andmask,
299 unsigned int *apicid);
302 void (*send_IPI)(int cpu, int vector);
303 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
304 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
306 void (*send_IPI_allbutself)(int vector);
307 void (*send_IPI_all)(int vector);
308 void (*send_IPI_self)(int vector);
310 /* wakeup_secondary_cpu */
311 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
313 void (*inquire_remote_apic)(int apicid);
316 u32 (*read)(u32 reg);
317 void (*write)(u32 reg, u32 v);
319 * ->eoi_write() has the same signature as ->write().
321 * Drivers can support both ->eoi_write() and ->write() by passing the same
322 * callback value. Kernel can override ->eoi_write() and fall back
325 void (*eoi_write)(u32 reg, u32 v);
326 u64 (*icr_read)(void);
327 void (*icr_write)(u32 low, u32 high);
328 void (*wait_icr_idle)(void);
329 u32 (*safe_wait_icr_idle)(void);
333 * Called very early during boot from get_smp_config(). It should
334 * return the logical apicid. x86_[bios]_cpu_to_apicid is
335 * initialized before this function is called.
337 * If logical apicid can't be determined that early, the function
338 * may return BAD_APICID. Logical apicid will be configured after
339 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
340 * won't be applied properly during early boot in this case.
342 int (*x86_32_early_logical_apicid)(int cpu);
347 * Pointer to the local APIC driver in use on this system (there's
348 * always just one such driver in use - the kernel decides via an
349 * early probing process which one it picks - and then sticks to it):
351 extern struct apic *apic;
354 * APIC drivers are probed based on how they are listed in the .apicdrivers
355 * section. So the order is important and enforced by the ordering
356 * of different apic driver files in the Makefile.
358 * For the files having two apic drivers, we use apic_drivers()
359 * to enforce the order with in them.
361 #define apic_driver(sym) \
362 static const struct apic *__apicdrivers_##sym __used \
363 __aligned(sizeof(struct apic *)) \
364 __section(.apicdrivers) = { &sym }
366 #define apic_drivers(sym1, sym2) \
367 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
368 __aligned(sizeof(struct apic *)) \
369 __section(.apicdrivers) = { &sym1, &sym2 }
371 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
374 * APIC functionality to boot other CPUs - only used on SMP:
377 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
380 #ifdef CONFIG_X86_LOCAL_APIC
382 static inline u32 apic_read(u32 reg)
384 return apic->read(reg);
387 static inline void apic_write(u32 reg, u32 val)
389 apic->write(reg, val);
392 static inline void apic_eoi(void)
394 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
397 static inline u64 apic_icr_read(void)
399 return apic->icr_read();
402 static inline void apic_icr_write(u32 low, u32 high)
404 apic->icr_write(low, high);
407 static inline void apic_wait_icr_idle(void)
409 apic->wait_icr_idle();
412 static inline u32 safe_apic_wait_icr_idle(void)
414 return apic->safe_wait_icr_idle();
417 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
419 #else /* CONFIG_X86_LOCAL_APIC */
421 static inline u32 apic_read(u32 reg) { return 0; }
422 static inline void apic_write(u32 reg, u32 val) { }
423 static inline void apic_eoi(void) { }
424 static inline u64 apic_icr_read(void) { return 0; }
425 static inline void apic_icr_write(u32 low, u32 high) { }
426 static inline void apic_wait_icr_idle(void) { }
427 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
428 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
430 #endif /* CONFIG_X86_LOCAL_APIC */
432 static inline void ack_APIC_irq(void)
435 * ack_APIC_irq() actually gets compiled as a single instruction
441 static inline unsigned default_get_apic_id(unsigned long x)
443 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
445 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
446 return (x >> 24) & 0xFF;
448 return (x >> 24) & 0x0F;
452 * Warm reset vector position:
454 #define TRAMPOLINE_PHYS_LOW 0x467
455 #define TRAMPOLINE_PHYS_HIGH 0x469
458 extern void apic_send_IPI_self(int vector);
460 DECLARE_PER_CPU(int, x2apic_extra_bits);
462 extern int default_cpu_present_to_apicid(int mps_cpu);
463 extern int default_check_phys_apicid_present(int phys_apicid);
466 extern void generic_bigsmp_probe(void);
469 #ifdef CONFIG_X86_LOCAL_APIC
473 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
475 static inline const struct cpumask *default_target_cpus(void)
478 return cpu_online_mask;
480 return cpumask_of(0);
484 static inline const struct cpumask *online_target_cpus(void)
486 return cpu_online_mask;
489 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
492 static inline unsigned int read_apic_id(void)
496 reg = apic_read(APIC_ID);
498 return apic->get_apic_id(reg);
501 static inline int default_apic_id_valid(int apicid)
503 return (apicid < 255);
506 extern int default_acpi_madt_oem_check(char *, char *);
508 extern void default_setup_apic_routing(void);
510 extern struct apic apic_noop;
514 static inline int noop_x86_32_early_logical_apicid(int cpu)
520 * Set up the logical destination ID.
522 * Intel recommends to set DFR, LDR and TPR before enabling
523 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
524 * document number 292116). So here it goes...
526 extern void default_init_apic_ldr(void);
528 static inline int default_apic_id_registered(void)
530 return physid_isset(read_apic_id(), phys_cpu_present_map);
533 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
535 return cpuid_apic >> index_msb;
541 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
542 const struct cpumask *andmask,
543 unsigned int *apicid)
545 unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
546 cpumask_bits(andmask)[0] &
547 cpumask_bits(cpu_online_mask)[0] &
550 if (likely(cpu_mask)) {
551 *apicid = (unsigned int)cpu_mask;
559 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
560 const struct cpumask *andmask,
561 unsigned int *apicid);
564 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
565 const struct cpumask *mask)
567 /* Careful. Some cpus do not strictly honor the set of cpus
568 * specified in the interrupt destination when using lowest
569 * priority interrupt delivery mode.
571 * In particular there was a hyperthreading cpu observed to
572 * deliver interrupts to the wrong hyperthread when only one
573 * hyperthread was specified in the interrupt desitination.
575 cpumask_clear(retmask);
576 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
580 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
581 const struct cpumask *mask)
583 cpumask_copy(retmask, cpumask_of(cpu));
586 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
588 return physid_isset(apicid, *map);
591 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
596 static inline int __default_cpu_present_to_apicid(int mps_cpu)
598 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
599 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
605 __default_check_phys_apicid_present(int phys_apicid)
607 return physid_isset(phys_apicid, phys_cpu_present_map);
611 static inline int default_cpu_present_to_apicid(int mps_cpu)
613 return __default_cpu_present_to_apicid(mps_cpu);
617 default_check_phys_apicid_present(int phys_apicid)
619 return __default_check_phys_apicid_present(phys_apicid);
622 extern int default_cpu_present_to_apicid(int mps_cpu);
623 extern int default_check_phys_apicid_present(int phys_apicid);
626 #endif /* CONFIG_X86_LOCAL_APIC */
629 bool apic_id_is_primary_thread(unsigned int id);
631 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
634 extern void irq_enter(void);
635 extern void irq_exit(void);
637 static inline void entering_irq(void)
641 kvm_set_cpu_l1tf_flush_l1d();
644 static inline void entering_ack_irq(void)
650 static inline void ipi_entering_ack_irq(void)
654 kvm_set_cpu_l1tf_flush_l1d();
657 static inline void exiting_irq(void)
662 static inline void exiting_ack_irq(void)
668 extern void ioapic_zap_locks(void);
670 #endif /* _ASM_X86_APIC_H */