arch/x86/include/asm/intel-family.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_INTEL_FAMILY_H
   3 #define _ASM_X86_INTEL_FAMILY_H
   4
   5 /*
   6  * "Big Core" Processors (Branded as Core, Xeon, etc...)
   7  *
   8  * The "_X" parts are generally the EP and EX Xeons, or the
   9  * "Extreme" ones, like Broadwell-E, or Atom microserver.
  10  *
  11  * While adding a new CPUID for a new microarchitecture, add a new
  12  * group to keep logically sorted out in chronological order. Within
  13  * that group keep the CPUID for the variants sorted by model number.
  14  */
  15
  16 /* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
  17 #define INTEL_FAM6_ANY                  X86_MODEL_ANY
  18
  19 #define INTEL_FAM6_CORE_YONAH           0x0E
  20
  21 #define INTEL_FAM6_CORE2_MEROM          0x0F
  22 #define INTEL_FAM6_CORE2_MEROM_L        0x16
  23 #define INTEL_FAM6_CORE2_PENRYN         0x17
  24 #define INTEL_FAM6_CORE2_DUNNINGTON     0x1D
  25
  26 #define INTEL_FAM6_NEHALEM              0x1E
  27 #define INTEL_FAM6_NEHALEM_G            0x1F /* Auburndale / Havendale */
  28 #define INTEL_FAM6_NEHALEM_EP           0x1A
  29 #define INTEL_FAM6_NEHALEM_EX           0x2E
  30
  31 #define INTEL_FAM6_WESTMERE             0x25
  32 #define INTEL_FAM6_WESTMERE_EP          0x2C
  33 #define INTEL_FAM6_WESTMERE_EX          0x2F
  34
  35 #define INTEL_FAM6_SANDYBRIDGE          0x2A
  36 #define INTEL_FAM6_SANDYBRIDGE_X        0x2D
  37 #define INTEL_FAM6_IVYBRIDGE            0x3A
  38 #define INTEL_FAM6_IVYBRIDGE_X          0x3E
  39
  40 #define INTEL_FAM6_HASWELL_CORE         0x3C
  41 #define INTEL_FAM6_HASWELL_X            0x3F
  42 #define INTEL_FAM6_HASWELL_ULT          0x45
  43 #define INTEL_FAM6_HASWELL_GT3E         0x46
  44
  45 #define INTEL_FAM6_BROADWELL_CORE       0x3D
  46 #define INTEL_FAM6_BROADWELL_GT3E       0x47
  47 #define INTEL_FAM6_BROADWELL_X          0x4F
  48 #define INTEL_FAM6_BROADWELL_XEON_D     0x56
  49
  50 #define INTEL_FAM6_SKYLAKE_MOBILE       0x4E
  51 #define INTEL_FAM6_SKYLAKE_DESKTOP      0x5E
  52 #define INTEL_FAM6_SKYLAKE_X            0x55
  53 #define INTEL_FAM6_KABYLAKE_MOBILE      0x8E
  54 #define INTEL_FAM6_KABYLAKE_DESKTOP     0x9E
  55
  56 #define INTEL_FAM6_CANNONLAKE_MOBILE    0x66
  57
  58 #define INTEL_FAM6_ICELAKE_X            0x6A
  59 #define INTEL_FAM6_ICELAKE_XEON_D       0x6C
  60 #define INTEL_FAM6_ICELAKE_DESKTOP      0x7D
  61 #define INTEL_FAM6_ICELAKE_MOBILE       0x7E
  62 #define INTEL_FAM6_ICELAKE_NNPI         0x9D
  63
  64 #define INTEL_FAM6_TIGERLAKE_L          0x8C
  65 #define INTEL_FAM6_TIGERLAKE            0x8D
  66
  67 #define INTEL_FAM6_COMETLAKE            0xA5
  68 #define INTEL_FAM6_COMETLAKE_L          0xA6
  69
  70 #define INTEL_FAM6_ROCKETLAKE           0xA7
  71
  72 /* Hybrid Core/Atom Processors */
  73
  74 #define INTEL_FAM6_LAKEFIELD            0x8A
  75 #define INTEL_FAM6_ALDERLAKE            0x97
  76 #define INTEL_FAM6_ALDERLAKE_L          0x9A
  77 #define INTEL_FAM6_ALDERLAKE_N          0xBE
  78
  79 #define INTEL_FAM6_RAPTORLAKE           0xB7
  80 #define INTEL_FAM6_RAPTORLAKE_P         0xBA
  81 #define INTEL_FAM6_RAPTORLAKE_S         0xBF
  82
  83 /* "Small Core" Processors (Atom) */
  84
  85 #define INTEL_FAM6_ATOM_BONNELL         0x1C /* Diamondville, Pineview */
  86 #define INTEL_FAM6_ATOM_BONNELL_MID     0x26 /* Silverthorne, Lincroft */
  87
  88 #define INTEL_FAM6_ATOM_SALTWELL        0x36 /* Cedarview */
  89 #define INTEL_FAM6_ATOM_SALTWELL_MID    0x27 /* Penwell */
  90 #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
  91
  92 #define INTEL_FAM6_ATOM_SILVERMONT      0x37 /* Bay Trail, Valleyview */
  93 #define INTEL_FAM6_ATOM_SILVERMONT_X    0x4D /* Avaton, Rangely */
  94 #define INTEL_FAM6_ATOM_SILVERMONT_MID  0x4A /* Merriefield */
  95
  96 #define INTEL_FAM6_ATOM_AIRMONT         0x4C /* Cherry Trail, Braswell */
  97 #define INTEL_FAM6_ATOM_AIRMONT_MID     0x5A /* Moorefield */
  98
  99 #define INTEL_FAM6_ATOM_GOLDMONT        0x5C /* Apollo Lake */
 100 #define INTEL_FAM6_ATOM_GOLDMONT_X      0x5F /* Denverton */
 101 #define INTEL_FAM6_ATOM_GOLDMONT_PLUS   0x7A /* Gemini Lake */
 102
 103 #define INTEL_FAM6_ATOM_TREMONT_X       0x86 /* Jacobsville */
 104 #define INTEL_FAM6_ATOM_TREMONT         0x96 /* Elkhart Lake */
 105 #define INTEL_FAM6_ATOM_TREMONT_L       0x9C /* Jasper Lake */
 106
 107 /* Xeon Phi */
 108
 109 #define INTEL_FAM6_XEON_PHI_KNL         0x57 /* Knights Landing */
 110 #define INTEL_FAM6_XEON_PHI_KNM         0x85 /* Knights Mill */
 111
 112 /* Family 5 */
 113 #define INTEL_FAM5_QUARK_X1000          0x09 /* Quark X1000 SoC */
 114
 115 /* Useful macros */
 116 #define INTEL_CPU_FAM_ANY(_family, _model, _driver_data)        \
 117 {                                                               \
 118         .vendor         = X86_VENDOR_INTEL,                     \
 119         .family         = _family,                              \
 120         .model          = _model,                               \
 121         .feature        = X86_FEATURE_ANY,                      \
 122         .driver_data    = (kernel_ulong_t)&_driver_data         \
 123 }
 124
 125 #define INTEL_CPU_FAM6(_model, _driver_data)                    \
 126         INTEL_CPU_FAM_ANY(6, INTEL_FAM6_##_model, _driver_data)
 127
 128 #endif /* _ASM_X86_INTEL_FAMILY_H */