2 * Support of MSI, HPET and DMAR interrupts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Convert to hierarchical irqdomain
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/pci.h>
17 #include <linux/dmar.h>
18 #include <linux/hpet.h>
19 #include <linux/msi.h>
20 #include <asm/irqdomain.h>
21 #include <asm/msidef.h>
23 #include <asm/hw_irq.h>
25 #include <asm/irq_remapping.h>
27 static struct irq_domain *msi_default_domain;
29 static void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg)
31 msg->address_hi = MSI_ADDR_BASE_HI;
34 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
38 ((apic->irq_dest_mode == 0) ?
39 MSI_ADDR_DEST_MODE_PHYSICAL :
40 MSI_ADDR_DEST_MODE_LOGICAL) |
41 MSI_ADDR_REDIRECTION_CPU |
42 MSI_ADDR_DEST_ID(cfg->dest_apicid);
45 MSI_DATA_TRIGGER_EDGE |
46 MSI_DATA_LEVEL_ASSERT |
47 MSI_DATA_DELIVERY_FIXED |
48 MSI_DATA_VECTOR(cfg->vector);
51 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
53 __irq_msi_compose_msg(irqd_cfg(data), msg);
56 static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg)
58 struct msi_msg msg[2] = { [1] = { }, };
60 __irq_msi_compose_msg(cfg, msg);
61 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg);
65 msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force)
67 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd);
68 struct irq_data *parent = irqd->parent_data;
72 /* Save the current configuration */
73 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
76 /* Allocate a new target vector */
77 ret = parent->chip->irq_set_affinity(parent, mask, force);
78 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
82 * For non-maskable and non-remapped MSI interrupts the migration
83 * to a different destination CPU and a different vector has to be
84 * done careful to handle the possible stray interrupt which can be
85 * caused by the non-atomic update of the address/data pair.
87 * Direct update is possible when:
88 * - The MSI is maskable (remapped MSI does not use this code path)).
89 * The quirk bit is not set in this case.
90 * - The new vector is the same as the old vector
91 * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up)
92 * - The interrupt is not yet started up
93 * - The new destination CPU is the same as the old destination CPU
95 if (!irqd_msi_nomask_quirk(irqd) ||
96 cfg->vector == old_cfg.vector ||
97 old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR ||
98 !irqd_is_started(irqd) ||
99 cfg->dest_apicid == old_cfg.dest_apicid) {
100 irq_msi_update_msg(irqd, cfg);
105 * Paranoia: Validate that the interrupt target is the local
108 if (WARN_ON_ONCE(cpu != smp_processor_id())) {
109 irq_msi_update_msg(irqd, cfg);
114 * Redirect the interrupt to the new vector on the current CPU
115 * first. This might cause a spurious interrupt on this vector if
116 * the device raises an interrupt right between this update and the
117 * update to the final destination CPU.
119 * If the vector is in use then the installed device handler will
120 * denote it as spurious which is no harm as this is a rare event
121 * and interrupt handlers have to cope with spurious interrupts
122 * anyway. If the vector is unused, then it is marked so it won't
123 * trigger the 'No irq handler for vector' warning in do_IRQ().
125 * This requires to hold vector lock to prevent concurrent updates to
126 * the affected vector.
131 * Mark the new target vector on the local CPU if it is currently
132 * unused. Reuse the VECTOR_RETRIGGERED state which is also used in
133 * the CPU hotplug path for a similar purpose. This cannot be
134 * undone here as the current CPU has interrupts disabled and
135 * cannot handle the interrupt before the whole set_affinity()
136 * section is done. In the CPU unplug case, the current CPU is
137 * about to vanish and will not handle any interrupts anymore. The
138 * vector is cleaned up when the CPU comes online again.
140 if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector])))
141 this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED);
143 /* Redirect it to the new vector on the local CPU temporarily */
144 old_cfg.vector = cfg->vector;
145 irq_msi_update_msg(irqd, &old_cfg);
147 /* Now transition it to the target CPU */
148 irq_msi_update_msg(irqd, cfg);
151 * All interrupts after this point are now targeted at the new
154 * Drop vector lock before testing whether the temporary assignment
155 * to the local CPU was hit by an interrupt raised in the device,
156 * because the retrigger function acquires vector lock again.
158 unlock_vector_lock();
161 * Check whether the transition raced with a device interrupt and
162 * is pending in the local APICs IRR. It is safe to do this outside
163 * of vector lock as the irq_desc::lock of this interrupt is still
164 * held and interrupts are disabled: The check is not accessing the
165 * underlying vector store. It's just checking the local APIC's
168 if (lapic_vector_set_in_irr(cfg->vector))
169 irq_data_get_irq_chip(irqd)->irq_retrigger(irqd);
175 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
176 * which implement the MSI or MSI-X Capability Structure.
178 static struct irq_chip pci_msi_controller = {
180 .irq_unmask = pci_msi_unmask_irq,
181 .irq_mask = pci_msi_mask_irq,
182 .irq_ack = irq_chip_ack_parent,
183 .irq_retrigger = irq_chip_retrigger_hierarchy,
184 .irq_compose_msi_msg = irq_msi_compose_msg,
185 .irq_set_affinity = msi_set_affinity,
186 .flags = IRQCHIP_SKIP_SET_WAKE |
187 IRQCHIP_AFFINITY_PRE_STARTUP,
190 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
192 struct irq_domain *domain;
193 struct irq_alloc_info info;
195 init_irq_alloc_info(&info, NULL);
196 info.type = X86_IRQ_ALLOC_TYPE_MSI;
199 domain = irq_remapping_get_irq_domain(&info);
201 domain = msi_default_domain;
205 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
208 void native_teardown_msi_irq(unsigned int irq)
210 irq_domain_free_irqs(irq, 1);
213 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
214 msi_alloc_info_t *arg)
216 return arg->msi_hwirq;
219 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
220 msi_alloc_info_t *arg)
222 struct pci_dev *pdev = to_pci_dev(dev);
223 struct msi_desc *desc = first_pci_msi_entry(pdev);
225 init_irq_alloc_info(arg, NULL);
227 if (desc->msi_attrib.is_msix) {
228 arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
230 arg->type = X86_IRQ_ALLOC_TYPE_MSI;
231 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
236 EXPORT_SYMBOL_GPL(pci_msi_prepare);
238 void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
240 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
242 EXPORT_SYMBOL_GPL(pci_msi_set_desc);
244 static struct msi_domain_ops pci_msi_domain_ops = {
245 .get_hwirq = pci_msi_get_hwirq,
246 .msi_prepare = pci_msi_prepare,
247 .set_desc = pci_msi_set_desc,
250 static struct msi_domain_info pci_msi_domain_info = {
251 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
253 .ops = &pci_msi_domain_ops,
254 .chip = &pci_msi_controller,
255 .handler = handle_edge_irq,
256 .handler_name = "edge",
259 void __init arch_init_msi_domain(struct irq_domain *parent)
261 struct fwnode_handle *fn;
266 fn = irq_domain_alloc_named_fwnode("PCI-MSI");
269 pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
272 if (!msi_default_domain) {
273 irq_domain_free_fwnode(fn);
274 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
276 msi_default_domain->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK;
280 #ifdef CONFIG_IRQ_REMAP
281 static struct irq_chip pci_msi_ir_controller = {
282 .name = "IR-PCI-MSI",
283 .irq_unmask = pci_msi_unmask_irq,
284 .irq_mask = pci_msi_mask_irq,
285 .irq_ack = irq_chip_ack_parent,
286 .irq_retrigger = irq_chip_retrigger_hierarchy,
287 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
288 .flags = IRQCHIP_SKIP_SET_WAKE |
289 IRQCHIP_AFFINITY_PRE_STARTUP,
292 static struct msi_domain_info pci_msi_ir_domain_info = {
293 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
294 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
295 .ops = &pci_msi_domain_ops,
296 .chip = &pci_msi_ir_controller,
297 .handler = handle_edge_irq,
298 .handler_name = "edge",
301 struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
302 const char *name, int id)
304 struct fwnode_handle *fn;
305 struct irq_domain *d;
307 fn = irq_domain_alloc_named_id_fwnode(name, id);
310 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
312 irq_domain_free_fwnode(fn);
317 #ifdef CONFIG_DMAR_TABLE
318 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
320 dmar_msi_write(data->irq, msg);
323 static struct irq_chip dmar_msi_controller = {
325 .irq_unmask = dmar_msi_unmask,
326 .irq_mask = dmar_msi_mask,
327 .irq_ack = irq_chip_ack_parent,
328 .irq_set_affinity = msi_domain_set_affinity,
329 .irq_retrigger = irq_chip_retrigger_hierarchy,
330 .irq_compose_msi_msg = irq_msi_compose_msg,
331 .irq_write_msi_msg = dmar_msi_write_msg,
332 .flags = IRQCHIP_SKIP_SET_WAKE |
333 IRQCHIP_AFFINITY_PRE_STARTUP,
336 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
337 msi_alloc_info_t *arg)
342 static int dmar_msi_init(struct irq_domain *domain,
343 struct msi_domain_info *info, unsigned int virq,
344 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
346 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
347 handle_edge_irq, arg->dmar_data, "edge");
352 static struct msi_domain_ops dmar_msi_domain_ops = {
353 .get_hwirq = dmar_msi_get_hwirq,
354 .msi_init = dmar_msi_init,
357 static struct msi_domain_info dmar_msi_domain_info = {
358 .ops = &dmar_msi_domain_ops,
359 .chip = &dmar_msi_controller,
362 static struct irq_domain *dmar_get_irq_domain(void)
364 static struct irq_domain *dmar_domain;
365 static DEFINE_MUTEX(dmar_lock);
366 struct fwnode_handle *fn;
368 mutex_lock(&dmar_lock);
372 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
374 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
377 irq_domain_free_fwnode(fn);
380 mutex_unlock(&dmar_lock);
384 int dmar_alloc_hwirq(int id, int node, void *arg)
386 struct irq_domain *domain = dmar_get_irq_domain();
387 struct irq_alloc_info info;
392 init_irq_alloc_info(&info, NULL);
393 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
395 info.dmar_data = arg;
397 return irq_domain_alloc_irqs(domain, 1, node, &info);
400 void dmar_free_hwirq(int irq)
402 irq_domain_free_irqs(irq, 1);
407 * MSI message composition
409 #ifdef CONFIG_HPET_TIMER
410 static inline int hpet_dev_id(struct irq_domain *domain)
412 struct msi_domain_info *info = msi_get_domain_info(domain);
414 return (int)(long)info->data;
417 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
419 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
422 static struct irq_chip hpet_msi_controller __ro_after_init = {
424 .irq_unmask = hpet_msi_unmask,
425 .irq_mask = hpet_msi_mask,
426 .irq_ack = irq_chip_ack_parent,
427 .irq_set_affinity = msi_domain_set_affinity,
428 .irq_retrigger = irq_chip_retrigger_hierarchy,
429 .irq_compose_msi_msg = irq_msi_compose_msg,
430 .irq_write_msi_msg = hpet_msi_write_msg,
431 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP,
434 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
435 msi_alloc_info_t *arg)
437 return arg->hpet_index;
440 static int hpet_msi_init(struct irq_domain *domain,
441 struct msi_domain_info *info, unsigned int virq,
442 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
444 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
445 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
446 handle_edge_irq, arg->hpet_data, "edge");
451 static void hpet_msi_free(struct irq_domain *domain,
452 struct msi_domain_info *info, unsigned int virq)
454 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
457 static struct msi_domain_ops hpet_msi_domain_ops = {
458 .get_hwirq = hpet_msi_get_hwirq,
459 .msi_init = hpet_msi_init,
460 .msi_free = hpet_msi_free,
463 static struct msi_domain_info hpet_msi_domain_info = {
464 .ops = &hpet_msi_domain_ops,
465 .chip = &hpet_msi_controller,
468 struct irq_domain *hpet_create_irq_domain(int hpet_id)
470 struct msi_domain_info *domain_info;
471 struct irq_domain *parent, *d;
472 struct irq_alloc_info info;
473 struct fwnode_handle *fn;
475 if (x86_vector_domain == NULL)
478 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
482 *domain_info = hpet_msi_domain_info;
483 domain_info->data = (void *)(long)hpet_id;
485 init_irq_alloc_info(&info, NULL);
486 info.type = X86_IRQ_ALLOC_TYPE_HPET;
487 info.hpet_id = hpet_id;
488 parent = irq_remapping_get_ir_irq_domain(&info);
490 parent = x86_vector_domain;
492 hpet_msi_controller.name = "IR-HPET-MSI";
494 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
501 d = msi_create_irq_domain(fn, domain_info, parent);
503 irq_domain_free_fwnode(fn);
509 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
512 struct irq_alloc_info info;
514 init_irq_alloc_info(&info, NULL);
515 info.type = X86_IRQ_ALLOC_TYPE_HPET;
516 info.hpet_data = dev;
517 info.hpet_id = hpet_dev_id(domain);
518 info.hpet_index = dev_num;
520 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);