arch/x86/kernel/apic/x2apic_cluster.c

   1 #include <linux/threads.h>
   2 #include <linux/cpumask.h>
   3 #include <linux/string.h>
   4 #include <linux/kernel.h>
   5 #include <linux/ctype.h>
   6 #include <linux/dmar.h>
   7 #include <linux/cpu.h>
   8
   9 #include <asm/smp.h>
  10 #include <asm/x2apic.h>
  11
  12 static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
  13 static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
  14 static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
  15
  16 static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  17 {
  18         return x2apic_enabled();
  19 }
  20
  21 static inline u32 x2apic_cluster(int cpu)
  22 {
  23         return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
  24 }
  25
  26 static void x2apic_send_IPI(int cpu, int vector)
  27 {
  28         u32 dest = per_cpu(x86_cpu_to_logical_apicid, cpu);
  29
  30         /* x2apic MSRs are special and need a special fence: */
  31         weak_wrmsr_fence();
  32         __x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
  33 }
  34
  35 static void
  36 __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
  37 {
  38         struct cpumask *cpus_in_cluster_ptr;
  39         struct cpumask *ipi_mask_ptr;
  40         unsigned int cpu, this_cpu;
  41         unsigned long flags;
  42         u32 dest;
  43
  44         /* x2apic MSRs are special and need a special fence: */
  45         weak_wrmsr_fence();
  46
  47         local_irq_save(flags);
  48
  49         this_cpu = smp_processor_id();
  50
  51         /*
  52          * We are to modify mask, so we need an own copy
  53          * and be sure it's manipulated with irq off.
  54          */
  55         ipi_mask_ptr = this_cpu_cpumask_var_ptr(ipi_mask);
  56         cpumask_copy(ipi_mask_ptr, mask);
  57
  58         /*
  59          * The idea is to send one IPI per cluster.
  60          */
  61         for_each_cpu(cpu, ipi_mask_ptr) {
  62                 unsigned long i;
  63
  64                 cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu);
  65                 dest = 0;
  66
  67                 /* Collect cpus in cluster. */
  68                 for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) {
  69                         if (apic_dest == APIC_DEST_ALLINC || i != this_cpu)
  70                                 dest |= per_cpu(x86_cpu_to_logical_apicid, i);
  71                 }
  72
  73                 if (!dest)
  74                         continue;
  75
  76                 __x2apic_send_IPI_dest(dest, vector, apic->dest_logical);
  77                 /*
  78                  * Cluster sibling cpus should be discared now so
  79                  * we would not send IPI them second time.
  80                  */
  81                 cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr);
  82         }
  83
  84         local_irq_restore(flags);
  85 }
  86
  87 static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
  88 {
  89         __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
  90 }
  91
  92 static void
  93 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
  94 {
  95         __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
  96 }
  97
  98 static void x2apic_send_IPI_allbutself(int vector)
  99 {
 100         __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
 101 }
 102
 103 static void x2apic_send_IPI_all(int vector)
 104 {
 105         __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
 106 }
 107
 108 static int
 109 x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 110                               const struct cpumask *andmask,
 111                               unsigned int *apicid)
 112 {
 113         u32 dest = 0;
 114         u16 cluster;
 115         int i;
 116
 117         for_each_cpu_and(i, cpumask, andmask) {
 118                 if (!cpumask_test_cpu(i, cpu_online_mask))
 119                         continue;
 120                 dest = per_cpu(x86_cpu_to_logical_apicid, i);
 121                 cluster = x2apic_cluster(i);
 122                 break;
 123         }
 124
 125         if (!dest)
 126                 return -EINVAL;
 127
 128         for_each_cpu_and(i, cpumask, andmask) {
 129                 if (!cpumask_test_cpu(i, cpu_online_mask))
 130                         continue;
 131                 if (cluster != x2apic_cluster(i))
 132                         continue;
 133                 dest |= per_cpu(x86_cpu_to_logical_apicid, i);
 134         }
 135
 136         *apicid = dest;
 137
 138         return 0;
 139 }
 140
 141 static void init_x2apic_ldr(void)
 142 {
 143         unsigned int this_cpu = smp_processor_id();
 144         unsigned int cpu;
 145
 146         per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR);
 147
 148         cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, this_cpu));
 149         for_each_online_cpu(cpu) {
 150                 if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
 151                         continue;
 152                 cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu));
 153                 cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu));
 154         }
 155 }
 156
 157 /*
 158  * At CPU state changes, update the x2apic cluster sibling info.
 159  */
 160 static int x2apic_prepare_cpu(unsigned int cpu)
 161 {
 162         if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL))
 163                 return -ENOMEM;
 164
 165         if (!zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL)) {
 166                 free_cpumask_var(per_cpu(cpus_in_cluster, cpu));
 167                 return -ENOMEM;
 168         }
 169
 170         return 0;
 171 }
 172
 173 static int x2apic_dead_cpu(unsigned int this_cpu)
 174 {
 175         int cpu;
 176
 177         for_each_online_cpu(cpu) {
 178                 if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
 179                         continue;
 180                 cpumask_clear_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu));
 181                 cpumask_clear_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu));
 182         }
 183         free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
 184         free_cpumask_var(per_cpu(ipi_mask, this_cpu));
 185         return 0;
 186 }
 187
 188 static int x2apic_cluster_probe(void)
 189 {
 190         int cpu = smp_processor_id();
 191         int ret;
 192
 193         if (!x2apic_mode)
 194                 return 0;
 195
 196         ret = cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "X2APIC_PREPARE",
 197                                 x2apic_prepare_cpu, x2apic_dead_cpu);
 198         if (ret < 0) {
 199                 pr_err("Failed to register X2APIC_PREPARE\n");
 200                 return 0;
 201         }
 202         cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, cpu));
 203         return 1;
 204 }
 205
 206 static const struct cpumask *x2apic_cluster_target_cpus(void)
 207 {
 208         return cpu_all_mask;
 209 }
 210
 211 /*
 212  * Each x2apic cluster is an allocation domain.
 213  */
 214 static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask,
 215                                              const struct cpumask *mask)
 216 {
 217         /*
 218          * To minimize vector pressure, default case of boot, device bringup
 219          * etc will use a single cpu for the interrupt destination.
 220          *
 221          * On explicit migration requests coming from irqbalance etc,
 222          * interrupts will be routed to the x2apic cluster (cluster-id
 223          * derived from the first cpu in the mask) members specified
 224          * in the mask.
 225          */
 226         if (mask == x2apic_cluster_target_cpus())
 227                 cpumask_copy(retmask, cpumask_of(cpu));
 228         else
 229                 cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu));
 230 }
 231
 232 static struct apic apic_x2apic_cluster __ro_after_init = {
 233
 234         .name                           = "cluster x2apic",
 235         .probe                          = x2apic_cluster_probe,
 236         .acpi_madt_oem_check            = x2apic_acpi_madt_oem_check,
 237         .apic_id_valid                  = x2apic_apic_id_valid,
 238         .apic_id_registered             = x2apic_apic_id_registered,
 239
 240         .irq_delivery_mode              = dest_LowestPrio,
 241         .irq_dest_mode                  = 1, /* logical */
 242
 243         .target_cpus                    = x2apic_cluster_target_cpus,
 244         .disable_esr                    = 0,
 245         .dest_logical                   = APIC_DEST_LOGICAL,
 246         .check_apicid_used              = NULL,
 247
 248         .vector_allocation_domain       = cluster_vector_allocation_domain,
 249         .init_apic_ldr                  = init_x2apic_ldr,
 250
 251         .ioapic_phys_id_map             = NULL,
 252         .setup_apic_routing             = NULL,
 253         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 254         .apicid_to_cpu_present          = NULL,
 255         .check_phys_apicid_present      = default_check_phys_apicid_present,
 256         .phys_pkg_id                    = x2apic_phys_pkg_id,
 257
 258         .get_apic_id                    = x2apic_get_apic_id,
 259         .set_apic_id                    = x2apic_set_apic_id,
 260
 261         .cpu_mask_to_apicid_and         = x2apic_cpu_mask_to_apicid_and,
 262
 263         .send_IPI                       = x2apic_send_IPI,
 264         .send_IPI_mask                  = x2apic_send_IPI_mask,
 265         .send_IPI_mask_allbutself       = x2apic_send_IPI_mask_allbutself,
 266         .send_IPI_allbutself            = x2apic_send_IPI_allbutself,
 267         .send_IPI_all                   = x2apic_send_IPI_all,
 268         .send_IPI_self                  = x2apic_send_IPI_self,
 269
 270         .inquire_remote_apic            = NULL,
 271
 272         .read                           = native_apic_msr_read,
 273         .write                          = native_apic_msr_write,
 274         .eoi_write                      = native_apic_msr_eoi_write,
 275         .icr_read                       = native_x2apic_icr_read,
 276         .icr_write                      = native_x2apic_icr_write,
 277         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 278         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 279 };
 280
 281 apic_driver(apic_x2apic_cluster);