1 #include <linux/export.h>
2 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/random.h>
9 #include <asm/processor.h>
12 #include <asm/spec-ctrl.h>
14 #include <asm/pci-direct.h>
15 #include <asm/delay.h>
18 # include <asm/mmconfig.h>
19 # include <asm/cacheflush.h>
24 static const int amd_erratum_383[];
25 static const int amd_erratum_400[];
26 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
29 * nodes_per_socket: Stores the number of nodes per socket.
30 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
31 * Node Identifiers[10:8]
33 static u32 nodes_per_socket = 1;
35 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
40 WARN_ONCE((boot_cpu_data.x86 != 0xf),
41 "%s should only be used on K8!\n", __func__);
46 err = rdmsr_safe_regs(gprs);
48 *p = gprs[0] | ((u64)gprs[2] << 32);
53 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
57 WARN_ONCE((boot_cpu_data.x86 != 0xf),
58 "%s should only be used on K8!\n", __func__);
65 return wrmsr_safe_regs(gprs);
69 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
70 * misexecution of code under Linux. Owners of such processors should
71 * contact AMD for precise details and a CPU swap.
73 * See http://www.multimania.com/poulot/k6bug.html
74 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
75 * (Publication # 21266 Issue Date: August 1998)
77 * The following test is erm.. interesting. AMD neglected to up
78 * the chip setting when fixing the bug but they also tweaked some
79 * performance at the same time..
82 extern __visible void vide(void);
83 __asm__(".globl vide\n"
84 ".type vide, @function\n"
88 static void init_amd_k5(struct cpuinfo_x86 *c)
92 * General Systems BIOSen alias the cpu frequency registers
93 * of the Elan at 0x000df000. Unfortunately, one of the Linux
94 * drivers subsequently pokes it, and changes the CPU speed.
95 * Workaround : Remove the unneeded alias.
97 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
98 #define CBAR_ENB (0x80000000)
99 #define CBAR_KEY (0X000000CB)
100 if (c->x86_model == 9 || c->x86_model == 10) {
101 if (inl(CBAR) & CBAR_ENB)
102 outl(0 | CBAR_KEY, CBAR);
107 static void init_amd_k6(struct cpuinfo_x86 *c)
111 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
113 if (c->x86_model < 6) {
114 /* Based on AMD doc 20734R - June 2000 */
115 if (c->x86_model == 0) {
116 clear_cpu_cap(c, X86_FEATURE_APIC);
117 set_cpu_cap(c, X86_FEATURE_PGE);
122 if (c->x86_model == 6 && c->x86_stepping == 1) {
123 const int K6_BUG_LOOP = 1000000;
125 void (*f_vide)(void);
128 pr_info("AMD K6 stepping B detected - ");
131 * It looks like AMD fixed the 2.6.2 bug and improved indirect
132 * calls at the same time.
143 if (d > 20*K6_BUG_LOOP)
144 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
146 pr_cont("probably OK (after B9730xxxx).\n");
149 /* K6 with old style WHCR */
150 if (c->x86_model < 8 ||
151 (c->x86_model == 8 && c->x86_stepping < 8)) {
152 /* We can only write allocate on the low 508Mb */
156 rdmsr(MSR_K6_WHCR, l, h);
157 if ((l&0x0000FFFF) == 0) {
159 l = (1<<0)|((mbytes/4)<<1);
160 local_irq_save(flags);
162 wrmsr(MSR_K6_WHCR, l, h);
163 local_irq_restore(flags);
164 pr_info("Enabling old style K6 write allocation for %d Mb\n",
170 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
171 c->x86_model == 9 || c->x86_model == 13) {
172 /* The more serious chips .. */
177 rdmsr(MSR_K6_WHCR, l, h);
178 if ((l&0xFFFF0000) == 0) {
180 l = ((mbytes>>2)<<22)|(1<<16);
181 local_irq_save(flags);
183 wrmsr(MSR_K6_WHCR, l, h);
184 local_irq_restore(flags);
185 pr_info("Enabling new style K6 write allocation for %d Mb\n",
192 if (c->x86_model == 10) {
193 /* AMD Geode LX is model 10 */
194 /* placeholder for any needed mods */
200 static void init_amd_k7(struct cpuinfo_x86 *c)
206 * Bit 15 of Athlon specific MSR 15, needs to be 0
207 * to enable SSE on Palomino/Morgan/Barton CPU's.
208 * If the BIOS didn't enable it already, enable it here.
210 if (c->x86_model >= 6 && c->x86_model <= 10) {
211 if (!cpu_has(c, X86_FEATURE_XMM)) {
212 pr_info("Enabling disabled K7/SSE Support.\n");
213 msr_clear_bit(MSR_K7_HWCR, 15);
214 set_cpu_cap(c, X86_FEATURE_XMM);
219 * It's been determined by AMD that Athlons since model 8 stepping 1
220 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
221 * As per AMD technical note 27212 0.2
223 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
224 rdmsr(MSR_K7_CLK_CTL, l, h);
225 if ((l & 0xfff00000) != 0x20000000) {
226 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
227 l, ((l & 0x000fffff)|0x20000000));
228 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
232 set_cpu_cap(c, X86_FEATURE_K7);
234 /* calling is from identify_secondary_cpu() ? */
239 * Certain Athlons might work (for various values of 'work') in SMP
240 * but they are not certified as MP capable.
242 /* Athlon 660/661 is valid. */
243 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
244 (c->x86_stepping == 1)))
247 /* Duron 670 is valid */
248 if ((c->x86_model == 7) && (c->x86_stepping == 0))
252 * Athlon 662, Duron 671, and Athlon >model 7 have capability
253 * bit. It's worth noting that the A5 stepping (662) of some
254 * Athlon XP's have the MP bit set.
255 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
258 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
259 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
261 if (cpu_has(c, X86_FEATURE_MP))
264 /* If we get here, not a certified SMP capable AMD system. */
267 * Don't taint if we are running SMP kernel on a single non-MP
270 WARN_ONCE(1, "WARNING: This combination of AMD"
271 " processors is not suitable for SMP.\n");
272 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
278 * To workaround broken NUMA config. Read the comment in
279 * srat_detect_node().
281 static int nearby_node(int apicid)
285 for (i = apicid - 1; i >= 0; i--) {
286 node = __apicid_to_node[i];
287 if (node != NUMA_NO_NODE && node_online(node))
290 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
291 node = __apicid_to_node[i];
292 if (node != NUMA_NO_NODE && node_online(node))
295 return first_node(node_online_map); /* Shouldn't happen */
299 static void amd_get_topology_early(struct cpuinfo_x86 *c)
301 if (cpu_has(c, X86_FEATURE_TOPOEXT))
302 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
306 * Fix up cpu_core_id for pre-F17h systems to be in the
307 * [0 .. cores_per_node - 1] range. Not really needed but
308 * kept so as not to break existing setups.
310 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
317 cus_per_node = c->x86_max_cores / nodes_per_socket;
318 c->cpu_core_id %= cus_per_node;
322 * Fixup core topology information for
323 * (1) AMD multi-node processors
324 * Assumption: Number of cores in each internal node is the same.
325 * (2) AMD processors supporting compute units
327 static void amd_get_topology(struct cpuinfo_x86 *c)
330 int cpu = smp_processor_id();
332 /* get information required for multi-node processors */
333 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
334 u32 eax, ebx, ecx, edx;
336 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
338 node_id = ecx & 0xff;
341 c->cu_id = ebx & 0xff;
343 if (c->x86 >= 0x17) {
344 c->cpu_core_id = ebx & 0xff;
346 if (smp_num_siblings > 1)
347 c->x86_max_cores /= smp_num_siblings;
351 * We may have multiple LLCs if L3 caches exist, so check if we
352 * have an L3 cache by looking at the L3 cache CPUID leaf.
354 if (cpuid_edx(0x80000006)) {
355 if (c->x86 == 0x17) {
357 * LLC is at the core complex level.
358 * Core complex id is ApicId[3].
360 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
362 /* LLC is at the node level. */
363 per_cpu(cpu_llc_id, cpu) = node_id;
366 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
369 rdmsrl(MSR_FAM10H_NODE_ID, value);
372 per_cpu(cpu_llc_id, cpu) = node_id;
376 if (nodes_per_socket > 1) {
377 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
378 legacy_fixup_core_id(c);
383 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
384 * Assumes number of cores is a power of two.
386 static void amd_detect_cmp(struct cpuinfo_x86 *c)
389 int cpu = smp_processor_id();
391 bits = c->x86_coreid_bits;
392 /* Low order bits define the core id (index of core in socket) */
393 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
394 /* Convert the initial APIC ID into the socket ID */
395 c->phys_proc_id = c->initial_apicid >> bits;
396 /* use socket ID also for last level cache */
397 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
401 u16 amd_get_nb_id(int cpu)
403 return per_cpu(cpu_llc_id, cpu);
405 EXPORT_SYMBOL_GPL(amd_get_nb_id);
407 u32 amd_get_nodes_per_socket(void)
409 return nodes_per_socket;
411 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
413 static void srat_detect_node(struct cpuinfo_x86 *c)
416 int cpu = smp_processor_id();
418 unsigned apicid = c->apicid;
420 node = numa_cpu_node(cpu);
421 if (node == NUMA_NO_NODE)
422 node = per_cpu(cpu_llc_id, cpu);
425 * On multi-fabric platform (e.g. Numascale NumaChip) a
426 * platform-specific handler needs to be called to fixup some
429 if (x86_cpuinit.fixup_cpu_id)
430 x86_cpuinit.fixup_cpu_id(c, node);
432 if (!node_online(node)) {
434 * Two possibilities here:
436 * - The CPU is missing memory and no node was created. In
437 * that case try picking one from a nearby CPU.
439 * - The APIC IDs differ from the HyperTransport node IDs
440 * which the K8 northbridge parsing fills in. Assume
441 * they are all increased by a constant offset, but in
442 * the same order as the HT nodeids. If that doesn't
443 * result in a usable node fall back to the path for the
446 * This workaround operates directly on the mapping between
447 * APIC ID and NUMA node, assuming certain relationship
448 * between APIC ID, HT node ID and NUMA topology. As going
449 * through CPU mapping may alter the outcome, directly
450 * access __apicid_to_node[].
452 int ht_nodeid = c->initial_apicid;
454 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
455 node = __apicid_to_node[ht_nodeid];
456 /* Pick a nearby node */
457 if (!node_online(node))
458 node = nearby_node(apicid);
460 numa_set_node(cpu, node);
464 static void early_init_amd_mc(struct cpuinfo_x86 *c)
469 /* Multi core CPU? */
470 if (c->extended_cpuid_level < 0x80000008)
473 ecx = cpuid_ecx(0x80000008);
475 c->x86_max_cores = (ecx & 0xff) + 1;
477 /* CPU telling us the core id bits shift? */
478 bits = (ecx >> 12) & 0xF;
480 /* Otherwise recompute */
482 while ((1 << bits) < c->x86_max_cores)
486 c->x86_coreid_bits = bits;
490 static void bsp_init_amd(struct cpuinfo_x86 *c)
495 unsigned long long tseg;
498 * Split up direct mapping around the TSEG SMM area.
499 * Don't do it for gbpages because there seems very little
500 * benefit in doing so.
502 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
503 unsigned long pfn = tseg >> PAGE_SHIFT;
505 pr_debug("tseg: %010llx\n", tseg);
506 if (pfn_range_is_mapped(pfn, pfn + 1))
507 set_memory_4k((unsigned long)__va(tseg), 1);
512 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
515 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
518 rdmsrl(MSR_K7_HWCR, val);
519 if (!(val & BIT(24)))
520 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
524 if (c->x86 == 0x15) {
525 unsigned long upperbit;
528 cpuid = cpuid_edx(0x80000005);
529 assoc = cpuid >> 16 & 0xff;
530 upperbit = ((cpuid >> 24) << 10) / assoc;
532 va_align.mask = (upperbit - 1) & PAGE_MASK;
533 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
535 /* A random value per boot for bit slice [12:upper_bit) */
536 va_align.bits = get_random_int() & va_align.mask;
539 if (cpu_has(c, X86_FEATURE_MWAITX))
542 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
545 ecx = cpuid_ecx(0x8000001e);
546 nodes_per_socket = ((ecx >> 8) & 7) + 1;
547 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
550 rdmsrl(MSR_FAM10H_NODE_ID, value);
551 nodes_per_socket = ((value >> 3) & 7) + 1;
554 if (c->x86 >= 0x15 && c->x86 <= 0x17) {
558 case 0x15: bit = 54; break;
559 case 0x16: bit = 33; break;
560 case 0x17: bit = 10; break;
564 * Try to cache the base value so further operations can
565 * avoid RMW. If that faults, do not enable SSBD.
567 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
568 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
569 setup_force_cpu_cap(X86_FEATURE_SSBD);
570 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
575 static void early_init_amd(struct cpuinfo_x86 *c)
579 early_init_amd_mc(c);
582 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
583 * with P/T states and does not stop in deep C-states
585 if (c->x86_power & (1 << 8)) {
586 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
587 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
588 if (!check_tsc_unstable())
589 set_sched_clock_stable();
592 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
593 if (c->x86_power & BIT(12))
594 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
597 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
599 /* Set MTRR capability flag if appropriate */
601 if (c->x86_model == 13 || c->x86_model == 9 ||
602 (c->x86_model == 8 && c->x86_stepping >= 8))
603 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
605 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
607 * ApicID can always be treated as an 8-bit value for AMD APIC versions
608 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
609 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
612 if (boot_cpu_has(X86_FEATURE_APIC)) {
614 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
615 else if (c->x86 >= 0xf) {
616 /* check CPU config space for extended APIC ID */
619 val = read_pci_config(0, 24, 0, 0x68);
620 if ((val >> 17 & 0x3) == 0x3)
621 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
627 * This is only needed to tell the kernel whether to use VMCALL
628 * and VMMCALL. VMMCALL is never executed except under virt, so
629 * we can set it unconditionally.
631 set_cpu_cap(c, X86_FEATURE_VMMCALL);
633 /* F16h erratum 793, CVE-2013-6885 */
634 if (c->x86 == 0x16 && c->x86_model <= 0xf)
635 msr_set_bit(MSR_AMD64_LS_CFG, 15);
638 * Check whether the machine is affected by erratum 400. This is
639 * used to select the proper idle routine and to enable the check
640 * whether the machine is affected in arch_post_acpi_init(), which
641 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
643 if (cpu_has_amd_erratum(c, amd_erratum_400))
644 set_cpu_bug(c, X86_BUG_AMD_E400);
647 /* Re-enable TopologyExtensions if switched off by BIOS */
648 if (c->x86 == 0x15 &&
649 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
650 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
652 if (msr_set_bit(0xc0011005, 54) > 0) {
653 rdmsrl(0xc0011005, value);
654 if (value & BIT_64(54)) {
655 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
656 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
661 amd_get_topology_early(c);
664 static void init_amd_k8(struct cpuinfo_x86 *c)
669 /* On C+ stepping K8 rep microcode works well for copy/memset */
670 level = cpuid_eax(1);
671 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
672 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
675 * Some BIOSes incorrectly force this feature, but only K8 revision D
676 * (model = 0x14) and later actually support it.
677 * (AMD Erratum #110, docId: 25759).
679 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
680 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
681 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
682 value &= ~BIT_64(32);
683 wrmsrl_amd_safe(0xc001100d, value);
687 if (!c->x86_model_id[0])
688 strcpy(c->x86_model_id, "Hammer");
692 * Disable TLB flush filter by setting HWCR.FFDIS on K8
693 * bit 6 of msr C001_0015
695 * Errata 63 for SH-B3 steppings
696 * Errata 122 for all steppings (F+ have it disabled by default)
698 msr_set_bit(MSR_K7_HWCR, 6);
700 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
703 static void init_amd_gh(struct cpuinfo_x86 *c)
706 /* do this for boot cpu */
707 if (c == &boot_cpu_data)
708 check_enable_amd_mmconf_dmi();
710 fam10h_check_enable_mmcfg();
714 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
715 * is always needed when GART is enabled, even in a kernel which has no
716 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
717 * If it doesn't, we do it here as suggested by the BKDG.
719 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
721 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
724 * On family 10h BIOS may not have properly enabled WC+ support, causing
725 * it to be converted to CD memtype. This may result in performance
726 * degradation for certain nested-paging guests. Prevent this conversion
727 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
729 * NOTE: we want to use the _safe accessors so as not to #GP kvm
730 * guests on older kvm hosts.
732 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
734 if (cpu_has_amd_erratum(c, amd_erratum_383))
735 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
738 static void init_amd_ln(struct cpuinfo_x86 *c)
741 * Apply erratum 665 fix unconditionally so machines without a BIOS
744 msr_set_bit(MSR_AMD64_DE_CFG, 31);
747 static bool rdrand_force;
749 static int __init rdrand_cmdline(char *str)
754 if (!strcmp(str, "force"))
761 early_param("rdrand", rdrand_cmdline);
763 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
766 * Saving of the MSR used to hide the RDRAND support during
767 * suspend/resume is done by arch/x86/power/cpu.c, which is
768 * dependent on CONFIG_PM_SLEEP.
770 if (!IS_ENABLED(CONFIG_PM_SLEEP))
774 * The nordrand option can clear X86_FEATURE_RDRAND, so check for
775 * RDRAND support using the CPUID function directly.
777 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
780 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
783 * Verify that the CPUID change has occurred in case the kernel is
784 * running virtualized and the hypervisor doesn't support the MSR.
786 if (cpuid_ecx(1) & BIT(30)) {
787 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
791 clear_cpu_cap(c, X86_FEATURE_RDRAND);
792 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
795 static void init_amd_jg(struct cpuinfo_x86 *c)
798 * Some BIOS implementations do not restore proper RDRAND support
799 * across suspend and resume. Check on whether to hide the RDRAND
800 * instruction support via CPUID.
802 clear_rdrand_cpuid_bit(c);
805 static void init_amd_bd(struct cpuinfo_x86 *c)
810 * The way access filter has a performance penalty on some workloads.
811 * Disable it on the affected CPUs.
813 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
814 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
816 wrmsrl_safe(MSR_F15H_IC_CFG, value);
821 * Some BIOS implementations do not restore proper RDRAND support
822 * across suspend and resume. Check on whether to hide the RDRAND
823 * instruction support via CPUID.
825 clear_rdrand_cpuid_bit(c);
828 static void init_amd_zn(struct cpuinfo_x86 *c)
830 set_cpu_cap(c, X86_FEATURE_ZEN);
833 * Fix erratum 1076: CPB feature bit not being set in CPUID.
834 * Always set it, except when running under a hypervisor.
836 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB))
837 set_cpu_cap(c, X86_FEATURE_CPB);
840 static void init_amd(struct cpuinfo_x86 *c)
847 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
848 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
850 clear_cpu_cap(c, 0*32+31);
853 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
855 /* get apicid instead of initial apic id from cpuid */
856 c->apicid = hard_smp_processor_id();
858 /* K6s reports MCEs but don't actually have all the MSRs */
860 clear_cpu_cap(c, X86_FEATURE_MCE);
863 case 4: init_amd_k5(c); break;
864 case 5: init_amd_k6(c); break;
865 case 6: init_amd_k7(c); break;
866 case 0xf: init_amd_k8(c); break;
867 case 0x10: init_amd_gh(c); break;
868 case 0x12: init_amd_ln(c); break;
869 case 0x15: init_amd_bd(c); break;
870 case 0x16: init_amd_jg(c); break;
871 case 0x17: init_amd_zn(c); break;
874 /* Enable workaround for FXSAVE leak */
876 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
878 cpu_detect_cache_sizes(c);
883 init_amd_cacheinfo(c);
886 set_cpu_cap(c, X86_FEATURE_K8);
888 if (cpu_has(c, X86_FEATURE_XMM2)) {
889 unsigned long long val;
893 * A serializing LFENCE has less overhead than MFENCE, so
894 * use it for execution serialization. On families which
895 * don't have that MSR, LFENCE is already serializing.
896 * msr_set_bit() uses the safe accessors, too, even if the MSR
899 msr_set_bit(MSR_AMD64_DE_CFG,
900 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
903 * Verify that the MSR write was successful (could be running
904 * under a hypervisor) and only then assume that LFENCE is
907 ret = rdmsrl_safe(MSR_AMD64_DE_CFG, &val);
908 if (!ret && (val & MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)) {
909 /* A serializing LFENCE stops RDTSC speculation */
910 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
912 /* MFENCE stops RDTSC speculation */
913 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
918 * Family 0x12 and above processors have APIC timer
919 * running in deep C states.
922 set_cpu_cap(c, X86_FEATURE_ARAT);
924 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
926 /* 3DNow or LM implies PREFETCHW */
927 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
928 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
929 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
931 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
932 if (!cpu_has(c, X86_FEATURE_XENPV))
933 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
937 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
939 /* AMD errata T13 (order #21922) */
942 if (c->x86_model == 3 && c->x86_stepping == 0)
944 /* Tbird rev A1/A2 */
945 if (c->x86_model == 4 &&
946 (c->x86_stepping == 0 || c->x86_stepping == 1))
953 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
955 u32 ebx, eax, ecx, edx;
961 if (c->extended_cpuid_level < 0x80000006)
964 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
966 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
967 tlb_lli_4k[ENTRIES] = ebx & mask;
970 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
971 * characteristics from the CPUID function 0x80000005 instead.
974 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
978 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
979 if (!((eax >> 16) & mask))
980 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
982 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
984 /* a 4M entry uses two 2M entries */
985 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
987 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
990 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
991 tlb_lli_2m[ENTRIES] = 1024;
993 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
994 tlb_lli_2m[ENTRIES] = eax & 0xff;
997 tlb_lli_2m[ENTRIES] = eax & mask;
999 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1002 static const struct cpu_dev amd_cpu_dev = {
1004 .c_ident = { "AuthenticAMD" },
1005 #ifdef CONFIG_X86_32
1007 { .family = 4, .model_names =
1010 [7] = "486 DX/2-WB",
1012 [9] = "486 DX/4-WB",
1018 .legacy_cache_size = amd_size_cache,
1020 .c_early_init = early_init_amd,
1021 .c_detect_tlb = cpu_detect_tlb_amd,
1022 .c_bsp_init = bsp_init_amd,
1024 .c_x86_vendor = X86_VENDOR_AMD,
1027 cpu_dev_register(amd_cpu_dev);
1030 * AMD errata checking
1032 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1033 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1034 * have an OSVW id assigned, which it takes as first argument. Both take a
1035 * variable number of family-specific model-stepping ranges created by
1036 * AMD_MODEL_RANGE().
1040 * const int amd_erratum_319[] =
1041 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1042 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1043 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1046 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1047 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1048 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1049 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1050 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1051 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1052 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1054 static const int amd_erratum_400[] =
1055 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1056 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1058 static const int amd_erratum_383[] =
1059 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1062 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1064 int osvw_id = *erratum++;
1068 if (osvw_id >= 0 && osvw_id < 65536 &&
1069 cpu_has(cpu, X86_FEATURE_OSVW)) {
1072 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1073 if (osvw_id < osvw_len) {
1076 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1078 return osvw_bits & (1ULL << (osvw_id & 0x3f));
1082 /* OSVW unavailable or ID unknown, match family-model-stepping range */
1083 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1084 while ((range = *erratum++))
1085 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1086 (ms >= AMD_MODEL_RANGE_START(range)) &&
1087 (ms <= AMD_MODEL_RANGE_END(range)))
1093 void set_dr_addr_mask(unsigned long mask, int dr)
1095 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1100 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1105 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);